JPS6246552A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve controllability and reliability by a method wherein a twin type CMOS is built without forming a bulge along the boundary between a P-type well region and N-type well region adjoining each other. CONSTITUTION:The quantity d1, which is the result of side etching, may easily be controlled because it is determined in proportion to the etching time. For the formation of a first well region, impurity ions are implanted with a resist pattern 8 serving as a blocking mask. The resist pattern 8 is removed, whereafter a selective oxidation process is performed with a patterned oxidation- resistant film 7 serving as a mask. A second oxide film 5 is formed, its ends forming bird's beaks going into under the oxidation-resistant film 7. The quantity d2 representing the dimension of the bird's beak penetration is dependent upon the conditions of oxidation and upon the thickness of the oxidation- resistant film 7, which ensures excellent controllability over the quantity d2. This results in a discharge of separation between the first and second well regions that is the sum of the quantities d1 and d2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a complementary MO8 semiconductor device, and particularly to an improvement in a method for forming a well diffusion layer in a twin-tub type complementary MO8 semiconductor device.

[Technical background of the invention and its problems] A complementary MO3 semiconductor device (0MO8) has a structure in which a P-channel MO8FET (P-MOSFET) and an N-channel MO8FET (N-MOSFET) are formed on one semiconductor substrate. Therefore, for example, when manufacturing 0MO8 using an N-type silicon substrate, a P-type well region is required to form an N-MOFET, and when a P-type substrate is used, a P-type well region is required to form a P-MOSFET. An N-type well region is required.Furthermore, recently, 0MO8 (hereinafter referred to as twin-tub type) has been manufactured in which the substrate concentration is lowered and both a P-type well region and an N-type well region are provided.

FIG. 3 (A> is a diagram showing a well region in an example of a twin-tub type CMO8, in which 1 is an N-type silicon substrate,
2 indicates a P-type well region, and 3 indicates an N-type well region. In the twin-tub type of this example, the impurity concentration of the substrate region forming the P-MOSFET can be controlled with high precision compared to the case of only P-type well region 2, and the edge boundary of the P-type well region is vertically aligned. This has the advantage that standby leakage current can be suppressed.

By the way, if the impurity concentrations of the P-type well region 2 and the N-type well region 3 have an equal distribution in the depth direction, the boundaries of both well regions are approximately perpendicular as shown in FIG. When the N-type well region 3 is different, for example, when the N-type well region 3 is formed shallowly, the P-type well region 2 goes around under the N-type well region 3, forming a so-called bulge 4, as shown in FIG. 3(8). As a result of the electric field flux generated by the presence of the bulge 4, an impurity region is formed in one well region and the other well #4 region, as shown by the arrows in FIG. 4(A) and (B). A problem arises in that the punch-through withstand voltage between the two is deteriorated.

Therefore, in order to avoid the occurrence of such bulges, the method shown in Fig. 5 has been proposed (1984 IE
DM newsletter).

In this method, for example, when forming the P-type well region 2 in a thermal oxidation step after boron ion implantation, a high-pressure oxidation method is used to remove the bird's beak of oxidation 1!15 that is formed using a normal oxidation method. Case (indicated by the broken line in the figure)
It has the following meanings:

That is, the oxide 115 formed at this time is used as a blocking mask in the subsequent ion implantation of phosphorus to form the N-type well region 3 (hereinafter, this oxide 115 will be referred to as masking oxide). Therefore, by extending the bird's beak of the masking oxide 5, the phosphorus ion implantation region for the N-type well region 3 is separated from the P-type well region 2, thereby preventing the occurrence of a bulge.

However, since the high-pressure oxidation method used in this method is still a special process, there are problems in that it is inferior in controllability and reliability compared to the conventional oxidation method, which has already been established as a process through the accumulation of a wealth of technology.

[Object of the invention].

The present invention has been made in view of the above circumstances, and uses only conventional highly reliable processes to
A twin-tub type 0MO8 can be manufactured without forming a bulge at the boundary between the type well region and the N-type well region.
Furthermore, the present invention aims to provide a manufacturing method that can greatly simplify the manufacturing process.

[Summary of the invention]

A method for manufacturing a semiconductor device according to the present invention includes the steps of forming a first oxide film on the surface of a semiconductor substrate of a first conductivity type, and then stacking an oxidation-resistant film thereon, and forming a twin tab. An oxidation-resistant film pattern is formed by forming a resist pattern having an opening on one of the planned well regions, and etching the oxidation-resistant film by an isotropic etching process using the resist pattern as a mask. and receding the edge of the oxidation-resistant film pattern to the inside of the edge of the resist pattern by side etching, and using the resist pattern as a blocking mask to form a first conductivity type impurity or a second conductivity type impurity. A step of ion-implanting a conductive type impurity into the semiconductor substrate, and after removing the resist pattern, selectively oxidizing the surface of the semiconductor substrate using the oxidation-resistant film pattern as a mask, the impurity is ion-implanted onto the surface of the ion-implanted region. forming a second thermal oxide film and activating the impurities at the same time to form a first well region constituting a twin tub; and after removing the oxidation-resistant film pattern, The first well region is formed by ion-implanting an impurity of a conductivity type opposite to that of the impurity that formed the first well region using the film as a mask, and activating the ion-implanted impurity by heat treatment. The method is characterized by comprising steps of forming a second well region of opposite conductivity type and forming twin tabs.

In the present invention, by side-etching the oxidation-resistant film pattern and receding its fraction inside the resist pattern, a masking oxide is formed by a normal selective oxidation method without using a high-pressure oxidation method. Where I was
The effect obtained is similar to that of the conventional case, and the effect will be explained with reference to FIGS. 1(A) and 1(B) as follows.

FIG. 1A shows a state in which the oxidation-resistant film has been patterned and further side-etched. In the same figure,
1 is a semiconductor substrate, 6 is a first oxide film, 7 is an oxidation-resistant film pattern, and 8 is a resist pattern. dl indicates the amount of side etching, and d2 is proportional to the etching time, so it can be easily controlled. In this state, using the resist pattern 8 as a blocking mask, impurity ions for forming the first well region are implanted, and after removing the resist pattern 8, selective oxidation is performed using the oxidation-resistant film pattern 7 as a mask. As a result, a second oxide film (masking oxide) 5 is formed as shown in FIG. Become. This erosion fIid2 is also determined by the oxidation conditions and the thickness of the oxidation-resistant gI7, so it can be easily controlled. As a result, the distance from the edge of the resist pattern 8 to the tip of the bird's beak (d10d
z) can be completely controlled, and is equivalent to elongating the bird's beak by dl by high-pressure oxidation. Namely, the first well! The ion implantation regions of the I region and the second well region are separated by the sum of dl and d2.

To explain with a more specific example, when patterning a silicon nitride film with a thickness of 2500 mm using CDE, d1 = 0.
．． 8. is, when forming a masking oxide with a film thickness of 8500 mm at 1000° C., d2-0.8#, so at this time dl +62-1.6 Hm. The lateral diffusion length in the first well region with a junction depth of 2.0p is 1.2 tones, and the lateral diffusion length in the second well region with the same impurity concentration as the substrate at 0.6 ua. Approximately 0.4
-, the magnitude of this dl +62 corresponds to the required length.

[Embodiments of the invention]

An embodiment of the present invention using a P-type substrate will be described below.

(1) By thermally oxidizing the surface of the P-type silicon substrate 11, a pad oxide film 12 with a thickness of 1000 nm is formed (
(Illustrated in FIG. 2(A)).

+2) Next, L PCVDlk - film thickness 2500
Person (7) Deposit silicon nitride film 13 (Fig. 2<8
). At this time, stress is applied by the silicon nitride film 13, but since the stress applied to the substrate 11 is superimposed by the intervening pad oxide film 12, distortion in the substrate and formation of defects can be prevented. I can do it.

(3) Next, a photoresist is applied, exposed and developed to form a resist pattern 14 having an opening above the planned N-type well region (FIG. 2(C))
(Illustrated).

(4) Next, by an isotropic etching process such as CDE (chemical dry etching), the silicon nitride film 13 is etched using the resist pattern 14 as a mask.
pattern. By continuing the etching further, side etching of about 0.8 mm is caused in the silicon nitride film pattern (as shown in FIG. 2(D)).

(2) Next, using the resist pattern 14 as a blocking mask, phosphorus ions are implanted to form an N-type well region. In the figure, 15 indicates a phosphorus ion-implanted layer (second
Figure (E) (Illustrated).

(6) Next, after removing the resist pattern 14, selective oxidation is performed using the silicon nitride film 13 as an oxidation-resistant mask to form a masking oxide 16 with a thickness of about 9,000 mm (as shown in FIG. 2(F)). . At this time, the previously ion-implanted phosphorus is activated, and an N-type diffusion layer 17 is formed.

(7) Next, silicon nitride l! After removing 13,
By re-diffusing phosphorus in the N-type diffusion layer 17 through high-temperature heat treatment and performing slapping, an N-type well region 18 with a junction depth of approximately 2 urrr is formed (as shown in FIG. 2(G)).

(8) Next, by implanting boron ions using the masking oxide 16 as a blocking mask,
A boron ion implantation layer 19 is selectively formed in a portion where a P-type well region is to be formed (as shown in FIG. 2()-1).

(9) Next, after removing the masking oxide 16 by etching in an N84F solution, an element isolation oxide film 21 is formed by selective oxidation.

Next, a P-MOSFET is installed in the N-type well region and an N-MOFE is installed in the P-type well region using the usual 0MO8 process.
After forming the T, an interlayer insulating pIA 22 is deposited, a contact hole for leading out the electrode is formed, a wiring 23 made of AI/St alloy, etc. is formed, and a passivation insulating film 24 is further deposited to complete the 0MO8 device ( Figure 2 (
1) As shown).

According to the above embodiment, a twin-tub type 0MO8 is formed without forming a bulge at the boundary between both well regions 18 and 20.
was able to be manufactured, and the bunch-through withstand voltage was improved. In addition, since the concentration profile in both well regions 18 and 20 can be set relatively freely, the MOS
A well can also be formed to serve as the threshold value IIIwJ of the FET.

Therefore, it has become possible to simplify the manufacturing process.

In the above example, after forming a masking oxide, impurities are thermally diffused at high temperature to form an N-type well region with a junction depth of 2*, but impurity ions are not implanted for a P-type well region. This diffusion step may be carried out after that. In that case, it is necessary to adjust the amount of side etching of the silicon nitride film, taking into consideration the diffusion coefficient and concentration in silicon of the impurity elements constituting the two well regions.

Furthermore, in the above embodiment, the thermal diffusion for forming the P-type well region is automatically performed in the heat treatment step included in the normal 0MO8 process, but after ion implantation for the P-type well region, A separate diffusion step may be added if necessary. In that case, if the depth at which the impurity concentration of the P-type well region is equal to the concentration of the P-type substrate is 1p, and the junction depth of the N-type well region is 2p, the silicon nitride film 13 It is necessary to increase the side etching amount to 1.0-. This may require the pad oxide film to become thicker.

In addition, the film thickness of the masking oxide 16 and the film thickness of the silicon nitride film 13 may be changed from the values shown in the above embodiment depending on other conditions. That is, masking oxide 16! ! The J thickness is determined from firstly the thickness required as a mask for ion implantation and secondly from the amount of extension of the bird's beak. Therefore, when performing highly accelerated ion implantation or when it is desired to further widen the distance between each ion implantation region in both well regions, the thickness of the masking oxide film may become even thicker, and vice versa.

On the other hand, the thickness of the silicon nitride film 13 is determined by the bird's beak length of the masking oxide 16 and the gloss of defects caused by distortion to the substrate, and if the masking oxide is extremely thick, it may be thinner than the value in the above example. You can get it and vice versa.

Further, in the above embodiment, the N-type well region 18 is formed first, but the N-type well region may be formed after the P-type well region is formed first. Of course, the present invention can be similarly applied even if an N-type substrate is used.

〔Effect of the invention〕

As described in detail above, according to the present invention, a bulge is formed at the boundaries of adjacent P-type well regions and N-type well regions by using only conventional and highly reliable processes without using special processes such as high-pressure oxidation. It is possible to produce a twin-tub type 0MO8 without forming a pore, and the production process can be greatly simplified, resulting in remarkable effects.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view for explaining the operation of the main steps of the present invention, Fig. 2 is a cross-sectional view showing the manufacturing process according to an embodiment of the present invention in order, and Fig. 3 is a cross-sectional view showing a twin tab. , FIG. 4 is an explanatory diagram showing a problem in a twin tub where a bulge has occurred, and FIG. 5 is a sectional view for explaining a conventional method for avoiding the occurrence of a bulge in the twin tub CMO8. DESCRIPTION OF SYMBOLS 11... P-type silicon substrate, 12... Pad oxide, 13... Silicon nitride film, 14... Resist pattern, 15... Hot ion implantation layer, 16... Masking oxide, 17...・N-type diffusion layer, 18...
N-type well region, 19... boron ion implantation layer, 20
...P-type well region, 21...Element isolation oxide film, 2
2... Interlayer insulating film, 23... AI/Si wiring applicant's agent, patent attorney Takehiko Suzue' 2nd C (A) 2nd cause (B) Figure 2 (C) Figure 2 (D) Figure 2 (I) Figure 3a (A) Figure 3 (B) Figure 4 (A) Figure 4 (B) Figure 5

Claims (3)

[Claims] (1) After forming a first oxide film on the surface of a semiconductor substrate of a first conductivity type, a step of stacking and depositing an oxidation-resistant film thereon;
A process of forming a resist pattern having an opening on one of the well regions forming the twin tub, and etching the oxidation-resistant film using an isotropic etching process using the resist pattern as a mask. forming a oxidation-resistant film pattern, and receding the edge of the oxidation-resistant film pattern inward from the edge of the resist pattern by side etching; A step of ion-implanting an impurity or a second conductivity type impurity into the semiconductor substrate, and after removing the resist pattern,
By selectively oxidizing the semiconductor substrate surface using the oxidation-resistant film pattern as a mask, a second thermal oxide film is formed on the surface of the impurity ion implantation region, and at the same time, the impurity is activated to form a twin tab. A step of forming a first well region, and after removing the oxidation-resistant film pattern, using the second thermal oxide film as a mask, impurities of a conductivity type opposite to those that formed the first well region are added. The method includes a step of implanting ions, and a step of activating the implanted impurities by heat treatment to form a second well region having a conductivity type opposite to that of the first well region, thereby forming a twin tab. A method for manufacturing a semiconductor device, characterized in that: (2) The semiconductor device according to claim (1), wherein after forming the first well region, a heat treatment step is further performed to deepen the first well region. Production method. (3) The semiconductor device according to claim (1), wherein the heat treatment for forming the second well region is also used as a heat treatment step included in a subsequent normal manufacturing process. Production method.