JPS6247227U - - Google Patents
Info
- Publication number
- JPS6247227U JPS6247227U JP13743885U JP13743885U JPS6247227U JP S6247227 U JPS6247227 U JP S6247227U JP 13743885 U JP13743885 U JP 13743885U JP 13743885 U JP13743885 U JP 13743885U JP S6247227 U JPS6247227 U JP S6247227U
- Authority
- JP
- Japan
- Prior art keywords
- link
- gate control
- control circuit
- circuit
- service unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000605 extraction Methods 0.000 claims description 3
- 239000000284 extract Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図はこの考案の一実施例による時分割多重
通信装置のブロツク図、第２図は従来の時分割多
重通信装置のブロツク図である。
１はＤＳＵ、２はＣＴ、４はクロツク抽出回路
、５はゲート制御回路、６はパターン発生回路、
７はバス。なお、図中、同一符号は同一、又は相
当部分を示す。
FIG. 1 is a block diagram of a time division multiplex communication device according to an embodiment of this invention, and FIG. 2 is a block diagram of a conventional time division multiplex communication device. 1 is a DSU, 2 is a CT, 4 is a clock extraction circuit, 5 is a gate control circuit, 6 is a pattern generation circuit,
7 is a bus. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
・ユニツトと、前記各リンク毎に設けられて前記
デイジタル・サービス・ユニツトから入つてきた
受信情報のなかからそれぞれクロツク情報を抽出
するクロツク抽出回路と、前記各リンク毎に前記
各クロツク抽出回路の出力端にそれぞれ設けられ
たゲート制御回路と、前記各リンク毎の前記各ゲ
ート制御回路に共通のバスを介して接続されて該
ゲート制御回路を制御することにより前記各リン
クから一系統のクロツクを取り出すパターン発生
回路とを備えた時分割多重通信装置。 a digital service unit provided for each link; a clock extraction circuit provided for each link for extracting clock information from received information received from the digital service unit; A gate control circuit provided at the output end of each clock extraction circuit for each link, and connected to each gate control circuit for each link via a common bus to control the gate control circuit. A time division multiplex communication device comprising a pattern generation circuit that extracts one system of clocks from each of the links.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13743885U JPS6247227U (en) | 1985-09-10 | 1985-09-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13743885U JPS6247227U (en) | 1985-09-10 | 1985-09-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6247227U true JPS6247227U (en) | 1987-03-23 |
Family
ID=31041490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13743885U Pending JPS6247227U (en) | 1985-09-10 | 1985-09-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6247227U (en) |
-
1985
- 1985-09-10 JP JP13743885U patent/JPS6247227U/ja active Pending
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