JPS6247232U - - Google Patents

Info

Publication number
JPS6247232U
JPS6247232U JP13793685U JP13793685U JPS6247232U JP S6247232 U JPS6247232 U JP S6247232U JP 13793685 U JP13793685 U JP 13793685U JP 13793685 U JP13793685 U JP 13793685U JP S6247232 U JPS6247232 U JP S6247232U
Authority
JP
Japan
Prior art keywords
input terminal
operational amplifier
amplifier circuit
voltage source
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13793685U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13793685U priority Critical patent/JPS6247232U/ja
Publication of JPS6247232U publication Critical patent/JPS6247232U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Manipulation Of Pulses (AREA)
  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案実施例の比較回路の回路図、
第2図a,bはこの考案実施例の比較回路の動作
を説明する電圧図、第3図はこの考案を適用した
リーダーテープ部検出回路図、第4図は従来の比
較回路の回路図、第5図a,bは従来の比較回路
の動作を説明する電圧図である。 1は演算増幅回路、2は信号入力端子、4aは
抵抗、前記他方の入力端と接地間に接続された4
bはコンデンサー、4は充放電回路、5は直流電
圧源である。
FIG. 1 is a circuit diagram of a comparison circuit according to an embodiment of this invention.
Figures 2a and b are voltage diagrams explaining the operation of the comparator circuit according to the embodiment of this invention, Figure 3 is a leader tape detection circuit diagram to which this invention is applied, and Figure 4 is a circuit diagram of a conventional comparison circuit. FIGS. 5a and 5b are voltage diagrams illustrating the operation of a conventional comparator circuit. 1 is an operational amplifier circuit, 2 is a signal input terminal, 4a is a resistor, and 4 is connected between the other input terminal and ground.
b is a capacitor, 4 is a charging/discharging circuit, and 5 is a DC voltage source.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 演算増幅回路1と、当該演算増幅回路1の一方
の入力端に接続された信号入力端子2と、前記演
算増幅回路1の他方の入力端とB電圧源間に接続
された抵抗4aと前記他方の入力端と接地間に接
続されたコンデンサー4bよりなる充放電回路4
と、前記信号入力端子2と前記他方の入力端間に
接続された直流電圧源5を具備することを特徴と
する比較回路。
an operational amplifier circuit 1; a signal input terminal 2 connected to one input terminal of the operational amplifier circuit 1; a resistor 4a connected between the other input terminal of the operational amplifier circuit 1 and voltage source B; A charging/discharging circuit 4 consisting of a capacitor 4b connected between the input terminal of the
and a DC voltage source 5 connected between the signal input terminal 2 and the other input terminal.
JP13793685U 1985-09-09 1985-09-09 Pending JPS6247232U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13793685U JPS6247232U (en) 1985-09-09 1985-09-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13793685U JPS6247232U (en) 1985-09-09 1985-09-09

Publications (1)

Publication Number Publication Date
JPS6247232U true JPS6247232U (en) 1987-03-23

Family

ID=31042454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13793685U Pending JPS6247232U (en) 1985-09-09 1985-09-09

Country Status (1)

Country Link
JP (1) JPS6247232U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5743300A (en) * 1980-08-28 1982-03-11 Fujitsu Ltd Comparing circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5743300A (en) * 1980-08-28 1982-03-11 Fujitsu Ltd Comparing circuit

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