JPS6251414U - - Google Patents

Info

Publication number
JPS6251414U
JPS6251414U JP14332985U JP14332985U JPS6251414U JP S6251414 U JPS6251414 U JP S6251414U JP 14332985 U JP14332985 U JP 14332985U JP 14332985 U JP14332985 U JP 14332985U JP S6251414 U JPS6251414 U JP S6251414U
Authority
JP
Japan
Prior art keywords
bus line
transformer bank
primary
bus
disconnector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14332985U
Other languages
Japanese (ja)
Other versions
JPH0524966Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14332985U priority Critical patent/JPH0524966Y2/ja
Publication of JPS6251414U publication Critical patent/JPS6251414U/ja
Application granted granted Critical
Publication of JPH0524966Y2 publication Critical patent/JPH0524966Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Control Of Electrical Variables (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案を適用する変電所の一実施例を
示す図、第2図は変圧器バンクの制御条件を判断
する論理回路の構成図、第3図は本考案による制
御装置の要部の一実施例を示すブロツク図、第4
図は従来装置における制御条件の判断を行うフロ
ーチヤートである。 1…1次甲母線、2…1次乙母線、3…2次甲
母線、4…2次乙母線、11,K1…1次甲母線
側断路器、12,K2…1次乙母線側断路器、1
3,K3,16,K6…遮断器、14,K4…2
次甲母線側断路器、15,K5…2次乙母線側断
路器、MEM…記憶回路、LGC…論理演算回路
、B…第1号LRTバンク、BK…第K号LR
Tバンク。
Fig. 1 is a diagram showing an embodiment of a substation to which the present invention is applied, Fig. 2 is a configuration diagram of a logic circuit that determines control conditions of a transformer bank, and Fig. 3 is a main part of a control device according to the present invention. Block diagram showing one embodiment of
The figure is a flowchart for determining control conditions in a conventional device. 1...Primary A bus line, 2...Primary A bus line, 3...Secondary A bus line, 4...Secondary A bus line, 11, K1...Primary A bus line side disconnector, 12, K2...Primary A bus line side disconnector vessel, 1
3, K3, 16, K6...breaker, 14, K4...2
Secondary A bus side disconnector, 15, K5...Secondary B bus side disconnector, MEM...Memory circuit, LGC...Logic operation circuit, B1 ...No. 1 LRT bank, BK...No. K LR
T bank.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 1次側甲母線と乙母線との間に直列接続された
1次甲母線側断路器および1次乙母線側断路器と
、2次側甲母線と乙母線との間に直列接続された
2次甲母線側断路器および2次乙母線側断路器と
、前記1次甲母線側断路器と1次乙母線側断路器
との接続点と負荷時電圧調整装置付変圧器バンク
の入力側との間に接続された1次遮断器と、前記
2次甲母線側断路器と2次乙母線側断路器との接
続点と前記負荷時電圧調整装置付変圧器バンクの
出力側との間に接続された2次遮断器とを変圧器
バンク別に有する変電所において、前記各断路器
および遮断器の開閉状態が所定の状態になつてい
るか否かを変圧器バンク別に判断し、所定の状態
になつているならば当該変圧器バンクの制御を実
行する変圧器バンクの制御装置であつて、各断路
器および遮断器の開閉状態をそれぞれ1ビツトの
情報として各変圧器バンク別に記憶する記憶回路
と、この記憶回路の情報を順次読出して各変圧器
バンクにおける断路器および遮断器の開閉状態が
所定の状態になつているか否かを論理演算によつ
て判断する論理演算回路とを備えた変圧器バンク
の制御装置。
The primary A bus line side disconnector and the primary O bus line side disconnector are connected in series between the primary A bus line and the O bus line, and the secondary A bus line is connected in series between the secondary A bus line and the O bus line. The connection point between the secondary A bus side disconnect switch and the secondary A bus line side disconnect switch, the connection point between the primary A bus side disconnect switch and the primary A bus side disconnect switch, and the input side of the transformer bank with on-load voltage regulator. between the primary circuit breaker connected between the connection point of the secondary A bus side disconnecting switch and the secondary A bus side disconnecting switch and the output side of the transformer bank with on-load voltage regulator. In a substation having connected secondary circuit breakers for each transformer bank, it is determined for each transformer bank whether the opening/closing state of each disconnector and circuit breaker is in a predetermined state, and the transformer bank is brought into a predetermined state. If so, it is a transformer bank control device that executes control of the transformer bank, and includes a memory circuit that stores the open/close status of each disconnector and circuit breaker as 1-bit information for each transformer bank. , and a logic operation circuit that sequentially reads out the information in this memory circuit and determines by logic operation whether the opening/closing states of the disconnectors and circuit breakers in each transformer bank are in a predetermined state. Bank control device.
JP14332985U 1985-09-19 1985-09-19 Expired - Lifetime JPH0524966Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14332985U JPH0524966Y2 (en) 1985-09-19 1985-09-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14332985U JPH0524966Y2 (en) 1985-09-19 1985-09-19

Publications (2)

Publication Number Publication Date
JPS6251414U true JPS6251414U (en) 1987-03-31
JPH0524966Y2 JPH0524966Y2 (en) 1993-06-24

Family

ID=31052909

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14332985U Expired - Lifetime JPH0524966Y2 (en) 1985-09-19 1985-09-19

Country Status (1)

Country Link
JP (1) JPH0524966Y2 (en)

Also Published As

Publication number Publication date
JPH0524966Y2 (en) 1993-06-24

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