JPS625439A - Instruction code expansion system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The undefined instruction code of the main processor is used as an extension instruction to instruct the work of the auxiliary processor, and upon detection of this extension instruction, the main processor is instructed not to operate. During this time, the auxiliary processor reads the extended instructions and performs the formulated data processing in place of the main processor.

[Industrial application field]

The present invention relates to a processor that performs a certain amount of formalized data processing, and in particular to an instruction code extension method that makes it possible to instruct work to an auxiliary processor by using undefined instruction codes of the main processor. Regarding.

2. Description of the Related Art With the development of semiconductor technology, many data processing devices have come into use that use a processor and instruct the processor to process data using a program. The processor used in this data processing device is of the Neumann type, and performs data processing by fetching and decoding instructions one by one from a program memory, and fetching and calculating operands according to the instructions.

By the way, as the intelligent functions of data processing devices increase, it is becoming more common for processors to perform a large number of formalized tasks that cannot be processed using only their instruction codes, and the programs that instruct this task require a considerable number of steps. As a result, the processing time of the processor is also increasing.

Therefore, this work can be done in a way that does not burden the processor.
It is desirable that the processing can be performed by another processor or the like.

[Conventional technology]

FIG. 2 is a block diagram showing an example of a data processing device.

The processor 1 reads a program from the memory 2, operates it, and stores the processed data in the memory 2. It also sends and receives data to and from a host device via the interface circuit 5. At this time, data input from the host device is stored in the memory 2, and the data in the memory 2 is read out and sent out.

Operator commands and input data are input from the keyboard 3 via the keyboard control circuit 4, and the processor 1 executes the commands and stores the data in the memory 2 before reading it out and processing it.

The processor 1 accesses the disk 7 via the disk control circuit 6 as necessary to read or write data. The printer is also driven via the printer control circuit 8 to print the data read from the memory 2. It also controls the display control circuit 10 to display the data read from the memory 2 on the display section 11.

A processor 1 of a conventional data processing device sequentially reads instruction codes and operands, decodes and executes data processing according to software using a unique instruction code (machine language), and processes a large amount of data. For example, access to the memory 2, access to input/output devices such as the disk 7 and the printer 9, etc. are all executed by the processor 1.

If this processor 1 is, for example, an 8-bit processor, there are 256 instruction codes from 0O to FF, but processing the large amount of data cannot be processed only with the 256 instruction codes possessed by the processor 1. A program that instructs this processing has a large number of steps.

[Problem that the invention seeks to solve]

As mentioned above, when a data processing method is formulated and this data processing is frequently performed, conventionally, instructions with a large number of steps are read out from the memory 2 one by one, fetched, decoded, and executed. There is a problem that the processing efficiency of the processor 1 decreases.

In view of these problems, the present invention provides an auxiliary processor outside of the processor 1, and utilizes the undefined instruction code of the processor 1 to enable the auxiliary processor to be started, and also directly updates the software of the processor 1. The purpose is to have this auxiliary processor execute the formulated data processing.

That is, an 8-bit processor generally uses about 200 out of 256 instruction codes.

Therefore, it is possible to expand the remaining undefined instruction codes and use them as instructions to the auxiliary processor.

[Failure to solve the problem]

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention.

15 is a main processor that controls the entire data processing device;
6 is an auxiliary processor that assists the main processor 15; 17;
18 is a shift register that stores an extended instruction using an undefined instruction code, and 18 is an instruction code that converts the extended instruction and sends a NOP (no-operation instruction, an instruction that instructs the processor not to operate) to the main processor 15. A conversion circuit 19 is an extended instruction determination circuit that determines whether the instruction is an extended instruction, and 20 is a program memory that stores a program.

If the instruction read from the program memory 20 is an extended instruction, the extended instruction determination circuit 19 causes the instruction code conversion circuit 18 to send a NOP to the main processor 15, and causes the shift register 17 to store this extended instruction. Soshi C
The shift i-1/register 17 is configured to issue a startup interrupt request to the auxiliary processor 16 when the extended instruction has been stored, causing the extended instruction to be executed.

[Effect]

With the above configuration, the program memory 20
By storing extended instructions that utilize the main processor's undefined instruction code in the auxiliary processor, it is possible to instruct the auxiliary processor to process data, and the main processor is freed from the burden by having it perform the formalized data processing on its behalf. data processing efficiency can be improved.

〔Example〕

In FIG. 1, the main processor 15 reads -instructions one by one from the program memory 20, takes in them, decodes them, and controls the input/output devices connected to the data bus B.

The extended instruction determination circuit 19 receives an instruction fetch cycle signal from the main processor 15, checks the data read to the data bus B, and selects an extended instruction from the program memory 20 in which extended instructions obtained by extending undefined instruction codes are stored in advance. When an instruction is read, the instruction code conversion circuit 18 is controlled to convert it to NOP and send it to the main processor 15, thereby preventing the extended instruction from entering the main processor 15 and running out of control.

At the same time, the extended instruction determination circuit 9 instructs the shift register 17 to store the extended instruction read onto the data bus B. When the shift register 17 has finished storing all of the extended instructions, it sends a startup interrupt request to the auxiliary processor 16 and starts the auxiliary processor 16.

The auxiliary processor 16 reads the contents of the shift register 17 and performs the work performed by the main processor 15 based on the instructions of this extended instruction. At this time, a memory or the like connected to the auxiliary processor bus A is used as necessary.

At this time, the main processor 15 only performs a NOP operation for one step instead of processing a 20-step program, and the remaining 19 steps can be used for other processing.

〔Effect of the invention〕

As explained below, according to the present invention, the undefined instruction code of the main processor is used to instruct the auxiliary processor as an extension instruction, so the main processor does not need to control the auxiliary processor (this improves processing efficiency). It can be increased.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a circuit showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a data processing device. In the figure, 1 is a processor, 2 is a memory, 3 is a keyboard, 4 is a keyboard control circuit, 5 is an interface circuit, 6 is a disk control circuit, 7 is a disk, 8 is a printer control circuit, 9 is a printer, and 10 is a display control circuit, 11
15 is a display unit, 15 is a main processor, 16 is an auxiliary processor, 17 is a shift register, 18 is an instruction code conversion circuit, 19 is an extended instruction determination circuit,

Claims (1)

[Claims] A data processing device having a main processor (15) and an auxiliary processor (16) that operates according to instructions from the main processor (15), using an undefined instruction code of the main processor (15). a memory (20) for storing extended instructions instructing the work of the auxiliary processor (16); and extended instruction determining means (19) for detecting that the extended instructions have been read from the memory (20). , an instruction code converting means (18) for converting the extended instruction into a no-operation instruction based on an instruction from the extended instruction determining means (19) and sending it to the main processor (15); and the extended instruction determining means (19). storage means (17) for storing extended instructions and sending a startup interrupt request to the auxiliary processor (16) based on instructions from the memory (20);
), the main processor (15
), an auxiliary processor (16) is activated to read an extended instruction stored in the storage means (17).