JPS625445A - Information processor - Google Patents

Abstract

PURPOSE:To detect easily the drop in allowance with respect to the clock signal of a logic circuit by selecting any one of a reference value and a few types of clock signals having values different from the reference value and supplying it to the logic circuit. CONSTITUTION:A clock signal circuit 1 generates a clock 50 with a margin and clocks 51 and 52 without a margin, and supplies them to a switching circuit 2. First the clock 50 is selected and given to the logic circuit 3 to execute a diagnosis program. If the abnormality of the logic circuit 3 is not detected as a result, the clock 51 is selected through the switching circuit 2, and given to the logic circuit 3 to execute the diagnosis program. If the abnormality is detected as a result, the drop in the margin is detected. On the other hand, when the abnormality is not detected, the clock 52 is selected and given to the logic circuit 3 to execute the diagnosis program. Thus the drop in the margin can be easily detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device including a logic circuit that operates in synchronization with one clock signal.

In particular, the present invention relates to means for automating margin testing of clock signals.

〔overview〕

The present invention provides an information processing bag π equipped with a diagnostic circuit for diagnosing the margin for a clock signal of a logic circuit that operates in synchronization with one clock signal, in which various attributes exhibited by the clock signal match its reference value. By automatically giving a signal and a signal that indicates a value different from its reference value to the logic circuit to be diagnosed, it is possible to easily detect a decrease in the margin of the logic circuit with respect to the clock signal. It is.

[Conventional technology]

In an information processing device that includes logic circuits that operate in synchronization with one clock signal, a single clock signal is distributed to each logic circuit while taking phase skew into consideration.

The logic circuit has sufficient margin for the frequency, pulse width, phase, etc. of the distributed clock signal. This amount of margin needs to be able to cope with expected variations such as variations in logic circuit speed, delay amount, aging, changes in power supply voltage, and changes in environmental conditions such as temperature.

In the conventional information processing apparatus, a decrease in the margin amount of a logic circuit is detected by changing the clock margin and executing a diagnostic program.

[Problem that the invention seeks to solve]

Conventional information processing devices like this require manual intervention to specify changes in the margin, so it is difficult to detect a decrease in the margin using normal diagnosis, and automatic diagnosis cannot be performed. Ta.

The present invention aims to eliminate such drawbacks, and aims to provide an information processing apparatus that has means for predicting margin decline in advance and performing preventive maintenance.

[Means for solving problems]

The present invention includes a plurality of logic circuits inputting clock signals;
In an information processing apparatus equipped with a diagnostic circuit configured with a procedure for measuring each response of the logic circuit to a variation from a reference value in an attribute of this clock signal, a reference value and a value varied from this reference value are used. and a control means for selecting one of the plurality of clock signals and outputting it to the logic circuit as a clock signal over a desired period. Features.

[Effect]

In the clock generation means, for example, the frequency of the clock signal,
A clock that conforms to a reference value and a clock that has a value different from the reference value are generated with respect to clock attributes such as pulse width and rising and falling slopes of the pulse.

One clock is selected from this clock generation means and applied to the logic circuit. This logic circuit operates normally for clocks with distortions within limits. This logic circuit operates according to a diagnostic procedure given by the diagnostic circuit, and detects the presence or absence of an abnormality.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A device according to an embodiment of the present invention will be described below with reference to the drawings.

The figure is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention.

First, the configuration of an apparatus according to an embodiment of the present invention will be explained based on the drawings. This embodiment device uses a normal clock with a margin of 5
A clock supply circuit 1 that generates 0 and two types of margin clocks 51 and 52 without margin, a switching circuit 2 that inputs the normal clock 50 generated by this clock supply circuit 1 and margin clocks 51 and 52, and Logic circuit 3 inputting clock supply signal 82 from circuit 2
, a diagnostic device 9 that receives an abnormality detection signal 91 from the logic circuit 3 and outputs a diagnostic program signal 90; a switching control circuit 4 that outputs a clock selection signal 81 to the switching circuit 2; An all-0 detection circuit 7 that outputs an all-0 detection signal 60 to the device 9, a selection circuit 5 that inputs a timer register data signal 70 from the diagnostic device 9, and a time register coupled to the selection circuit 5 and the all-0 detection circuit 7. 8 and the output of time register 8,
A counting circuit 6 that outputs a time register count data signal 80 to the selection circuit 5 is provided.

Here, in the switching circuit 2, one of the three clocks 50 to 52 outputted from the clock supply circuit 1 is selected based on the clock selection signal 81, and based on this, the clock supply signal 82 is generated and the logic It is output to circuit 3. In addition, in the counting circuit 6, the time interval is minus r
It is counted in increments of lJ.

Further, in the timer register 8, the number of time intervals is set based on a program instruction included in the timer register data signal 7o outputted from the diagnostic device 9. Further, the all-0 detection circuit 7 detects that the set value of the timer register 8 has become all-0. The switching control circuit 4 outputs a clock selection signal 81 to the switching circuit 2 based on the all 0 detection signal that is the output of the all 0 detection circuit 7.
is generated.

Next, the operation of this embodiment device will be explained based on the drawings.

During normal operation, the normal clock 50 supplied from the clock supply circuit 1 is selected by the switching circuit 2, and is supplied to the logic circuit 3 using the clock supply signals 82 and 17.
Then, the operation is performed in synchronization with this.

Next, an explanation will be given of an operation during a diagnostic operation in which a diagnostic program is executed without manual intervention while changing the clock margin automatically. The timer register data signal 70 from the diagnostic device '89 sets the timer register 8 to a time sufficient to loop the diagnostic program once. 1. Based on the diagnostic program signal 90 from the diagnostic device 9, the logic circuit 3 executes the diagnostic program. In addition, a clock selection signal 8 from the switching control circuit 4
1, the switching circuit 2 selects the normal clock 50 supplied from the clock supply circuit 1. When an abnormality in the logic circuit 3 is detected as a result of successive execution of the diagnostic program in the logic circuit 3, this is notified to the diagnostic device 9 by an abnormality detection signal 91. No abnormality detected in logic circuit 3.
? , during normal operation, the value of the timer register 8 is counted down by 1 in synchronization with the clock (i) by the counting circuit 6.
1. h is executed by the logic circuit 3, and when the operation 1 always ends, it is repeatedly executed by the diagnostic device 9. Diagnosis boo
When enough time has been counted to loop the program once, timer register 8 goes to state 6. - becomes,
This is detected by the all-0 detection circuit 7. The diagnosis device 9 and the switching control circuit 4 are notified by the all-O detection signal 60 from the all-0 detection circuit 7 that the values of the timer/register 8 are all O. When it is notified by the all O detection signal 60 that all the values in the timer register 8 have become O, the switching circuit 2 selects the margin clock 5 by the clock selection 13 81 from the switching control circuit 4.
1 is selected, and the logic circuit 3 is selected by the clock supply signal 82.
A margin clock 51 is supplied to. When the diagnostic device 9 is notified by the all 0 detection signal 60 that the values of the timer register 8 are all O, the timer register 8 is notified by the timer register data signal 70 to loop the diagnostic program once. Sufficient time is set, and the diagnostic program in the logic circuit 3 is executed based on the diagnostic program signal 90.

In this way, when a diagnostic program using the clock signal 51 with no margin is executed in the logic circuit 3 and an abnormality is detected in the logic circuit 3 as a result, the diagnostic device 9 is notified by the abnormality detection signal 91. A decrease in the margin is detected.

Furthermore, when the timer register 8 is turned on for a sufficient period of time to loop the diagnostic program once, all registers become 0.
This state is notified to the diagnostic device 9 and the switching control 1 circuit 4 by the all 0 detection signal 60. When it is notified that the value of the timer register has become zero, another margin clock 52 is selected in the switching circuit 2 based on the clock selection 14 No. 81 from the switching control circuit 4, and the logic circuit 3 At the same time, the timer register data signal 70 from the diagnostic device 9 sets a time sufficient to loop the diagnostic program once, and at the same time, the diagnostic program signal 90 is used. A diagnostic program is executed in the logic circuit 3.

In this way, two types of clock signals with no margin are used to automatically run the diagnostic program in the logic circuit, and the margin drop detection test is performed without human intervention.

In this embodiment, there are two types of clocks with no margin, and 2. There are differential 1 and check items for margins such as frequency 1, pulse width, phase, and slope of the rising edge and falling edge of the clock signal, so the number of clocks output by the clock supply circuit depends on the number of checked items. The present invention can be implemented even if the number is increased or decreased.

〔Effect of the invention〕

As explained below, the present invention detects a decrease in the margin through normal diagnostic operations by sequentially specifying changes in the cross-margin from the diagnostic device without manual intervention and automatically running the diagnostic program. This has the effect of making preventive maintenance of the information processing device easier.

[Brief explanation of the drawing]

The figure is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention. 1... Clock supply circuit, 2... Switching circuit, 3...
・Logic circuit, 4... Switching control circuit, 5... Selection circuit, 6... Counting circuit, 7... All 0 detection circuit, 8...
...Timer register, 9...Diagnostic device, 50...Normal clock, 51.52...Margin clock, 60
...All 0 detection signal, 70...Timer register data signal, 80...Timer register count data signal, 81...Clock selection signal, 82...Clock supply signal, 90...Diagnostic program signal , 91...
Abnormality detection signal. Configuration diagram of example

Claims (1)

[Claims] (1) An information processing device comprising a plurality of logic circuits into which a clock signal is input, and a diagnostic circuit configured with a procedure for measuring each response of the logic circuits to a variation from a reference value of an attribute of the clock signal. a clock generating means for generating a plurality of different types of clock signals having a reference value and a value varied from the reference value, and selecting one of the plurality of types of clock signals to apply the clock signal to the logic circuit for a desired period. 1. An information processing device comprising: a control means for outputting a clock signal over the clock signal.