JPS6255679B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an automatic accompaniment device for an electronic musical instrument, and more particularly to an automatic accompaniment device for an electronic musical instrument that has a function of automatically generating chords and a function of generating notes of appropriate degrees according to an automatic accompaniment pattern, such as automatic bass performance. To automatically generate a plurality of tones, that is, a chord, having a predetermined pitch relationship (1st, 3rd, or 5th, etc.) with respect to this root note by pressing a desired key on a keyboard as a root note designation key. is already known as a single finger mode function in automatic bass chord performance. Additionally, automatic bass sound generators have been available that detect the root note of a chord and automatically generate a bass note with a note name that is separated from the note name of the root note by the number of degrees indicated by automatic bass pattern data. Are known. However, conventional single finger mode chord generators and automatic bass tone generators are
Both require a read-only memory or an arithmetic circuit that handles multiple bits of parallel coded signals, resulting in a large-scale circuit configuration. An object of the present invention is to provide an automatic accompaniment device having both an automatic chord generation function known as a single finger mode function and an automatic bass tone generation function with a simplified circuit configuration. In order to achieve this objective, in the present invention, time division timing is assigned in advance to each note name, and the note name of an arbitrary desired note corresponding to a standard degree (for example, 1 degree or root note) is assigned in advance. generates the above-mentioned time-division timing pulses corresponding to the above, sequentially shifts these pulses in a shift register, and outputs pulses from predetermined plural stages of this shift register according to the desired chord type to indicate the name of each note of the harmonious notes. (indicated by the timing), and using the same shift register, take out the output pulses from the appropriate stages of the shift register corresponding to the degrees indicated by the automatic base pattern signal;
The present invention is characterized in that a musical tone signal having a note name corresponding to the generation timing of each extracted pulse is sounded as an automatic chord or a bass tone, respectively.
Specifically, the automatic accompaniment device for an electronic musical instrument according to the present invention includes a pulse generating means that outputs a pulse at the timing of a desired note name corresponding to a reference frequency among the time division timings assigned to each note name; A shift register having a plurality of stages, the interval between each stage corresponding to a pitch, and sequentially shifting the pulses output from the pulse generating means in synchronization with the time division timing, and specifying a desired chord type. and a chord type specifying means that outputs pulses from a plurality of stages of the shift register that have a pitch relationship of the chord with respect to the reference frequency according to the chord type specified by the chord type specifying means. a first pulse extracting means for extracting each pulse indicating the note name of the constituent notes, and a pattern signal indicating the frequency of the bass note to be generated at the timing at which the bass note should be generated, the pattern signal indicating The frequency corresponds to the pitch difference with respect to the reference frequency.Base sound pattern generation means, and the frequency corresponding to the reference frequency among the stages of the shift register according to the pattern signal generated by the base sound pattern generation means. a second pulse extraction means for extracting an output pulse from a stage corresponding to the pitch difference in frequency of the pattern signal; and a second pulse extraction means for extracting an output pulse from a stage corresponding to a pitch difference in frequency of the pattern signal, and a second pulse extraction means for extracting an output pulse from a required stage of the shift register in the first pulse extraction means. Control is performed in a first time period having a time width for one round of the time division timing of the name, and
The output pulse extraction operation of the required stage of the shift register in the second pulse extraction means has a time width that makes at least one cycle of the time division timing of each note name, and is different from the first time period. a control means for controlling execution in a second time period, and converting each pulse extracted by the first pulse extraction means in the first time period into pitch name data corresponding to the timing of generation thereof; pitch name data converting means for converting the pulse extracted by the second pulse extracting means in the second time period into pitch name data corresponding to the generation timing thereof;
A plurality of musical tone signals corresponding to each pitch name data converted by the pitch name data converting means are generated as musical tone signals of chord constituent notes in the second time period, and the pitch name data is generated in the second time period. and musical tone generating means for generating a musical tone signal corresponding to the note name data converted by the converting means as a musical tone signal of the bass tone. According to this invention, the circuit for determining the note name data of each note of a chord and the note name data of the degree indicated by the automatic bass pattern signal based on the note name data corresponding to the reference degree includes a shift register and the shift register. Since the circuit extracts the output pulse from an appropriate stage of the register (the circuit for extracting may be a simple logic circuit), the circuit configuration is simplified.
In this case, a single shift register can be used for both automatic chords and automatic bass notes, so the circuit can be simplified in this respect as well. Since the pulse input to the shift register is generated at the timing of the note name corresponding to the standard frequency, the note name timing of the pulse output from each stage of the shift register as a result of the shift of this pulse is the standard. It corresponds to pitch names whose intervals are sequentially shifted by semitones from the pitch name corresponding to the degree of . That is, the position of each stage of this shift register corresponds to the number of tones. Therefore, depending on the desired chord type (major, minor, seventh, etc.), a predetermined plurality of stages (for example, one stage in the case of a major chord)
By extracting the output pulses of stages (stages corresponding to degrees, major thirds, and perfect fifths), it is possible to obtain pulses corresponding to the timing of each note name of the chord constituent notes. By extracting the output pulse from the stage corresponding to the frequency indicated, it is possible to obtain pitch name data (pulses generated at the timing assigned to the pitch name) corresponding to the frequency indicated by the pattern signal. . In the embodiments described below, the parts that are deeply related to the gist of the present invention are the explanations regarding "automatic bass chord performance (especially single finger mode and automatic bass performance)", and particularly noteworthy circuit devices and drawings. are key scanning circuit 11, chord detection control circuit 30, SF root note detection priority circuit 32, SF
chord type detection section 33, root note shift register 41,
1 and 7 related to the bass note key data forming circuit 42, SF chord key data forming circuit 43, etc.
12, 15, 16, 17, etc. Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. General description of the overall configuration of the embodiment The electronic musical instrument shown in FIG. 1 is of a single-keyboard type, and a key switch matrix 10 has key switches arranged in a matrix, corresponding to each key of the single-level keyboard. The key scanning circuit 11 scans the key switch matrix 10 from the treble side, and performs a time division method that indicates whether the key is on or off depending on the presence or absence of a pulse (“1” or “0”) in the time slot corresponding to each key. Generate multiplexed key data KD onto a single output line. Furthermore, the key scanning circuit 1
1 may be configured to scan from the low-pitched key, but in the following explanation it will be assumed that scanning starts from the high-pitched key. The key scanning circuit 11 includes a scanning counter, and outputs a multi-bit key code (consisting of note codes N1 to N4 and octave codes B1 to B3) indicating the key currently being scanned. Scan key display line 12 is supplied. In addition, the key scanning circuit 11 forms an extra scanning time that does not correspond to each key of the key switch matrix 10, and by not sending out the key data KD during this time, various automatic operations are performed in the subsequent circuit. This ensures enough time to create key information for performance. Furthermore, the key scanning circuit 1
1, various timing signals related to key scanning are formed and supplied to other circuits. Details of those key scanning related timing signals will be revealed later. The electronic musical instrument shown in Figure 1 is equipped with an automatic bass chord performance function, and when automatic bass chord performance is not selected, all keys on the keyboard are played in the first tone generation mode (melody performance). The sound channel is used commonly for all keys, and if automatic bass chord performance is selected, some keys on the keyboard are used as the second key range.
to correspond to the musical sound generation mode (automatic bass chord performance and automatic arpeggio performance, that is, accompaniment performance),
The remaining key range is made to correspond to the first musical tone generation mode (melody performance). When the keyboard is divided and used for the first and second tone generation modes, a predetermined tone generation channel group out of all tone generation channels is used exclusively for the second tone generation mode, and the remaining tone generation channel groups are used exclusively for the second tone generation mode. is the first
It is used exclusively for the musical sound generation mode. In the key range used for the second musical tone generation mode, accompaniment chords (chords) are specified to be pressed. The automatic bass tone is automatically formed based on the accompaniment chord specified by the key press and the bass pattern data. The pronunciation channel group (accompaniment channel) for the second musical tone generation mode includes a predetermined pronunciation channel for chords and a dedicated pronunciation channel for automatic bass notes. Furthermore, the electronic musical instrument shown in FIG. 1 has an automatic arpeggio performance function linked to automatic bass chord performance. When automatic bass chord performance is selected, automatic arpeggio performance is also selected in conjunction with this, and the constituent notes of the accompaniment chord are automatically sounded in an arpegillo format. Therefore, the second
The sound generation channel group for the musical tone generation mode further includes a dedicated sound generation channel for automatic arpeggio sounds. The mode selection circuit 13 determines whether the keyboard and sound generation channel of the electronic musical instrument shown in FIG. selected. The mode selection circuit 13 mainly includes a switch FC-SW for selecting a finger chord mode for automatic bass chord performance, and a switch SF-SW for selecting a single finger mode.
Other auxiliary function selection switches include a memory function selection switch M-SW and a usage channel selection switch 10/7-SW. Furthermore, in the mode selection circuit 13, each of the above-mentioned switches is turned on and off.
A latch device 14 captures the off state, and various mode signals 10/7, M,
It is provided with a mode switching control circuit 15 that generates FC, SF, and ABC, and also generates pulses Δ and ΔABC indicating mode switching at the time of mode switching. Fin guard code mode selection switch FC−
When the SW or single finger mode selection switch SF-SW is turned on, it means that automatic bass chord play (and automatic arpeggio play in conjunction with it) is selected, and the keyboard and sound channel of this electronic instrument are selected. is dividedly used depending on the first and second musical tone generation modes. At this time,
The automatic base code mode signal ABC becomes "1", indicating that it should be used separately as described above. Note that the output "1" of the switch FC-SW is inverted by the inverter 16 and applied to the AND circuit 17.
The output of switch SF-SW is blocked, and finger code mode FC has priority over single finger mode SF. When both switches FC-SW and SF-SW are off, it means that automatic bass chord play is not selected, and in that case, the keyboard and sound channel of this electronic instrument are used only in the first musical sound generation mode. be done. The mode in which automatic bass chord performance is not selected will hereinafter be referred to as normal mode. In the case of normal mode, automatic base code mode signal ABC is "0". In the mode switching control circuit 15, when changing from automatic base chord mode (finger chord mode or single finger mode) to normal mode, or vice versa,
Mode switching pulse △ABC is generated for a certain period of time. This mode switching pulse ΔABC functions to clear the sound generation assignment of the sound generation channel group used in the second musical tone generation mode (automatic bass chord performance) and to temporarily inhibit the operation of various circuits. This sound generation channel group is used for both the first and second musical tone generation modes, so when switching modes, old sound generation data (sound generation data for either the first or second musical tone generation mode) is transferred to this sound generation channel group. Mode switching pulse △ABC
to clear the new pronunciation data (first
Alternatively, preparations are made to allocate data for the other of the second musical tone generation mode. In particular, this mode switching pulse ΔABC is effective in preventing excessive generation of unnecessary sounds due to the switching when the mode is switched while playing the keyboard. The memory function selection switch M-SW is a switch for selecting a memory function that stores key press data even after the key is released during automatic bass chord performance and continues to generate automatic bass tones, chords, etc. even after the key is released. The channel selection switch 10/7 is a switch for selecting the total number of sound channels to be used, and in this embodiment, one of 10 channels and 7 channels can be selected. When this switch 10/7 is off, channel 10 is selected. The sound generation assignment circuit 18 performs a sound generation assignment control function that assigns the sound of a pressed key to one of the sound generation channels based on time-division multiplexed key data KD indicating the pressed key depending on the presence or absence of a pulse in each time slot. Contains part 19. The maximum number of sound generation channels is 10, and when the above-mentioned switch 10/7 is turned on, the maximum number of sound generation channels is reduced to 7. Furthermore, the sound generation assignment circuit 1
8 includes a timing signal generation circuit 20 and a window circuit 21. The timing signal generation circuit 20 generates channel timing signals UchT, LchT, PchT, and AchT corresponding to the time division timing of each sound generation channel. Which channel timing signal UchT, LchT, PchT,
Depending on whether AchT occurs, it is indicated whether the channel is used by the first tone generation mode or the second tone generation mode. The channel timing at which each channel timing signal UchT to AchT is generated is switched according to the states of various mode signals 10/7 to ΔABC given from the mode selection circuit 13. By this switching, all sound generation channels are used for the first tone generation mode, or both the first and second sound generation mode are used.
It becomes possible to control switching whether to divide and use the musical sound generation mode. The window circuit 21 sends the key data KD given from the key scanning circuit 11 to the mode selection circuit 1.
This is for distributing to one of the first and second musical tone generation modes according to the states of various mode signals given from No. 3. In normal mode, the key data KD of all keys is distributed to the first musical tone generation mode, but in the case of automatic bass chord mode, the key data KD of a predetermined key range is distributed to the first musical tone generation mode. , key data KD of other key ranges
is assigned to the second musical tone generation mode. The key data KD distributed according to each tone generation mode is given to the sound generation assignment control section 19, and assigned to one of the channel groups specified by the channel timing signals UchT and LchT given from the timing signal generation circuit 20. It will be done. The off-channel timing signal OFchT generated by the timing signal generation circuit 20 is generated based on the mode switching pulse ΔABC, and indicates the channel for which the tone generation assignment is to be cleared. The truncate circuit 22 provided in conjunction with the sound generation assignment circuit 18 is a circuit that detects the channel for which the key was released the earliest (the channel to be truncated). The number TRUN is generated. The sound generation assignment control section 19 allocates the sound of a new pressed key in correspondence to the channel specified by the truncate channel signal TRUN. In the sound generation assignment control section 19, the key scanning circuit 11
When it is decided to newly allocate the key data KD given from
(allocation instruction) is generated. At the same time, the sound generation assignment control section 19 stores a key-on signal KO1 corresponding to the channel that generated the load signal LD,
Output. The key information conversion unit 23 converts the key data KD divided by the sound generation allocation circuit 18 into a multi-bit key code and stores the converted key code. The key information converter 23 includes a key code memory 24 that stores key codes of sounds assigned to each sound generation channel. The key code memory 24 is given key codes N1 to N4 and B1 to B3 from the key scanning circuit 11 via the scanning key display line 12.
When the load signal LD is applied from the sound generation allocation control section 19, the key codes N1 to B3 applied to the input side are stored corresponding to the channel in which the load signal LD is generated. Further, the key information conversion section 23 includes a comparison circuit 25, and a key code indicating the scanning key given to the scanning key display line 12 and a key code memory 2.
Compare the key code with the assigned key code stored in 4. The key code memory 24 outputs the key codes assigned to each channel in a time-division manner in synchronization with the time-division time slots of each channel in the sound generation assignment circuit 18. The time division timing of each channel is faster than the key scanning timing, and while one key code N1 to B3 is output to the scanning key display line 12, all channels' keys are output from the key code memory 24. The code is now being output. When the two input key codes match, the comparison circuit 25 outputs a match signal EQ and supplies it to the sound generation assignment control section 19. In the sound generation assignment control section 19, this coincidence signal
Depending on the presence or absence of EQ, it is determined whether the currently given key data KD has already been allocated. Octave code conversion circuits 26 and 27 provided in the key information conversion section 23 convert octave code B of the key chord during processing for automatic bass chord performance or automatic arpeggio performance.
This is for changing the values of 1 to B3. The multiplication circuit 28 inputs key codes N1 to N1 assigned to each channel output from the key code memory 24.
N4, B1 to B3 and the key-on signal KO1 output from the sound generation allocation control section 19 are multiplexed into 4-bit data KC1 to KC4. The reason for multiplexing is to save the number of connection pins since the parts separated by the dashed line 29 are composed of separate integrated circuits. Incidentally, the timing signal generation circuit 20 in the sound generation allocation circuit 18 also generates clock pulses φ _A and φ _B for setting the key scanning time.
1. Key data output from key scanning circuit 11
KD is also supplied to the chord detection control circuit 30. The chord detection control circuit 30 mainly detects accompaniment chords in automatic bass chord performance, but has multiple functions. The configuration of the chord detection control circuit 30 is divided into functions: an FC chord detection section 31 for finger chord mode, an SF root note detection priority circuit 32 for single finger mode, and an SF chord type detection section for single finger mode. 33 and
It also includes an arpeggio ARP key data storage section 34. The lower key range key data register 35 includes the FC chord detection section 31, the SF chord type detection section 33, and the ARP
It is shared by the key data storage unit 34.
Also, minor chord min memory 36 and seventh chord
The 7th memory 37 is shared by the FC chord detection section 31 and the SF chord type detection section 33. The FC chord detection unit 31 detects accompaniment chords based on the combination of pressed key data in the key range used for the second musical tone generation mode (this will be referred to as the lower key range) from the key data KD, Outputs root note data RTLD representing the root note name of the detected chord, and data min or 7th representing the chord type. When it is a minor chord, the data min is "1", when it is a seventh chord, the data 7th is "1", and when it is a major chord, both data min and 7th are "0".
These data min and 7th are stored in memories 36 and 37. In single-finger mode SF, one key indicating the root note of a chord is pressed as the highest note (or lowest note) in the lower key area (i.e. accompaniment key area) used for the second musical sound generation mode. However, the major, minor, and seventh chord types are designated by pressing (or not pressing) a predetermined key on the lower (or higher) side of the same key range. Therefore, the SF root note detection priority circuit 32 preferentially detects the pressed key data of the highest note (or lowest note) among the key data KD of the lower key range, and outputs it as root note data RTLD. Also,
The SF chord type detection unit 33 detects the chord type from the pressed key data other than the highest note (or lowest note) detected preferentially by the circuit 32, and
Store in 7. For example, if a white key other than the root key is pressed, it will be a seventh chord, if a black key is pressed, it will be a minor chord, and if no key other than the root key is pressed, it will be a major chord. . The chord detection control circuit 30 selects the key data of the lower key range from the key data KD and outputs it as the lower key range key data LKKD. This lower key area key data
LKKD is supplied to a lower key area new key-on detection circuit 38, and a lower key area new key on signal LANKO is generated from the circuit 38 when any key is newly pressed in the lower key area. The chord detection control circuit 30 also stores lower key range key data LKKD, and a lower key range key-on signal that becomes "1" when any key is pressed in the lower key range.
Causes LKO. This lower key range key-on signal LKO
is stored in the lower key area key-on memory 39, and the lower key area any key-on signal LKAKO becomes "1" in terms of direct current when any key is pressed in the lower key area.
is output from the memory 39. this signal
When LKAKO is in memory mode (M is "1"), it remains "1" even after the key is released. The automatic bass chord processing circuit 40 includes a root note shift register 41 that stores and shifts the root note data RTLD detected by the chord detection control circuit 30, a bass note key data formation circuit 42, and an SF chord key for single finger mode. The data forming circuit 43 includes a data forming circuit 43. The root note shift register 41 stores root note data generated in accordance with the timing of the root note name.
The RTLD is sequentially shifted, and timing data of a predetermined number of tones (follower tones) relative to the root tone is output from each shift stage. In the bass note key data forming circuit 42, based on the output of the root note shift register 41, the chord type data min, 7th, and the bass pattern data BassPT, timing data of the note name corresponding to the number of note degrees indicated by the bass pattern data BassPT is generated. That is, it generates the bass tone key data KP and also generates the octave codes B1' to B3' of the bass tone. Furthermore, a base timing signal BT indicating the generation timing of the bass sound is generated in accordance with the generation timing of the bass pattern data BassPT. The SF chord key data forming circuit 43 uses timing data (single finger chord key data
SFKL). The arpeggio (ARP) key data storage unit 34 in the chord detection control circuit 30 stores key data of constituent notes of accompaniment chords in fingered chord mode (FC) or single finger mode (SF), and stores the key data. AKD is supplied to the arpeggio key data forming circuit 44. The arpeggio note key data forming circuit 44 searches the chord constituent note key data AKD for the note in the pitch order specified by the arpeggio pattern data ArpPT, and then selects an arpeggio note key corresponding to the timing of the found note name. In addition to generating data KA, the octave code B1″ of the arpeggio sound
~B3'' is output. Also, in accordance with the generation timing of the arpeggio pattern data ArpPT, an arpeggio timing signal AT indicating the generation timing of the arpeggio sound is output. In order to search for notes in the pitch order, the matching signal EQ output from the comparison circuit 25 of the key information conversion section 23 is used by the arpeggio note key data forming circuit 44. Single finger chord key data SFKL, bass note key Data KP, arpeggio key data
The timing of each note name in KA matches the timing of key data KD output from the key scanning circuit 11. These automatically generated key data SFKL, KP, KA are generated by the sound generation assignment circuit 1.
8 and is assigned to the sound generation channel group for the second musical tone generation mode. The octave codes B1' to B3' of the bass notes and the octave codes B1'' to B3'' of the arpeggio notes are supplied to the octave code conversion circuit 26, and stored in the key code memory 24 in place of the octave codes B1 to B3 of the scanning keys of line 12. Supplied. Also, in the case of single finger mode (SF), a unique octave code is formed in the octave code conversion circuit 26 based on the single finger mode signal SF, and is stored in the key code memory instead of the octave code of the scanning key on line 12. 24. The base pattern data BassPT and arpeggio pattern data AtpPT are the autorhythm device 4.
It is generated from a pattern generation circuit 46 in 5. The autorhythm device 45 includes a large number of rhythm selection switches (not shown) and pattern selection switches (not shown), and selects predetermined base pattern data according to the selected rhythm and pattern.
BassPT, arpeggio pattern data ArpPT, and chord (chord) sound timing pattern pulse
CT is generated from a pattern generation circuit 46. In addition, rhythm sound signals are generated in response to the selected rhythm.
Generate R.TONE. In addition, the autorhythm device 4
5 generates a rhythm run signal RUN indicating whether or not the rhythm is moving. When "1" is set in the RUN memory 47, the autorhythm device 45 is operating and is in a state where it can generate the rhythm sound signal R.TONE and pattern data BassPT, ArpPT, CT. At this time, RUN memory 47
The rhythm run signal RUN output from is "1". When the RUN memory 47 is reset, the autorhythm device 45 stops and the rhythm sound signal R.
TONE and pattern data BassPT, ArpPT, CT
is not generated. The RUN memory 47 is set by a signal "1" from the OR circuit 48 when the rhythm start switch STRT is turned on, or when the synchronized start switch SYNC is turned on and some key is pressed in the lower accompaniment range. Ru. The output of the synchro start switch SYNC is applied to an AND circuit 49, and the other input of this AND circuit 49 is applied with the lower key range any key-on signal LKAKO from the lower key range key-on memory 39. Synchronized start means starting a rhythm in synchronization with the start of a key press. Pattern data BassPT,
In order for ArpPT,CT to occur, it is not sufficient that the RUN memory 47 is simply set;
Some kind of rhythm must be selected. RUN memory 47 uses mode switching pulse △ABC
It is temporarily reset by . If the rhythm start switch STRT is on, it will be set again when the pulse △ABC disappears, so the rhythm and automatic performance pattern will stop only while the mode switching pulse △ABC is being generated. If the synchro start switch SYNC is on, it will be set again when a key in the lower key range is pressed for the first time after the pulse ΔABC is erased. The rhythm stop signal RSTP is generated by the autorhythm device 45 when the RUN memory 47 is reset ( ) or when no rhythm is selected. This rhythm stop signal RSTP is used for automatic bass chord performance control. The multiplexing circuit 28 receives key codes N1 to B3 assigned to each channel and a key-on signal KO1.
In addition, control signals such as the automatic base code mode signal ABC output from the mode selection circuit 13 are also multiplexed and output. The demodulation circuit 50 converts the key codes N1 to KC4 from the multiplexed data KC1 to KC4 sent from the multiplexing circuit 28.
This is a circuit that separately extracts B3, key-on signal KO1, automatic bass chord mode signal ABC, etc. Key codes N1 to B3 taken out from the demodulation circuit 50
is supplied to the musical tone generation circuit 51. The musical tone generation circuit 51 generates a musical tone generation series corresponding to each channel.
It is equipped with ch1 to ch10, and the key code N1 to B3 of each channel given from the demodulation circuit 50.
The musical sound generation series ch1 corresponding to that channel
-Distributed to ch10, each musical tone generation series ch1 to ch1
At 0, musical tone signals of pitches corresponding to the distributed key codes N1 to B3 are generated. The timing signal generator 52 generates timing pulses φ _A ′, φ based on the reference pulse SY given from the demodulation circuit 50 .
_B ', FB0 to FB10 are generated. The timing pulses FB0 to FB10 are used by the tone generation circuit 51 to distribute the key codes N1 to B3 of each channel outputted from the demodulation circuit 50 to the tone generation series ch1 to ch10 of the tone generation circuit 51. The musical tone control circuit 53 generates an attack signal AT, a decay signal DC, an automatic bass chord mode signal ABC or A mode switching pulse △ABC〓 is generated, and a tone selection signal TC is also generated. The musical tone generation circuit 51 controls the musical tone amplitude envelope and timbre according to the signal generated from the musical tone control circuit 53. In addition, the mode switching pulse △ABC〓 is the mode switching control circuit 15.
This pulse is almost the same as the mode switching pulse △ABC generated from the mode signal ABC, and in order to save the number of wires, the pulse △ABC is not brought to the musical tone generation circuit 51, and the mode switching pulse △ABC is generated based on the mode signal ABC. 〓 is being recreated. The musical tone control circuit 53 includes a key-on rising pulse generating circuit 54, which generates a key-on signal KO1.
Key-on rising pulse with a fixed time width at the rising edge of
Causes KO2. This key-on rising pulse
By generating the attack signal AT for a short time based on KO2, the musical tone generating circuit 51 generates a musical tone with a percussive amplitude envelope. The key-on rising pulse generation circuit 54 prohibits the generation of the key-on rising pulse KO2 when the mode switching pulse ΔABC is being generated. This is because the note being pressed is reassigned to a different channel when the mode is switched, resulting in a false key-on rising pulse KO2 even though it is not actually the beginning of the key press.
This is to prevent the percussive envelope sound from being generated twice by prohibiting this false key-on rising pulse KO2. The musical tone signal generated from the musical tone generation circuit 51 and the rhythm tone signal R.TONE generated from the autorhythm device 45 are supplied to the sound system 55,
pronounced. It should be noted that FIG. 1 only shows the rough wiring of the various circuits of the electronic musical instrument of this embodiment, and in reality, many more signals are transmitted and received between the various circuits. The details will become clear in the detailed drawings of each part shown from FIG. 2 onwards. Description of Clock Pulses A detailed example of the timing signal generation circuit 20 in the sound generation assignment circuit 18 of FIG. 1 is shown in FIG. This timing signal generating circuit 20 generates not only channel timing signals UchT to AchT but also clock pulses φ _A and φ _B for key scanning. In FIG. 2, the initial clear signal IC is applied to a delay flip-flop 56 and an AND circuit 57, and the output of the delay flip-flop 56 is inverted by an inverter 58 and applied to the other input of the AND circuit 57. The initial clear signal IC is a signal that rises to "1" for a certain period of time when the electronic musical instrument is powered on. Delay flip-flop 56 is driven by system clock pulse φ.
The system clock pulse φ is composed of two-phase clock pulses φ ₁ and φ ₂ as shown in FIG. 3, and the timing for taking in data follows the pulse φ ₁ , and the timing for outputting the taken data follows the pulse φ ₂ . The time corresponding to one cycle of this system clock pulse φ is hereinafter referred to as one bit time. Delay flip-flop 56, AND circuit 5
7. The inverter 58 constitutes a differential circuit,
Initial clear signal IC rise (power on)
In response to this, a 1-bit time width pulse IC' is outputted from the AND circuit 57 (see FIG. 3). The output pulse IC' of the AND circuit 57 is the OR circuit 5
9 to an 11-stage/1-bit shift register 60 and a flip-flop 61.
It is added to the set input (S) of The flip-flop 61 is driven in synchronization with the system clock pulse φ, takes in the S input or T input signal at the timing of the pulse _φ1 , and outputs a signal indicating the state set based on the input signal to the pulse _φ2.
Output at the timing of. flipflop 61
The output Q of is the pulse applied to the set input (S)
It rises to "1" one bit time later than IC' (see 61-Q in FIG. 3). Shift register 60 sequentially shifts pulse IC' having a one-bit time width in accordance with system clock pulse φ. The outputs of the first stage Q1 to the tenth stage Q10 are applied to the NOR circuit 62, and the output of the NOR circuit 62 is returned to the shift register 60 via the OR circuit 59 and is applied to the T input of the flip-flop 61. When "1" is shifted to the final stage Q11 of the shift register 60, the outputs of the previous stages Q1 to Q10 are "0", and the output of the NOR circuit 62 becomes "1". At that time, the output "1" of the NOR circuit 62 is output to the shift register 6.
The output of the first stage Q1 becomes "1" at the next timing. Therefore, in the shift register 60, a single signal "1" always circulates and is shifted sequentially.
Numbers 1 to 11 of stages Q1 to Q11 of the shift register 60 that output "1" are set to 60-
Shown in Q. The flip-flop 61 inverts its state every time "1" is output from the NOR circuit 62. The output Q (61-Q) of the flip-flop 61 is inverted one bit time after the output "1" of the NOR circuit 62, that is, the output "1" of the eleventh stage Q11 of the shift register 60. Therefore, the output Q of the flip-flop 61 becomes a repetitive pulse with a duty of 1/2, as shown at 61-Q in FIG. The output Q of the flip-flop 61 is the NOR circuit 6
3, and a signal obtained by inverting this output Q by an inverter 64 is applied to a NOR circuit 65. Noah circuit 6
The other inputs of 3 and 65 are the shift register 60.
11 The output of stage Q11 is added. Noah circuit 63
A clock pulse φ _B having a 22-bit time period as shown in FIG. 3 is output from the NOR circuit 65, and a clock pulse φ _A having a 22-bit time period as shown in FIG. 3 is output from the NOR circuit 65. These two-phase clock pulses φ _A and φ _B are used as clock pulses for key scanning. When used as a pair of two-phase clock pulses, these pulses φ _A and φ _B are denoted as φ _AB . The 22-bit time from the rising edge of clock pulse _φB to just before the next rising edge is defined as one key time. Also, the output Q (61-
Q) is output from the timing signal generation circuit 20 as the second half period signal H2. This second half period signal H2 is "1" during the last 11 bit times of one key time. Further, the output Q of flip-flop 61 is applied to AND circuit 66. AND circuit 66
The output of the 11th stage Q11 of the shift register 60 is added to the other input of the shift register 60. Therefore, 61 in Figure 3
When -Q is "1" and 60-Q is "11", the condition of AND circuit 66 is satisfied and "1" is input to delay flip-flop 67. Delay flip-flop 67 receives system clock pulse φ
The input signal is delayed by 1 bit time according to the following and output as signal S1. Therefore, the signal S1 is the third
As shown in the figure, this occurs repeatedly corresponding to the first 1 bit time of 1 key time. Details of Mode Selection Circuit 13 A detailed example of the mode selection circuit 13 in FIG. 1 is shown in FIG. In FIG. 4, the latch device 14 is connected to each switch 10/7-SW, M-SW,
Latch circuit 14- corresponding to FC-SW, SF-SW
1, 14-2, 14-3, 14-4. Since the internal configurations of each of the latch circuits 14-1 to 14-4 are substantially the same, only the latch circuit 14-1 will be described using the reference numeral. In the latch circuit 14-1, the switch 10/7
The output of -SW is applied to an AND circuit 68, and the output of the AND circuit 68 is taken into a delay flip-flop 70 via an OR circuit 69. AND circuit 6
A relatively long scan cycle pulse of 4.5M is applied to the other input of 8. As described later,
This 4.5M pulse is applied to the key scanning circuit 11 (first
It is generated corresponding to one scanning cycle from Fig. 1, has a pulse width of one key time, and a pulse generation period of 4.5 milliseconds. The output of the delay flip-flop 70 is self-held via an AND circuit 71 and an OR circuit 69. The output of the NOR circuit 72 is added to the other input of the AND circuit 71. The output of this NOR circuit 72 becomes "0" when the initial clear signal IC is generated or when the scan cycle pulse 4.5M is generated, and the above self-holding is prohibited, but self-holding is possible at other times. Make it. Therefore, every time a 4.5M scan cycle pulse occurs, the state of switch 10/7-SW is loaded into the delay flip-flop 70;
is stored until it occurs. The reason why the switch output is latched in accordance with the slow (4.5 ms cycle) pulse 4.5M is to eliminate switch chattering. The latch circuits 14-3 and 14-4 corresponding to the switches FC-SW and SF-SW respectively include exclusive OR circuits 73 and 74 which receive the input signal and output signal of a delay flip-flop that latches the switch output. . These exclusive OR circuits 73 and 74 are connected to the finger code mode selection switch FC-SW.
Or single finger mode selection switch
This is to detect that the SF-SW has been switched from on to off or from off to on. For example, when the switch FC-SW switches from off to on, the switch output “1” indicates on.
At the generation timing of the 4.5M pulse to be taken in, a signal "1" appears at the input side of the delay flip-flop 75 of the latch circuit 14-3, and a signal "0" indicating the immediately previous off state appears at the output side of the delay flip-flop 75. appears. Therefore, the output signal ΔFC of the exclusive OR circuit 73 becomes "1" only during one key time. The same applies to the opposite case. That is, when the switch FC-SW is switched from on to off, the input side of the delay flip-flop 75 is "0", the output side is "1", and the output signal .DELTA.FC of the exclusive OR circuit 73 becomes "1". Similarly, switch
When the SF-SW switches from on to off or from off to on, the output △SF of the exclusive OR circuit 74 changes to 1 in response to the generation timing of 4.5M pulses.
It becomes “1” only once. The latch output of the latch circuit 14-1 is output as a channel mode signal 10/7 indicating the on/off state of the channel selection switch 10/7-SW. When this channel mode signal 10/7 is "0", all 10 channels are used for generating musical tones, and when it is "1", only seven predetermined channels are used for generating musical tones. Delay flip-flop 7 of latch circuit 14-3
The signal latched at 5 is a fin guard chord mode signal indicating whether the fin guard chord mode (FC) for automatic bass chord performance is selected.
Output as FC. The signal latched in the delay flip-flop of latch circuit 14-4 is output as a single finger mode signal SF indicating whether the single finger mode (SF) of automatic bass chord performance is selected. The signal latched to the delay flip-flop of the latch circuit 14-2 is transmitted to the memory function selection switch M-
The signal is applied to the AND circuit 76 of the mode switching control circuit 15 as a signal indicating the on/off state of the SW.
A signal indicating the output of this switch M-SW, automatic bass chord mode signal ABC, and rhythm run signal
A memory mode signal M is generated based on RUN and the lower key area key-on signal LKO. The circuit 77 in the mode switching control circuit 15 is
This is a circuit that generates a signal △ that becomes "0" for a certain period of time when a change detection signal △FC or △SF is generated. As described above, when the switch FC-SW or SF-SW is switched, the change detection signal ΔFC or ΔSF becomes "1" corresponding to the timing of generation of pulse 4.5M (see FIG. 5). When the change detection signal △FC or △SF becomes “1”, the flip-flop 80 is output via the OR circuits 78 and 79.
is reset. Flip-flop 80 takes in an input at the timing of clock pulse _φA , and determines its state at the timing of clock pulse _φB . Therefore, the output Q of flip-flop 80
As shown at 80-Q in FIG. 5, falls to "0" one key time later than the signal ΔFC or ΔSF. At the same time, the rotation output of flip-flop 80 rises to "1". This inverted output is applied to an AND circuit 81. A scanning cycle pulse of 4.5M is applied to other inputs of the AND circuit 81. Therefore, when the next scan cycle pulse 4.5M is generated, the AND circuit 81 is applied to the T input of the flip-flop 80.
“1” is supplied from the flip-flop 80, and after one key time, the state of the flip-flop 80 is reversed and the output Q (fifth
80-Q) in the figure rises to "1". Thereafter, since the inverted output of flip-flop 80 becomes "0", AND circuit 81 does not operate, and the state of flip-flop 80 does not change until it is reset again by signal ΔFC or ΔSF. The output Q of the flip-flop 80 is an AND circuit 8
2, the output of the AND circuit 82 is added to the NOR circuit 8
Join 4. Further, the output of the OR circuit 79 is inverted by an inverter 83 and applied to an AND circuit 82, and is also applied to a NOR circuit 85. Noah circuit 84 and 8
5 is a flip-flop, and the NOR circuit 8
The output of 5 is output as the SF/FC mode switching signal Δ. Before the signal △FC or △SF rises to “1”, the conditions of the AND circuit 82 are satisfied,
Due to the output "1" of the AND circuit 82, the output "0" of the NOR circuit 84, and the output "0" of the OR circuit 79, the output signal Δ of the NOR circuit 85 is "1". When the signal ΔFC or ΔSF becomes "1", the input of the NOR circuit 85 becomes "1", and the output signal Δ falls to "0". Since the output Q of the flip-flop 80 falls to "0" at the same time as the signal △FC or △SF falls to "0", the output of the AND circuit 82 remains "0", and the output signal △ of the NOR circuit 85 maintains “0”. The arrival of the next scan cycle pulse 4.5M causes flip-flop 8
When 0 is inverted, the output of the AND circuit 82 is “1”
Therefore, the output signal Δ of the NOR circuit 85 rises to "1". Therefore, as shown in FIG.
falls to "0" only for "4.5ms + α" (however, α is one key time). This signal Δ falls to "0" for "4.5 ms+α" when the change detection signal ΔFC or ΔSF is generated, and this occurs in the following case. When switching from automatic base code mode to normal mode (when switches FC-SW and SF-SW are both turned off) or vice versa (when switch FC-SW or SF-SW is turned on) ), or when switching from fingered chord mode to single finger mode in automatic bass chord mode, or vice versa. This signal Δ is used in the chord detection control circuit 30 (FIG. 1) to clear the chord memory. The signal △ is “0” not only when switching from automatic base code mode to normal mode (or vice versa), but also when switching modes within automatic base code mode (from FC to SF or vice versa). The reason for this is that even if the key press state is the same, the chords may be different in the finger chord mode and the single finger mode. Note that the output of the NOR circuit 85 is inverted by an inverter 86 and applied to an OR circuit 87. The output of the OR circuit 87 is used as a mode switching pulse ΔABC. Therefore, when the signal △ falls to “0”,
A mode switching pulse ΔABC is generated with the same time width (4.5ms+α) as this signal Δ. However, the pulse ΔABC generated in response to this signal Δ is much shorter than the original mode switching pulse ΔABC. Original mode switching pulse △
ABC is generated as follows. The finger code mode signal FC or single finger mode signal SF output from the latch circuit 14-3 or 14-4 is input to the OR circuit 88. The output of the OR circuit 88 is "1" in automatic base code mode (either FC or SF) and "0" in normal mode.
It is. The output of the OR circuit 88 is delayed by one key time by a delay flip-flop 89, and the output of the exclusive OR circuit 88 is delayed by one key time.
Add to 0. The output of the OR circuit 88 is directly applied to the other input of the exclusive OR circuit 90. Therefore, when the automatic base code mode changes to the normal mode (or vice versa), the exclusive OR circuit 90 generates a change detection pulse ΔABC' with a one-key time width. As shown in FIG. 5, the timing of generation of this change detection pulse ΔABC' is delayed by one key time from the scanning cycle pulse 4.5M. This is because the delay flip-flops in the latch circuits 14-3 and 14-4 cause the signal FC or
This is because SF changes. The flip-flop 91 is set by the change detection pulse ΔABC' output from the exclusive OR circuit 90, and the counter 92 is reset.
The flip-flop 91 is similar to the flip-flop 8.
0, it is controlled by clock pulse φ _AB , and there is a one key time delay between input and output. Therefore, the output Q of flip-flop 91 is connected to the set input (S) as shown at 91-Q in FIG.
1 from the rising edge of the change detection pulse △ABC′ applied to
It rises to “1” after a key time delay. Outputs Q and 91-Q of flip-flop 91 pass through OR circuit 87 and are output as mode switching pulse ΔABC. A scanning cycle pulse of 4.5M is applied to the count input (T) of the counter 92 via an AND circuit 93. Further, a two-phase clock pulse φ _AB is added as a control clock pulse for the counter 92. The counter 92 takes in the count input (T) signal at the timing of the clock pulse _φA , and
If the input signal is "1", it counts up by 1 and outputs the count result at the timing of clock pulse _φB . Outputs Q1 to Q3 of the 3-bit binary counter 92 are input to an AND circuit 94. A signal obtained by inverting the change detection pulse ΔABC' by an inverter 95 is applied to the remaining inputs of the AND circuit 94. The output of AND circuit 94 is applied to the reset input (R) of flip-flop 91, inverted by inverter 96, and applied to AND circuit 93. When the change detection pulse △ABC' is generated, the counter 92 is reset, and the counted value is shown as 9 in FIG.
It becomes 0 as shown in 2-Q. From then on, the counter 92 counts up every time the scanning cycle pulse 4.5M is generated, and when the count value reaches decimal "7", the binary outputs Q1 to Q3 all become "1", and the condition of the AND circuit 94 is satisfied. do. As a result, the flip-flop 91 is reset, the AND circuit 93 becomes inactive, and counting is stopped.
Therefore, the output Q of the flip-flop 91 takes the time equivalent to 7 periods of the scanning cycle pulse 4.5M (4.5ms x 7
= 31.5ms) becomes “1”. Therefore, the pulse width of the mode switching pulse ΔABC outputted from the OR circuit 87 in response to the output Q of the flip-flop 91 has a width of at least 31.5 ms. By the way, since the signal △FC or △SF is always generated immediately before the change detection pulse △ABC' is output from the exclusive OR circuit 90, the signal △FC or △SF is generated 2 key hours before the output Q of the flip-flop 91 rises to "1". The signal △ is “0”
The OR circuit 87 outputs (△
ABC) rises to “1”. Therefore, as shown in FIG. 5, the actual mode switching pulse ΔABC rises two key times before the output Q of the flip-flop 91, so its pulse width is 31.5ms+2α.
(α is one key time). NOR circuits 97 and 98 constitute a flip-flop, and automatic base code mode signal ABC is output from NOR circuit 97. counter 92 no 2
The outputs Q2 and Q3 of the 3rd and 3rd bits are applied to the AND circuit 100 via the OR circuit 99, and the other inputs of the AND circuit 100 receive the change detection pulse Δ.
The output of the inverter 95 that inverts ABC' is added, and the output of the AND circuit 100 is transferred to the AND circuit 101.
and 102. delay flip-flop 89
The output of is “1” in finger guard mode (FC) or single finger mode (SF), that is, in automatic base chord mode,
This output is applied to an AND circuit 102, inverted by an inverter 103, and applied to an AND circuit 101. When switching from normal mode to automatic base code mode, that is, switches FC-SW and SF
- When one of the -SWs is turned on from a state where both of them were off, a change detection pulse △ABC' is generated from the exclusive OR circuit 90, and one key time later, the output of the delay flip-flop 89 becomes "1".
stand up. When the pulse △ABC' becomes "1", the output of the AND circuit 100 (see 100 in Fig. 5)
falls to “0”. Since the output of the OR circuit 99 becomes "0" when the counter 92 is reset by the pulse ΔABC', it remains at "0" even after the output pulse ΔABC' of the AND circuit 100 is erased. When the count value of the counter 92 becomes 2 or more, the output Q2 or Q3 becomes "1", so the output of the AND circuit 100 rises to "1". AND circuit 1
The time when the output of 00 is “0” is a pulse
This is the time for two cycles of 4.5M (4.5ms x 2 = 9ms). Therefore, the AND circuits 101 and 102 are inoperative for 9 ms after the mode is switched, and the states of the flip-flops 97 and 98 are prevented from changing. When the output of the AND circuit 100 rises to "1", the condition of the AND circuit 102 is satisfied by the signal "1" from the delay flip-flop 89, and "1" is input to the NOR circuit 98. on the other hand,
The conditions of AND circuit 101 are not satisfied, and NOR circuit 9
“0” is input to 7. This causes the output of the NOR circuit 97, that is, the automatic base code mode signal.
ABC rises to “1” (see Figure 5). Similarly, when switching from automatic base code mode to normal mode, the states of flip-flops 97 and 98 are reversed after a 9ms delay, and
Signal ABC falls to “0” with a delay of 9ms. A signal indicating the on/off state of the memory function selection switch M-SW outputted from the latch circuit 14-2 is stored in the delay flip-flop 107 via the AND circuits 76, 104, 105 and the OR circuit 106. The AND circuit 104 is for taking in, and the AND circuit 105 is for self-holding. The automatic base code mode signal ABC output from the NOR circuit 97 is applied to the other input of the AND circuit 76. The AND circuit 104 has an AND circuit 76
In addition to the output of the autorhythm device 45 (first
The rhythm run signal RUN given from the circuit shown in FIG. 1 and the lower key range key-on signal LKO given from the chord detection control circuit 30 (FIG. 1) are input. The output of AND circuit 104 is taken into delay flip-flop 107 via OR circuit 106, and the output of delay flip-flop 107 is self-held via AND circuit 105. delay flip-flop 1
The output of 07 becomes the memory mode signal M. When automatic bass chord performance is selected (ABC is “1”), press the memory function selection switch M-
When the SW is turned on, the condition of the AND circuit 76 is satisfied. At this time, if the autorhythm is operating (RUN is "1") and some key is pressed in the predetermined lower key range (LKO is "1"), the AND circuit 1
04 is satisfied, and the delay flip-flop 10
7 is stored (memory mode signal M becomes "1"). The AND circuit 105 for self-holding includes, in addition to the output of the delay flip-flop 107, the output of the AND circuit 76, the rhythm run signal RUN, and the SF/FC.
Mode switching signal △ is input. Therefore, when the switch M-SW is turned off, when the automatic bass chord mode is turned off (ABC is "0"), or when the automatic rhythm stops,
(RUN is "0"), or when the finger code mode or single finger mode changes (Δ is "0"), the AND circuit 105 becomes inoperable and the memory mode signal M is cleared. Regarding the proper use of the keyboard and sound channel, the keyboard used in this example has keys C2 to C7.
It consists of 61 keys arranged in a row (in one row). The first step is to explain how to use the different key ranges on this keyboard.
Shown in the table.

[Table] In normal mode, that is, when automatic bass chord play is not selected, all keys on the keyboard C
2 to C7 are the first musical tone generation mode (melody performance)
used for. The key range used for this first tone generation mode will be referred to as the upper key range (denoted by U). In the case of automatic bass chord mode (ABC mode), the key range of one and a half octaves on the bass side from key C2 to F#3 is used for the second musical tone generation mode (automatic bass chord performance and automatic arpeggio performance, that is, accompaniment performance). It is used for the treble side keys G3 to C.
The key range up to 7 is used for the first tone generation mode (melody performance). The lower key range L is the key range of keys C2 to F#3 used for the second musical tone generation mode. This key range of keys C2 to F#3 functions as the upper key range U in normal mode, but
When in ABC mode, it functions as the lower key area L. Next, we will explain how to use different pronunciation channels. In the sound generation allocation circuit 18 (FIG. 1), data corresponding to each sound generation channel is processed in a time-division manner. There are 11 time-division channel timings in the sound generation allocation circuit 18, but one channel timing among them does not correspond to the actual sound generation channel. The actual number of sound generation channels (number of musical sound generation series) in the musical sound generation circuit 51 (FIG. 1) is ten. The reason for providing the extra channel timing is due to processing convenience in the multiplexing circuit 28 (FIG. 1). Table 2 shows how to use the 11 time-division channel timings in the sound generation allocation circuit 18.

[Table] In Table 2, channel timing "1"
are extra channel timings that do not correspond to the actual pronunciation channels, and channel timings "2" to "11" correspond to each of the 10 pronunciation channels. The symbol U indicates a channel to which keys in the upper keyboard range are assigned, that is, a channel used for the first musical tone generation mode (melody tone). Symbols L, P, and A indicate channels to which accompaniment tones based on pressed keys in the lower key range are assigned, that is, channels used for the second musical tone generation mode. L indicates a channel to which the chord constituent notes (key pressed notes in the lower key region L) are assigned, P indicates a channel to which the automatic bass note is assigned,
A indicates the channel to which the automatic arpeggio sound is assigned. X indicates a channel to be forcibly turned off (to clear the sound assignment). In the second performance, in the 10 channel mode (channel mode signal 10/7 is "0"), all channels 2 to 11 are used for the first tone generation mode U in the normal mode. Finguard chord mode for automatic bass chord playing
For FC, channels 2, 3, 5, 7, 9, 1
1 is used for the second musical sound generation mode L, P, and A, and the remaining channels 4, 6, 8, and 10 are used for the first musical sound generation mode U. however,
In single-finger mode SF, channel "3" is not used, and there are only three channels L for chord constituent notes. This is because in the single finger mode, tritones do not occur in chord constituent tones. Mode switching pulse △ABC
During the short period (31.5ms+2α) during which
5, 7, 9, and 11 are forcibly cleared. This is because changing the mode changes the tone generation mode of these channels 2, 3, 5, 7, 9, and 11 (from the first to the second, or vice versa), which causes problems in the assignment operation. This is to prevent this from happening. Table 2 shows that in the 7-channel mode (signal 10/7 is "1"), three channels "3", "8", and "10" are forcibly cleared. Regarding the proper use of the first musical tone generation mode U and the second musical tone generation modes L, P, and A, see 10 above.
This is the same as in channel mode. The time division channel timings "1" to "11" shown in Table 2 are set in the shift register 60 (FIG. 2) of the timing signal generation circuit 20 in the sound generation allocation circuit 18. The first stage Q1 to the eleventh stage Q11 of this shift register 60
The output timing (see 60-Q in Figure 3) is the second
This corresponds to channel timings "1" to "11" shown in the table. In FIG. 2, the outputs of each stage Q1 to Q11 of the shift register 60 are supplied to an allocation mode setting circuit 108 and an allocation prohibition circuit 109. The allocation mode setting circuit 108 sets the channel timing signals UchT, LchT, according to a predetermined allocation mode (see Table 2) corresponding to the selected mode.
Generates PchT and AchT. The upper key range channel timing signal UchT is generated in accordance with the time division timing of channel U for the first tone generation mode shown in Table 2. The lower key range channel timing signal LchT is generated in accordance with the time division timing of the accompaniment chord channel L shown in Table 2. Base channel timing signal PchT
is the channel P for automatic bass sound shown in Table 2.
is generated in accordance with the timing of The arpeggio channel timing signal AchT is generated in accordance with the timing of channel A for automatic arpeggio sounds shown in Table 2. Channel mode signal 10/ generated from mode selection circuit 13 in FIG.
7. The single-finger mode signal SF and the automatic base code mode signal ABC are supplied to the allocation mode setting circuit 108, and are set in a predetermined manner according to the states of these mode signals (as shown in Table 2).
Channel timing signals UchT-AchT are generated. In the allocation mode setting circuit 108, predetermined stage outputs Q2 to Q11 of the shift register 60
are synthesized to generate each channel timing signal UchT~
The logic circuit is constructed to obtain AchT. AND circuits 110, 111, and 112 are in stage Q when in 10 channel mode (signal 10/7 is “0”).
This is a circuit for selecting the outputs of Q3, Q8, and Q10. The OR circuit 113 is a circuit that synthesizes the upper key range channel timing signal UchT in the normal mode. The OR circuit 114 is a circuit that synthesizes the upper key range channel timing signal UchT in the automatic base chord mode ABC. OR circuit 115 is the lower key range channel timing signal
This is a circuit that synthesizes LchT. When in automatic base code mode (ABC is “1”), AND circuit 11
Signal via 6,117,118,119
UchT, LchT, PchT, AchT are output. When in normal mode (ABC is “0”), the signal UchT is sent from the AND circuit 120 via the OR circuit 121.
only is output. The logical formulas for generating each signal UchT to AchT are shown below. Note that 10/7 indicates the signal 10/7 inverted by the inverter 122. UchT=ABC・(Q4+Q6+10/7 ・Q8+10/7・Q10)+ ・(Q2+・10/7・Q3+Q4 +Q5+Q6+Q7+10/7 ・Q8+Q9+10/7・Q10 +Q11) LchT=ABC・(・10/7 ・Q3+Q5+Q7+Q9) PchT= ABC·Q2 AchT=ABC·Q11 The allocation prohibition circuit 109 generates an off-channel timing signal OFchT corresponding to the timing of the channel indicated by the cross mark in the second table. 7
When in channel mode (signal 10/7 is "1"), stages Q3, Q8, Q
An off-channel timing signal OFchT is generated corresponding to the output timing of 10. In addition, when in single finger mode (signal SF is "1"), a signal is sent via the OR circuit 128 and the AND circuit 123 corresponding to the output timing of stage Q3.
Occurs OFchT. Also, the mode switching pulse △
While ABC is being generated, AND circuit 129 is enabled, and signal OFchT is generated in accordance with the output timing of stages Q2, Q3, Q5, Q7, Q9, and Q11 combined by OR circuit 130. Channel timing signal UchT when in 10 channel mode (signal 10/7 is “0”),
Figure 6 shows examples of the states in which LchT, PchT, AchT, and OFchT occur. In the single finger mode SF, the signal LchT corresponding to channel "3" is not generated. This is the AND circuit 110 in FIG.
This is because it becomes inoperable. As shown in FIGS. 3 and 6, the timing of each channel occurs twice during one key time (22 μs). Details of Key Scanning Circuit 11 FIG. 7 is a diagram showing a detailed example of the key scanning circuit 11 in FIG. 1 in relation to the key switch matrix 10. Key scanning counters 131 and 132 of key scanning circuit 11 are supplied with two-phase clock pulses φ _AB (φ _A , φ _B ) for key scanning generated from timing signal generating circuit 20 (FIG. 2).
The hexadecimal counter 131 repeatedly adds up the signal "1" applied to the count input T at the timing of the clock pulse φ _AB . That is, at the timing of the clock pulse φ _A , the count input T is taken in and counted up, and at the timing of the pulse φ _B , the output state corresponding to the count result is set. Therefore, the hexadecimal counter 131 is counted up in accordance with the clock pulse φ _AB , and the state of its output changes every time the clock pulse φ _B rises, that is, every one key time shown in FIG. The count contents of the hexadecimal counter 131 are “0”, “1”, “2”, “4” in decimal notation,
"5", "6" (binary display "000", "001", "010"
”,
The number changes in the order of "100", "101", "110"), and skips over "3" in decimal representation ("011" in binary representation). The count content of the hexadecimal counter 131 is “6”
(“110”) to “0” (“000”), specifically, at the timing of the pulse φ _A just before the output of the counter 131 changes to “0” at the timing of the pulse φ _B , the carry signal CO is counter 13
1 and is supplied to the count input T of the hexadecimal counter 132. The hexadecimal counter 132 takes in the carry signal applied to the count input T at the timing of the pulse φ _A , counts up, and sets an output state corresponding to the count result at the timing of the pulse φ _B. In short, each time the output of the hexadecimal counter 131 becomes "0", the output of the hexadecimal counter 132 changes (increases by one count). The count content of hexadecimal counter 132 is "15"
When returning from (“1111”) to “0” (“0000”), specifically, at the timing of pulse φ _A just before the output of the counter 132 changes to “0” at the timing of pulse φ _B , the carry signal CO is counter 1
It is output from 32. The carry signal CO of this counter 132 is input to a delay flip-flop 133. The delay flip-flop 133 takes in the carry signal CO at the timing of the pulse _φA and outputs it at the timing of the pulse _φB . Therefore, the delay flip-flop 1 corresponds to one key time when the outputs of the counters 131 and 132 are all "0".
The output of 33 becomes "1". The output of this delay flip-flop 133 is a scan cycle pulse of 4.5M.
is supplied to each circuit as As will be described later, this scanning cycle pulse 4.5M corresponds to the timing of scanning the highest key C7. The output of hexadecimal counter 131 is applied to decoder 134, and the output of hexadecimal counter 132 is applied to decoder 1.
Join 35. The output of the decoder 134 is input to the note name line of the key switch matrix 10.
The output "0" of the decoder 134 is input to the note name C and F# lines, "1" is input to the B and F lines, "2" is input to the A# and E lines, "4" is input to the A and D# lines, and the G
"5" is input to the # and D lines, and G and C
“6” is input to the # line. Therefore, the count contents of the hexadecimal counter 131 are "0", "1",
The pitch name C, A#, A, G#, G, F changes as "2", "4", "5", "6", "0", "1"...
The 12 note names are repeatedly scanned in the order of #, F, etc. starting from the treble side. Outputs B52 to B of key switch matrix 10
11 corresponds to a half-octave group of keys C7 to C2. These outputs B52-B11 are applied to multiplexer 136 and hex counter 1
selected by the outputs BT0 to BT10 of the decoder 135 corresponding to the count values "0" to "10" of 32,
The lines are combined into one line 137. Table 3 shows the relationship between the key groups corresponding to the outputs B52-B11 of the key switch matrix 10 and the outputs BT0-BT10 of the decoder 135 that selects these outputs B52-B11.

[Table] The lowest key C2 is led to the same output B11 as the half-octave key group F#2 to G#2 above it. Therefore, a dedicated scanning input line CL is provided for this lowest key C2. The output "0" of the decoder 134 corresponding to the pitch name C is input to AND circuits 138 and 139. Decoder 1 for selecting the half-octave range to which the lowest key C2 belongs
The output BT10 of No. 35 is applied to an AND circuit 139, and a signal obtained by inverting the output BT10 by an inverter 140 is applied to an AND circuit 138. Therefore,
While the outputs BT0 to BT9 of the decoder 135 are being generated, the AND circuit 138 is enabled to operate, and based on the output "0" of the decoder 134, C7 and C
6, C5, C4, C3 or F#6, F#5,
The keys of F#4, F#3, and F#2 are scanned. When the output BT10 of the decoder 135 is generated, the AND circuit 139 becomes operational, and when the output "0" of the decoder 134 becomes "1", a scanning pulse is applied to the lowest key C2 via the line CL. The scan output of this lowest key C2 is the output B1 of the matrix 10.
Appears in 1. The scanning pulse on the line CL is also applied to an AND circuit 141 of the multiplexer 136, and the AND circuit 141 selects the scanning output of the lowest key C2 appearing on the output B11. When the output of the hexadecimal counter 132 is "0", the output B52 of the highest half-octave C7 to G6 is selected by the output BT0 of the decoder 135. Thereafter, as the count of the counter 132 progresses, the outputs B51...B11 of the lower key range are gradually selected. Further, while the output of the decoder 135 maintains the same value, the output of the decoder 134 increases from 1 to 1 from the treble side.
As it rotates, in the end, the key switch matrix 1
Each key of 0 is scanned in order from the treble side (from the highest note C7 to the lowest note C2). The output line 137 of the multiplexer 136 receives key data ("1" indicates key-on, "0" indicates key-off) that is time-division multiplexed in order from the treble side keys. The data on line 137 is outputted as key data KD via AND circuit 142. The width of one time slot (one key data) in the time-division multiplexed key data KD is one key time (see FIG. 3). The outputs of the counters 131 and 132 are key codes N1 to N4 and B1 to B3 indicating the key currently being scanned.
The scan key display line 12 (FIG. 1) is supplied as a signal to the scan key display line 12 (FIG. 1). Note code N1 that makes up the key code
~N4, the lower 3 bits N1 to N3 are the output of the hexadecimal counter 131, and the upper 1 bit N4 is 16
This is the least significant bit output of the advance counter 132. Octave codes B1 to B3 are hexadecimal counters 132
This is the upper 3 bits output. Note code N1~
Table 4 shows the relationship between the value of N4 and the pitch name, and Table 5 shows the relationship between the values of octave codes B1 to B3 and the octave key range.

【table】

[Table] Note that octave codes B3, B2, and B1 also take the values "110" (decimal 6) and "111" (decimal 7), but these do not correspond to the keyboard. signal
It corresponds to the timing of occurrence of BT112.13 and BT14.15. Decoder 1 corresponding to the key range of keys F#3 to C#2
35 outputs BT7, BT8, BT9 (see Table 3)
is input to the OR circuit 143. Furthermore, the signal of the scanning line CL of the lowest key C2 is also input to this OR circuit 143. The output of this OR circuit 143 becomes "1" corresponding to the scan timing of keys F#3 to C2 in the lower keyboard range used for automatic bass chord performance, and is used as the lower key range scan timing signal LK. Ru. This lower key area scanning timing signal
LK is input to a NAND circuit 144. A mode switching pulse ΔABC is supplied from the mode selection circuit 13 (FIG. 4) to the other input of the NAND circuit 144, and its output is applied to the AND circuit 142.
Therefore, during the short period (31.5ms+2α) during which the mode switching pulse ΔABC is generated, the output of the NAND circuit 144 becomes "0" at the lower key area scan timing, and the key data of the lower key area (F#3 to C2) is KD
is blocked by the AND circuit 142. This is to prevent an inconvenient allocation operation from being performed when switching modes. FIG. 8 shows a portion of keys C7 to C2 assigned to each time slot of key data KD. Also,
The generation timings of the outputs BT0 to BT15 of the decoder 135 are shown in BT0 to BT15 in FIG. below,
The timing at which each of the outputs BT0 to BT15 of the decoder 135 is generated will be referred to as block timing. One block timing is 6 key times. Furthermore, the generation timing of the lower key area scanning timing signal LK is shown as LK in FIG. Further, the generation timing of the lowest key C2 scanning timing signal CLT is shown as CLT in FIG. This signal CLT is a scanning pulse applied to the lowest key scanning line CL. Outputs BT5 and BT6 of the decoder 135 and the initial clear signal IC are input to the NOR circuit 145. These outputs BT5 and BT6 are the 1 immediately before the lower key area.
It corresponds to the scanning timing of octave (F#4 to G3). As shown in FIG. 8, the output of the NOR circuit 145 becomes "0" when the decoder outputs BT5 and BT6 are generated (and when the initial clear signal IC is generated). The output of this NOR circuit 145 is used as a cancel signal for memory release. The outputs BT0 and BT1 of the decoder 135 are input to an OR circuit 146, and a signal BT0.1 (see FIG. 8) is obtained. Also, the output of the decoder 135
Signals BT10 to 13 are obtained from the OR circuit 147 into which BT10 to BT13 are input, and BT12 and BT1
The signal BT1 is output from the OR circuit 148 which inputs 3.
2.13 is obtained, and a signal BT14.15 is obtained from the OR circuit 149 into which BT14 and BT15 are input. As shown in Figure 8, these signals BT1
0-13, BT12.13, and BT14.15 occur after the actual key scan. Processing for automatic bass chord performance or automatic arpeggio performance is performed in the extra scanning time that does not correspond to the key indicated by these signals. The output "0" of the decoder 134, that is, the signal corresponding to the pitch name C or F#, and the signal obtained by inverting the least significant bit N4 of the hexadecimal counter 132 by the inverter 151 are applied to the AND circuit 150. The C note timing signal CNT output from the AND circuit 150 becomes "1" when the note codes N1 to N4 obtained from the counters 131 and 132 are "0000", that is, at the timing of the C note, and is the 8th C note timing signal CNT. As shown in the figure, this occurs repeatedly every 12 key times. Incidentally, when the outputs of the counters 131 and 132 are all "0", the highest key C7 is scanned, so the scan cycle pulse 4.5M is generated corresponding to the scanning timing of the highest key C7 as shown in FIG. Ru. In addition, the outputs BT5 and BT of the decoder 135
6 is input to the NOR circuit 279, and the signal 5.6
is obtained. Overview of the time relationships of various processing operations Before we give detailed explanations of various processes such as assignment processing and automatic performance key data formation processing, we would like to briefly explain the time relationships in which these various processing operations are executed. An outline of the timing at which the process is executed is shown in Z in FIG. The key scanning period is the highest key C
This is 61 key times from the scanning timing of C.7 to the scanning timing of the lowest key C2. Z in FIG. 8 shows the processing operation timing in the normal mode. In the normal mode, all keys are treated as the upper key range, so the assignment process for the upper key range to the sound generation channel is performed in accordance with the all-key scanning timing. Note that the assignment processing for each pressed key is performed within one key time period in which the key data KD is generated. FC at Z in FIG. 8 indicates the processing operation timing in the fine guard code mode. In Finguard code mode, C7 to G3
The keys up to are the upper key range, and the keys from F#3 to C2 are the lower key range. Therefore, during the 42-key period from the scan timing of key C7 to the scan timing of key G3, the process of assigning the pressed key indicated by key data KD (the pressed key in the upper key range) to the sound generation channel in the upper key range is performed. It will be done. In Finguard chord mode, the keys pressed in the lower key range are directly sounded as chord constituent notes, so key F#3
At the key scan timing of the lower key area from C2 to C2, the pressed key indicated by the key data KD (the pressed key of the lower key area) is transferred to the sound generation channel of the lower key area (indicated by the channel timing signal LchT). channel). The key data KD (more specifically, the note timing) generated at the key scan timing of the lower key area from key F#3 to C2 is stored in the lower key area key data register 35 (inside the chord detection control circuit 30 in FIG. 1).
, and it is detected whether or not a chord is formed by the combination of pressed keys in the lower key area during the 12 key period immediately after the scanning timing of the lowest key C2. If the chord is not established, a process is performed in which the lowest note of the pressed key is set as the rhizome in the subsequent 12 key periods. On the other hand, during the 12 key time period when the signals BT12.13 are generated, the arpeggio sound key data forming circuit 44
(Fig. 1), arpeggio (ARP) homophonic processing is performed. This is a process of detecting sounds with the same sound in a different octave from among the lower key region pressed sounds assigned to the lower key region pronunciation channel. In Finguard chord mode (FC), keys in the lower key range are assigned as they are, so notes with the same name in different octaves may be assigned to different channels. In arpeggio performance, notes with same notes in different octaves are the same note (even if there are multiple notes, only one note)
Therefore, it is necessary to perform processing in advance to detect sounds with the same name in different octaves. Thereafter, arpeggio (ARP) processing is performed during the 12 key time period in which signal BT14.15 occurs. In this arpeggio (ARP) process, the number of keys pressed in the lower key range (notes after the same note process) is counted according to the value of the arpeggio pattern data ArpPT (FIG. 1). After the chord detection and arpeggio (ARP) processing is completed, automatic bass note P and automatic arpeggio note A are assigned to be produced during the 12 key time period when signal BT0.1 is generated. Of course, these automatic sound pronunciation assignment processes are performed using the pattern data BassPT,
This is done only when ArpPT is occurring.
This P and A pronunciation assignment processing timing overlaps with the upper key region pronunciation assignment processing timing,
One channel dedicated to each (PchT, AchT
Since the channel is assigned to the channel indicated by ), no inconvenience will occur. SF in Z in FIG. 8 indicates the processing operation timing in the single finger mode. In single finger mode, the lower key range is used to specify the root note of the chord and the type of chord, rather than specifying the chord constituent notes themselves. Therefore,
Sound generation assignment processing is not performed at the key scanning timing of the lower key area from keys F#3 to C2. At this scanning timing of the lower key area, processing is performed to detect the highest note among the keys pressed in the lower key area based on the key data KD of the lower key area. The most pressed key in this lower key range is the root note. This is because the root note is pressed as the highest note, and the key indicating the chord type is pressed on the lower note side than the key indicating the root note. At the 12 key time when signal BT12.13 occurs
SF chord assignment processing is performed. In this SF chord assignment process, key data SFKL of chord constituent notes is automatically formed by the SF chord key data forming circuit 43 (Fig. 1) based on the root note and chord type.
Based on this key data SFKL, the sound generation assignment circuit 18 performs assignment processing to the sound generation channels of the lower key range. Signal BT14.1
At the 12 key time when 5 occurs, arpeggio (ARP) processing is performed in the same way as in the Finguard chord mode (FC). Furthermore, during the 12 key time period in which the signal BT0.1 is generated, automatic bass note P and automatic arpeggio note A are assigned to be produced. The time required for processing related to automatic performance, such as chord detection, is 12 key hours because of the 12 note names (C, B,...
This is to match all the timings (note timings) of D, C#). The note name (note timing) corresponding to each key time is determined by the key scanning circuit 1.
Note code N1~ supplied from 1 (Figure 7)
Denoted by N4. Details of the key information converter 23 Details of the key information converter 23 in FIG. 1 are shown in FIG. 9. Note codes N1 to N4 supplied via line 12 from counters 131 and 132 (FIG. 7) of key scanning circuit 11 are applied to one input A of key code memory 24 and comparator circuit 25 in FIG. Line 1 from counter 132
Octave codes B1-B supplied via 2
3 are input to AND circuits 152, 153, and 154 of the octave code conversion circuit 26, respectively. The output of the inverter 155 is added to other inputs of the AND circuits 152, 153, and 154. OR circuit 15 only when assigning a bass note or arpeggio note
The output of the inverter 155 becomes "1" and the output of the inverter 155 becomes "0", but at other times the output of the inverter 155 is always "1". Therefore, the AND circuits 152, 153, and 154 are normally operable, and the octave codes B1, B2, and B3 supplied from the line 12 are output to the AND circuit 15.
2, 153, 154 and OR circuit 157, 15
8,159 and is output (without conversion). Note that the mode selection circuit 1 is included in the AND circuit 160.
Single finger mode signal SF from latch circuit 14-4 (FIG. 4) of No. 3 and key scanning circuit 11
The signal BT1 from the OR circuit 148 (FIG. 7)
2.13 has been added, and the output of the AND circuit 160 is "1" at the processing timing for assigning pronunciation of chord constituent notes in single finger mode (timing of BT12.13 shown in FIG. 8).
and AND circuit 1 via inverter 161
53 is inactive and octave codes B1 to B3
Change the value of Octave code conversion circuit 26
Octave code output from (usually B1,
B2, B3) are input to one input A of the key code memory 24 and comparison circuit 25. The key code memory 24 has key codes N1 to B.
7 shift registers 2 corresponding to each bit of 3
4-1 to 24-7. Each shift register 24-1 to 24-7 has 11 stages corresponding to the number of channel timings (see FIG. 6), and is synchronized with each channel timing 1 to 11 by a system clock pulse φ. Driven by shift. Therefore, shift register 24-1
The input and output channel timings of 24-7 to 24-7 match. The outputs of each of the shift registers 24-1 to 24-7 are returned to the input side via the gate section 24-G and are stored and held. Gate part 24-
G is a load signal LD at a certain channel timing
When is given, note codes N1 to N4 given from line 12 and octave codes B1 to B3 given from octave conversion circuit 26 are taken in and input to the first stages of shift registers 24-1 to 24-7. At this time, the load signal LD
The output of the NOR circuit 162 that inverts becomes "0", the output signals of the shift registers 24-1 to 24-7 are blocked by the gate section 24-G, and the load signal
The memory of the old key code stored in the channel where the LD occurred will be cleared. load signal
When LD is not occurring, the output of the NOR circuit 162 becomes "1", the outputs of the shift registers 24-1 to 24-7 are returned to the input side, and the key code stored corresponding to each channel is held. be done.
The load signal LD is generated from the sound generation assignment control section 19 (FIG. 1) in accordance with the channel timing when the key codes N1 to B3 supplied to the line 12 are to be newly assigned to a certain channel. be. Therefore, the key code memory 24
That is, the shift registers 24-1 to 24-7 store key codes indicating the sounds assigned to each channel, and these assigned key codes are output in a time-sharing manner in synchronization with the timing of each channel. be done. Among the key codes assigned to each channel output from the key code memory 24 in a time-divisional manner, 4-bit note codes N1 to N4 are output to the comparison circuit 2.
5 to the other input B, and the octave code B1
~B3 are input to OR circuits 163, 164, and 165 of the octave code conversion circuit 27. The octave code conversion circuit 27 is a circuit that converts the values of octave codes B1 to B3 during automatic arpeggio processing, and at other times, the octave codes B1 to B3 output from the key code memory 24 are used.
It passes through B3 as it is and is input to the other input B of the comparator circuit 25. Comparison circuit 25 generates a match signal EQ when the values of the key codes applied to both inputs A and B match. On the other hand, key codes N1 to B added to input A
3 corresponds to the key scanning timing, which does not change during one key time. On the other hand, the key codes N1 to B3 applied to input B change at each channel timing (FIG. 6). Since one key time corresponds to 22 channel timings, the key codes N1 to B3 corresponding to the key scanning timing are assigned to all (11) channels during one key time when they hold the same value. The comparison with the individual key codes N1 to B3 is performed twice.
That is, in the 11-bit time in the first half of one key time, it is determined whether the key code N1-B3 having the same value as the key code N1-B3 corresponding to the key scanning timing has already been assigned to any channel. General explanation of pronunciation assignment processing FIG. 10 shows a detailed example of the pronunciation assignment control section 19 and window circuit 21 in the pronunciation assignment circuit 18 (FIG. 1). AND circuits 166 and 1 of window circuit 21
67 is an AND circuit 142 of the key scanning circuit 11.
The key data KD outputted from (FIG. 7) are respectively input. The window circuit 21 sends the key data KD to the upper key area (first
tone generation) or the lower key region (second
(musical sound generation mode). The output of the NAND circuit 168 is added to the other input of the AND circuit 166. The automatic base code mode signal ABC from the NOR circuit 97 of the mode selection circuit 13 and the lower key area scanning timing signal LK from the OR circuit 143 (FIG. 7) of the key scanning circuit 11 are input to the NAND circuit 168. Ru. In the normal mode, the signal ABC is always "0" and the output of the NAND circuit 168 is always "1". Therefore,
The AND circuit 166 is always operational, and all key data from the highest key C7 to the lowest key C2
KD passes through the AND circuit 166 and is output as upper key range key data KU. Therefore, in normal mode, all keys are processed as keys belonging to the upper key range. When using automatic base code, signal ABC is “1”
It is. Therefore, the lower key area scanning timing signal LK
When this occurs, the condition of the NAND circuit 168 is satisfied, the output of the NAND circuit 168 becomes "0", and the AND circuit 166 becomes inactive. Therefore, the scanning timing of keys F#3 to C2 in the lower key area at which the lower key area scanning timing signal LK becomes "1" (see Fig. 8)
In this case, the AND circuit 166 does not operate, and the key data KD of these lower key areas F#3 to C2 does not become the upper key area key data KU. However, keys C7~G
At scan timing 3 (see Figure 8), the signal LK
is "0", and the output of the NAND circuit 168 becomes "1". Therefore, the key data KD of keys C7 to G3 passes through the AND circuit 166 and is output as upper key range key data KU. Therefore, in the automatic bass chord mode, some of the keys C7 to G3 are processed as belonging to the upper key range (first tone generation mode). The other inputs of the AND circuit 167 are inputted with the above-mentioned lower key area scanning timing signal LK and the finger chord mode signal FC output from the latch circuit 14-3 (FIG. 4) of the mode selection circuit 13. The output of this AND circuit 167 is the OR circuit 16
9 and output as lower key range key data KL. Therefore, the AND circuit 167 is enabled only in the fine guard chord mode of the automatic base chord (FC is "1"), and the lower key region scan timing signal LK generated when the lower key region scan timing signal LK is "1" is operable. Only the key data KD of keys F#3 to C2 are selected by the AND circuit 167 and output as lower key range key data KL. In the single finger mode, the AND circuit 167 does not operate, and the key data KD of the lower key range F#3 to C2 does not directly become the lower key range key data KL. Instead, the SF chord key data forming circuit 43 (FIG. 1) generates key data SFKL of chord constituent tones automatically formed for the single finger mode, and this key data SFKL is sent to the OR circuit 169. Input, lower key area key data
Output as KL. In the sound generation allocation control section 19, the window circuit 2
Based on the upper key range key data KU or lower key range key data KL distributed in step 1, the note corresponding to KU is assigned to the upper key range pronunciation channel, and the note corresponding to KL is assigned to the lower key range pronunciation channel. , respectively. As already mentioned, when the mode changes, the aspects of the upper key range channel and the lower key range channel change. That is, the manner in which channel timing signals UchT, LchT, PchT, and AchT are generated in the timing signal generation circuit 20 (FIG. 2) changes (see FIG. 6). These channel timing signals UchT, LchT, PchT, AchT are the first
The signal is supplied to the sound generation assignment control section 19 shown in FIG. 0, and controls the assignment operation. In the sound generation assignment control section 19, the upper key range key data KU is applied to an AND circuit 170, and the lower key range key data KL is applied to an AND circuit 171. AND circuits 170 to 173 are key data
This is to determine whether the conditions for newly assigning sounds corresponding to KU, KL, KP, and KA to any channel are satisfied. When the allocation condition is satisfied, a load signal LD is generated from AND circuits 170 to 173 via OR circuit 174 in accordance with the timing of the channel to be allocated.
This load signal LD is given to the key code memory 24 (FIG. 9), and the OR circuit 175, 1
The current key-on memory 177 and key-on memory 178 are stored via the current key-on memory 76. Both key-on memories 177 and 178 are 11 each.
Consists of a stage/1-bit shift register,
The shift is controlled by the system clock pulse φ. The signal "1" (load signal LD) taken into the shift register (key-on memory) 177, 178 at a certain channel timing is returned 11 bit times later (that is, at the same channel timing).
The shift register (key-on memory) 177,1
It is output from the final stage of 78. The output of the shift register (current key-on memory) 177 is self-held via an AND circuit 179 and an OR circuit 175. The output of the shift register (key-on memory) 178 is connected to an AND circuit 180 or 1
81 and an OR circuit 176. In the key-on memories 177 and 178, the key codes N1 to B3 stored corresponding to each channel in the key code memory 24 (FIG. 9) are associated with keys that are being pressed or keys that have been released. In other words, whether the key assigned to each channel is being pressed or released,
This is for time-divisionally storing information corresponding to each channel timing. When the key is being pressed, "1" stored based on the load signal LD is held, and the output is "1". When the key is released,
Self-holding AND circuit 179 or 180,1
81 becomes inactive, its memory is cleared, and the output becomes "0". Current key on memory 177
stores the key-on signal KON′ corresponding to the actual key on/off, and when the key is released, the key-on signal of the channel to which that key was assigned is stored.
KON' is cleared immediately. This key-on signal KON' indicating actual key on/off is supplied to the truncate circuit 22 (FIG. 1). Note that this current key-on memory 177 is not applied to bass notes, arpeggio notes, and lower key range notes (chord constituent notes) in finger mode. The key-on memory 178 is a key-on signal that takes into account the memory mode.
It memorizes KO1, and when in memory mode, a key-on signal is immediately issued even if a key in the lower range is released.
KO1 is not cleared and continues to be stored until a predetermined clearing condition is met. This key-on memory 17
The key-on signal KO1 outputted from 8 is used as a signal for controlling the sound production of musical tones. Sound generation assignment processing in the case of normal mode In the case of normal mode, as described above, the key data KD for all keys C7 to C2 are distributed by the window circuit 21 as upper key range key data KU. In addition, the timing signal generation circuit 20
From (Fig. 2), as shown in Fig. 6, upper key range channel timing signals UchT are generated corresponding to all channel timings "2" to "11" except channel timing "1" which is not used. , other channel timing signal LchT,
PchT and AchT are not generated at all. Furthermore, the signal
UchT is all channel timing “2” ~
The occurrence corresponding to "11" occurs when the 10 channel mode (10/7 is "0"), and when the 7 channel mode (10/7 is "1"), the second
Although the modes are different as shown in the table, the explanation below assumes that the mode is 10 channel mode. For example, key data at the scanning timing of key C4
Suppose that KD becomes “1”. At this time line 1
2 to the key code memory 24 and comparison circuit 2
5) Key codes B3, B2, which are input in Figure 9)
The values of B1, N4, N3, N2, and N1 are "0110000" (see Tables 4 and 5), which indicates the key C4. In FIG. 10, corresponding to the key data KD of this key C4, the upper key range key data KU becomes "1" for one key time, and this upper key range key data
The AND circuit 170 to which KU is input determines whether the assignment condition is satisfied. Other inputs of the AND circuit 170 include the upper key range channel timing signal UchT (FIG. 6) and the second half period signal H2 (61 in FIG. 3) generated from the flip-flop 61 (FIG. 2) of the timing signal generation circuit 20. −
Q), a truncate channel signal TRUN generated from the truncate circuit 22 (FIG. 1),
An unregistered signal output from the NOR circuit 182 and a signal obtained by inverting the key-on signal KO1 output from the key-on memory 178 by an inverter 183 are input. truncate channel signal
TRUN is a signal that becomes "1" corresponding to the timing of the earliest released channel among the upper key range channels that have already been released, and indicates that the newly assigned key should be assigned to this channel. It shows. This truncated channel signal
Details of the occurrence of TRUN will be described later. The unregistered signal is the key code N1~ corresponding to the key data KD (KU) to be assigned now.
When the same key code as B3 has already been assigned to any channel, it is "0", and when it has not been assigned to any channel yet, it is "1". In other words, the key data to be assigned now
If the same key code as the key code N1 to B3 corresponding to KD (KU) is already assigned to any channel, that key code N1 to B3
3 is supplied to the scan key display line 12 1
The comparison circuit 25 corresponds to the timing of any channel in the first 11 bit times of the key time.
A coincidence signal EQ is generated from (FIG. 9). This coincidence signal EQ is applied to AND circuit 183 in FIG. The other input of the AND circuit 183 receives a current key-on signal from the current key-on memory 177 via an AND circuit 184 and an OR circuit 185.
KON′ joins. A signal obtained by inverting the output of the OR circuit 187 by an inverter 186 is added to the other input of the AND circuit 184. In the case of upper key range assignment, the output of the OR circuit 187 is "0" and the AND circuit 184 operates. It's becoming possible. Therefore, the key assigned to the channel where the coincidence signal EQ was generated is currently being actually pressed (KON' is "1").
Under this condition, the output of AND circuit 183 becomes "1" and is input to AND circuits 188 and 189. The AND circuit 188 receives the upper key range channel timing signal UchT, and the AND circuit 189 receives the lower key range channel timing signal LchT. Therefore, when the coincidence signal EQ is generated corresponding to the upper key range channel, it is passed from the AND circuit 188 through the OR circuit 190 to the delay flip-flop 1.
"1" is stored in 91. Also, match signal EQ
is generated corresponding to the lower key range channel (although this cannot occur in the normal mode), "1" is stored in the delay flip-flop 193 from the AND circuit 189 via the OR circuit 192. Ru. Delay flip-flop 191, 193
The memories of are self-maintained via AND circuits 194 and 195, respectively. delay flip-flop 191,
The output of 193 is input to NOR circuit 182. Therefore, the key data KD to be allocated now
If (KU) has already been assigned to one of the upper key range channels and is currently being pressed (KON' is "1"), the output of the delay flip-flop 191 is output in the latter 11 bit time of one key time. continues to be "1", and the unregistered signal output from the NOR circuit 182 becomes "0". Conversely, the key data KD (KU) to be allocated now
If the channel has not yet been assigned to any channel, the outputs of the delay flip-flops 191 and 193 are "0" at the 11-bit time in the second half of one key time, and the unregistered signal becomes "1".
A signal S1 (FIG. 3) generated from the timing signal generation circuit 20 (FIG. 2) is inverted by an inverter 208 and applied to AND circuits 194 and 195, and is applied to the delay flip-flop at channel timing "1" at the beginning of one key time. 191,1
Clear the memory of 93. The reason why the second half period signal H2 is input to the AND circuit 170 is to perform the assignment in the second half period of one key time when a correct unregistered signal can be obtained. Further, the reason why a signal obtained by inverting the key-on signal KO1 by the inverter 183 is inputted to the AND circuit 170 is to perform a new assignment to a blank channel (KO1 is "1").
Furthermore, the reason why the unregistered signal is input to the AND circuit 170 is to prevent a key press sound that has already been assigned from being doubly assigned to another channel. When all the input signals of the AND circuit 170 are "1", the condition for making a new assignment is satisfied, and one of the upper key range channels (UchT) specified by the truncate channel signal TRUN in the second half of one key time. One load signal LD is generated from the AND circuit 170 via the OR circuit 174 corresponding to one channel timing. The key codes N1 to B3 of the line 12 are taken into the key code memory 24 (FIG. 9) in correspondence with the timing of one channel when the load signal LD is generated. In this way, a certain channel (load signal LD
The key data KD indicating the key (for example, C4) to be newly assigned to the channel in which the problem occurred is the key code N1, using the time division time slot.
~B3 (for example, a value indicating C4) and stored in the key code memory 24. In addition, a current key-on signal is sent to the current key-on memory 177 and key-on memory 178 (Fig. 10) in response to the channel timing at which the load signal LD is generated.
KON' and key-on signal KO1 are stored. The key codes N1 to B3 stored in the key code memory 24 (Fig. 9) corresponding to a certain channel based on the load signal LD are not deleted until the next time when another key code is assigned to that channel. . Key-on signal stored in current key-on memory 177 and key-on memory 178
KON' and KO1 are deleted as follows. The match signal EQ output from the comparison circuit 25 in FIG. 9, the output KON' of the current key-on memory 177, and the output of the inverter 197 are applied to the AND circuit 196 in FIG. Key data KD is applied to inverter 197 via OR circuit 198 and AND circuit 199. The output of the AND circuit 196 is inverted by a NOR circuit 200, and an AND circuit 179 for memory retention of the current key-on memory 177
is input. The output of the OR circuit 201 is applied to the other input of the OR circuit 198, but the output of the OR circuit 201 is "0" at the key scanning timing and does not affect the key data KD. Further, the output of the NAND circuit 202 is added to the other input of the AND circuit 199. NAND circuit 202
A single finger mode signal SF and a lower key range scanning timing signal LK are added to "0" is output to "1") to disable the AND circuit 199. This is because the key data KD of the lower key range is blocked by the AND circuit 199 since the key data KD of the lower key range is not directly used in the sound generation assignment processing in the single finger mode. The key data KD of the upper key range passes directly through the OR circuit 198 and the AND circuit 199 and reaches the inverter 197. Therefore, when a key in the upper key range is released, the key data KD corresponding to that key is “0”.
Therefore, the output of the inverter 197 becomes "1". At that time, the key codes N1 to B3 corresponding to the released key data KD are applied to one input A of the comparator circuit 25 in FIG. If it is assigned to a channel, a match signal EQ is generated corresponding to that channel. Furthermore, if the key assigned to that channel (the channel in which the coincidence signal EQ is generated) has been pressed until just before, the output KON' of the current key-on memory 177 is "1". Therefore, the condition of the AND circuit 196 is satisfied when the key that has been pressed until now is just released, and the output of the AND circuit 196 becomes "1" in accordance with the channel timing to which that key is assigned. (New key off pulse
NOFF). The output "1" of this AND circuit 196 is inverted by the NOR circuit 200, and "0" is added to the AND circuit 179, clearing the current key-on signal KON' of the channel to which the just-released key is assigned. . In this way, the current key-on signal KON' becomes "1" or "0" corresponding to actual key-on or key-off. Note that the off-channel timing signal OFchT and the initial clear signal IC generated from the timing signal generation circuit 20 (FIG. 2) are applied to other inputs of the NOR circuit 200. Therefore, in the channel where the off-channel timing signal OFchT (see Figure 6) is generated, the current key-on signal KON' is forcibly cleared, and the key is treated as being released even though it is not actually released. . The OR circuit 201 includes the output of the AND circuit 203 and the OR circuit 149 (seventh) of the key scanning circuit 11.
The signal BT14.15 (see FIG. 8) supplied from the circuit shown in FIG. AND circuit 203 is supplied with signals BT12.13 (see FIG. 8) supplied from OR circuit 148 (FIG. 7) of key scanning circuit 11 and latch circuit 14-3 (fourth
The finger code mode signal FC generated from the circuit shown in Fig.) is input. Processing in the arpeggio key data forming circuit 44 (FIG. 1) described later
What is the actual octave code of the assigned key code converted by the octave code conversion circuit 27 (Fig. 9) during the "ARP homophone processing" and "ARP processing" outlined with reference to the figure? Make the match signal EQ occur regardless,
This matching signal EQ is used for arpeggio processing. Match signal EQ generated at this time
In order to prevent the current key-on memory 177 from being cleared based on the above, during the arpeggio processing, "1" is generated from the AND circuit 203 and the OR circuit 201, and the key data KD is pseudo-transmitted via the OR circuit 198. I'm trying to set it to 1". The output KON' of the current key-on memory 177 is inverted by the inverter 204, and the AND circuit 205
added to. The upper key range channel timing signal UchT is added to the other input of the AND circuit 205, and its output is inverted by the NOR circuit 206 and sent to the self-holding AND circuit 180 of the key-on memory 178.
join. The upper key range channel timing signal UchT is applied to the remaining inputs of the AND circuit 180 via the OR circuit 207. When a key is released, the current key-on signal KON' of the channel to which that key is assigned becomes "0", and the inverter 204
The output of becomes "1". If the key is in the upper key range, the output of the AND circuit 205 becomes "1",
The output of the NOR circuit 206 becomes "0" and the AND circuit 180 becomes inactive. Therefore, in the case of the upper key range, as soon as the current key-on signal KON' stored in the current key-on memory 177 becomes "0", the key-on memory 178 is also cleared. Therefore, the key-on signal KO1 in the upper key range corresponds to the actual key press,
It becomes “1” or “0” in response to key release. Note that an upper key range channel timing signal UchT and a lower key range channel timing signal LchT are applied to the AND circuit 180 via an OR circuit 207, and a key-on signal for the upper or lower key range is applied.
This AND circuit 180 is for clearing KO1, and is always inoperable at timings other than the upper key range and lower key range channels. Another self-holding AND circuit 181 is for clearing the key-on signal KO1 of the bass sound channel (channel of signal PchT) and the arpeggio sound channel (channel of signal AchT), and is for clearing the key-on signal KO1 of the bass sound channel (channel of signal PchT) and the channel of upper and lower key ranges. The timing is always inactive. Note that an off-channel timing signal OFchT is applied to other inputs of the NOR circuit 206.
At the channel timing when this signal OFchT is generated, the output of the NOR circuit 206 becomes "0", and even if the key is not actually released, the key-on signal KO1
is forcibly cleared. Sound assignment in case of fin guard chord mode In case of fin guard chord mode, fin guard chord mode signal FC and automatic base chord mode signal ABC are "1". As described above, the window circuit 21 outputs the key data KD of keys C7 to G3 as upper key range key data KU, and outputs the key data KD of keys F#3 to C2 as lower key range key data KL. Further, from the timing signal generation circuit 20 (FIG. 2), the signal shown in FIG.
As shown in the ABC column, channel timing signals UchT, LchT,
PchT and AchT occur respectively. The pronunciation assignment processing operation based on the upper key range key data KU is the same as in the normal mode described above. The only difference is that in normal mode, the key data KD of all keys becomes the upper key range key data KU, whereas in automatic base chord mode (finger chord mode and single finger mode), some key data KD becomes upper key data KU. Key data for keys C7 to G3
KD becomes the upper key range key data KU, and in normal mode, the upper key range channel timing signal UchT is generated corresponding to all sounding channels, whereas in automatic bass chord mode, only some channels are generated. The only difference is that the upper key range channel timing signal UchT is generated corresponding to the sound generation channel of . In the sound generation assignment control unit 19 shown in FIG. 10, the lower key range key data KL is input to an AND circuit 171. When a key in the lower key area F#3 to C2 is pressed, the key data KL becomes "1" for one key time at the key scanning timing of that key. AND circuit 1
The other inputs of 71 are inputted with the lower key area channel timing signal LchT, the second half period signal H2, the truncate channel signal TRUN, the unregistered signal, and a signal obtained by inverting the key-on signal KO1 by the igaverter 183. When the lower key range key data KL is generated, the truncate channel signal TRUN becomes "1" corresponding to the timing of the earliest key released channel among the lower key range channels. If the key codes N1 to B3 corresponding to the currently occurring lower key range key data KL have already been assigned to any of the lower key range channels, the comparison circuit 25
A coincidence signal EQ is generated from (FIG. 9) and input to the AND circuit 183 in FIG. 10. The output "1" of this AND circuit 183 is transferred to the delay flip-flop 19 via an AND circuit 189 which is operable by the lower key range channel timing signal LchT.
3 is stored. Therefore, if the key corresponding to the currently generated lower key range key data KL has already been assigned, the output of the delay flip-flop 193 becomes "1" continuously during the 11-bit time in the latter half of one key time. This delay flip-flop 193
The output is supplied to other circuits as a signal LKOEXT, inverted by a NOR circuit 182, and inputted to an AND circuit 171 as an unregistered signal. When the conditions of the AND circuit 171 are satisfied, the load signal LD is generated and the currently generated key data is
The key codes N1 to B3 corresponding to KD (KL) are stored in the key code memory 24 (FIG. 9), and at the same time, the current key-on signal KON' and the key-on signal KO1 are stored in the current key-on memory 177 and the key-on memory 178. In this manner, in the fin guard chord mode, the keys that are pressed in the lower key range are assigned to be sounded in the lower key range channel, and the pressed keys (usually a plurality of keys) in the lower key range are sounded as accompaniment chords. In the fine guard chord mode, the current key-on signal KON' in the lower key range is erased when the condition of the AND circuit 196 is satisfied (that is, when the condition of (when the previously held key is newly released). The key-on signal KO1 of the lower key area in the key-on memory 178 is erased as follows. Memory mode signal M output from mode switching control circuit 15 (FIG. 4) is inverted by inverter 209 and input to AND circuit 210. The other inputs of the AND circuit 210 are applied with a signal obtained by inverting the fine guard code mode signal FC and the current key-on signal KON' by the inverter 204. Therefore,
In Finguard code mode (FC is “1”) and not in memory mode (M is “0”)
When the key in the lower key range is actually released (KON' is "0"), the condition of the AND circuit 210 is satisfied. The output “1” of the AND circuit 210 is applied to the AND circuit 212 via the OR circuit 211. AND circuit 2
The lower key range channel timing signal LchT is added to the other input of 12, and the current key-on signal KON' which has become "0" is assigned to the lower key range channel (the output of the AND circuit 210 is "1"). ” occurs at the timing of the signal LchT), the output of the OR circuit 211 (and circuit 2
10 output "1") and is added to the NOR circuit 206. Eventually, the output “1” of the AND circuit 210 is inverted by the NOR circuit 206, and the key-on memory 17
The self-holding AND circuit 180 of No. 8 is made inactive, and the key-on signal KO1 is cleared. Therefore,
If the fine guard chord mode is not the memory mode, when a key in the lower key range is actually released, the key-on signal KO1 of the channel to which that key is assigned is cleared. In the memory mode (M is "1"), the output of the inverter 209 is "0" and the AND circuit 210 is inoperative. Therefore, when the key in the lower range is actually released, the current key-on signal is generated.
Even if KON′ becomes “0”, the key-on signal KO1
is not cleared. Therefore, in the memory mode, based on the key-on signal KO1 which remains "1" even after the key is actually released, the sound of the key in the lower range continues to be produced even after the key is released. The AND circuit 213 clears the key-on signal KO1 in the memory mode. The AND circuit 213 has a current key-on signal.
A signal obtained by inverting KON' with an inverter 204, key data KL of the lower key range output from the OR circuit 169 of the window circuit 21, a signal obtained by inverting the output LKOEXT of the delay flip-flop 193 that stores the coincidence signal EQ with an inverter 214, and A second half period signal H2 is input. The output of AND circuit 213 is applied to AND circuit 212 via OR circuit 211. When a new key is pressed in the lower key area, the key data KL becomes "1" at the scanning timing of that key. Since this key has not been pressed (i.e., not assigned) until now, no coincidence signal EQ is generated, and the delay flip-flop 193 is output during the second half of one key time.
LKOEXT becomes "0" and the output of inverter 214 becomes "1". Therefore, the second half period signal H2
(See Figure 3) occurs, the AND circuit 21
Output of inverter 214 and key data added to 3
If KL are both "1", this indicates that a new key has been pressed in the lower key area. When a new key is pressed in the lower key range, during the latter 11 bit time corresponding to the channel timing when the key is actually released (KON' is "0" and the output of the inverter 204 is "1"). “1” is output from the AND circuit 213. In the AND circuit 212 to which the output of the AND circuit 213 is input via the OR circuit 211, the lower key range channel timing (LchT
The output “1” of the AND circuit 213, which occurs when the output signal is “1”), is selected and added to the NOR circuit 206. The AND circuit 180 becomes inoperable due to the output "0" of the NOR circuit 206, and the key-on signal KO1 of the lower key range, which was held at "1" even after the key is actually released, is cleared to "0". In other words, in the memory mode, the key-on signal KO1 is retained even after the key in the lower key area is released, but if any key is subsequently pressed in the lower key area, the actual key-on signal held until then is Key-on signal of released key
Clear all KO1. Of course, on the one hand, as already mentioned, the load signal LD is generated for the newly pressed key, and the current key-on signal KON' and the key-on signal KO1 are newly stored. Incidentally, the coincidence signal EQ generated regarding the lower key range channel timing is delayed by a flip-flop 193.
In the case of the finger code mode, the output of the AND circuit 184 is applied via an OR circuit 185 to the other input of the AND circuit 183 which selects the matching signal EQ to be stored in the EQ. AND circuit 1
The current key-on signal KON' and the output of the inverter 186 are applied to 84. At the lower key area scanning timing in the finger chord mode (see LK in FIG. 8), the single finger mode signal SF and signal BT1 are applied to the OR circuit 187.
2.13 and BT14.15 (Figure 8) are “0”
Therefore, the output of the inverter 186 becomes "1". This causes the current key-on signal to
KON' is added to the AND circuit 183 via the AND circuit 184, and "1" is stored in the delay flip-flop 193 only when the key assigned to the lower key range channel where the coincidence signal EQ is generated is actually being pressed. be done. As mentioned above, the reason why the current key-on signal KON' is used instead of the key-on signal KO1 as a condition for storing the matching signal EQ for the lower key range channel in the fine guard chord mode is because the output of the delay flip-flop 193
Key-on signal KO in memory mode using the signal inverted from LKOEXT by inverter 214
This is because 1 is cleared. When in memory mode, the key-on signal KO1 remains even after the key is released.
becomes “1”, so if this key-on signal KO
1 to store the coincidence signal EQ in the delay flip-flop 193, when the same key is pressed again after the key is released, the signal LKOEXT becomes "1" and the AND circuit 213 cannot detect a new key press. , the memory 178 cannot be cleared. Therefore, in the fine guard code mode, the current key-on signal KON' is used to store the coincidence signal EQ in the delay flip-flop 193. Details of the truncate circuit 22 A detailed example of the truncate circuit 22 in FIG. 1 is shown in FIG. 11. In FIG. 11, a 4-bit adder 216 and four 11-stage/1-bit shift registers 217 to 220 constitute a counter, and for each channel in which the key is released, Count the number of keys in a time-division manner. The shift registers 217 to 220 are shift-controlled by the system clock pulse φ, and the count value for each channel, which is output in a time-division manner corresponding to the timing of each channel from the final stage, is sent to the adder 216. It is returned to inputs A1 to A4.
The adder 216 adds the signals applied to the carry input Ci from the AND circuit 221, and outputs S1 to S.
4 is input to shift registers 217-220 via AND circuits 222-225. AND circuit 2
The output of the NOR circuit 226 is added to the other inputs 22-225. A current key-on signal KON' of each channel is applied to the NOR circuit 226, which is output in a time-divisional manner from the current key-on memory 177 of the sound generation assignment control section 19 shown in FIG. Therefore, at the channel timing when the current key-on signal KON' is "0" (that is, when the key is actually released), the AND circuits 222 to 225 become operational and counting becomes possible. At the channel timing during key depression, the signal KON' is "1" and the output of the NOR circuit 226 is "0", so the AND circuits 222 to 225 become inactive and the count value is cleared. In addition, when the initial clear signal IC is generated or the off-channel timing signal OFchT
At the channel timing when , the output of the OR circuit 227 becomes "1", which is inverted by the NOR circuit 226 to disable the AND circuits 222 to 225. In this case, counting operation is impossible, but the output “1” of the OR circuit 227 is
28 to the shift register 21 for the least significant bit.
7 is input, and the count value is forcibly set to “0001”. The AND circuit 221 receives a second half period signal H2 supplied from the timing signal generation circuit 20 (FIG. 2).
and the new key off signal NKOF supplied from the OR circuit 229 of the sound generation assignment control section 19 in FIG.
is input. This new key off signal NKOF is generated when any key is newly released. When a key previously assigned to any channel is newly released, a new key off pulse NOFF is generated from the AND circuit 196 in FIG. 10 at the channel timing. This new key off pulse NOFF is transmitted from the AND circuit 230 or 231 to the OR circuit 232 or 233.
delay flip-flop 234 or 2
35. An upper key range channel timing signal UchT is applied to the other input of the AND circuit 230, and a new key off pulse NOFF generated corresponding to the upper key range channel is stored in the delay flip-flop 234. The other input of the AND circuit 231 is a lower key range channel timing signal.
LchT is added, and the new key off pulse NOFF generated corresponding to the lower key range channel is stored in the delay flip-flop 235. The memories in delay flip-flops 234 and 235 are self-maintained via AND circuits 236 and 237. AND circuits 236 and 237 are rendered inactive at the beginning of one key time by a signal obtained by inverting signal S1 (FIG. 3) by inverter 208, and the memories in delay flip-flops 234 and 235 are cleared. Therefore, when the key assigned to the upper key range channel is newly released, the output of the delay flip-flop 234 becomes "1" continuously for at least the latter 11 bit times of one key time. The output of this delay flip-flop 234 is output from the AND circuit 23.
8, it is selected only at the timing of the upper key range channel by the signal UchT, and is outputted as the new key off signal NKOF via the OR circuit 229. On the other hand, when the key assigned to the lower key range channel is newly released, the delay flip-flop 235
The output of is “1” continuously for at least the latter 11 bit time of one key time, and this output “1”
is selected at the lower key region channel timing by the signal LchT in the AND circuit 239, and is outputted as the new key off signal NKOF via the OR circuit 229. In the AND circuit 221 of FIG. 11, the signal NKOF is passed by the second half period signal H2 in the second half 11 bit time of one key time when the new key off signal NKOF becomes valid. As described above, the new key off signal NKOF is generated corresponding to either the upper key range channel or the lower key range channel group. Therefore, adder 216 and shift registers 217 to 22
With a counter consisting of 0, a new key off signal is generated for each channel group in the upper or lower key range.
Count NKOF. For example, if the newly released key is assigned to the upper key range channel, the channel of the upper key range channel that has already been released (the channel with KON′ “0”)
Each count is incremented by one based on the new key off signal NKOF. The count value of the channel whose key was released the oldest has the largest value because the number of keys released subsequently is the largest. The count value of each channel output from the shift registers 217 to 220 is output from one input A of the comparator 240 and the AND circuit 24 of the maximum value memory 241.
2 to 245 are input. The maximum value memory 241 is a circuit that stores the maximum count value, and its output is added to the other input B of the comparator 240. The maximum value memory 241 includes delay flip-flops 247 to 250 for storing the maximum count value, and an AND circuit 251 for self-holding the stored maximum count value.
254 and AND circuits 242 to 245 for loading the maximum count value. When the signal S1 (see Figure 3) becomes "1" at the first channel timing of one key time,
The output of the NOR circuit 255 becomes "0", the self-holding AND circuits 251 to 254 become inoperable, and the maximum value memory 241 is cleared. Therefore, the minimum value "0000" is initially output from the memory 241. The count value of each channel sequentially output from the shift registers 217 to 220 and the output of the maximum value memory 241 are compared by the comparator 240, and when A>B, that is, the shift register 21
The count values output from 7 to 220 are stored in memory 2.
41, the AND circuit 256
"1" is output for. AND circuit 256
The other input is the output of the OR circuit 257 in FIG.
UchT・KU＋LchT・KL are added. The output of this OR circuit 257 is the output of an AND circuit 258 which inputs the upper key range channel timing signal UchT and the upper key range key data KU, and the input of the lower key range channel timing signal LchT and the lower key range key data KL. If the key data KD to be assigned is in the upper key range (KU is "1"), the signal is
It becomes "1" at the timing of UchT, and if the key data KD to be assigned is for the lower key range (KL is "1"), it becomes "1" at the timing of signal LchT. For example, if the currently supplied key data KD is for the upper key range, the output of the AND circuit 256 becomes "1" only when A>B is established at the upper key range channel timing. AND circuit 256
AND circuits 242 to 245 by the output "1" of
becomes operational, and shift registers 217 to 22
Flip-flops 247 to 250 that delay the output of 0
Incorporate into. In this way, the count values of each channel in one of the channel groups in the upper key range or the lower key range are sequentially compared, and the larger count value is stored in the memory 241. Therefore, when the first 11 bit time of one key time ends, the comparison for all channels is completed and the true maximum count value is stored in the memory 241. In the 11 bit time in the second half of 1 key time,
It is detected which channel the true maximum count value stored in the memory 241 belongs to, that is, which channel was the one whose key was released the earliest. That is, during the 11-bit time in the latter half of one key time, the true maximum count value stored in the memory 241 and the count value of each channel are compared in the comparator 240, and a match is output (A= B) is “1”
becomes. This coincidence output (A=B) is the AND circuit 2
Truncated channel signal through 60 TRUN
is output as The maximum count value channel is 1
There may be more than one, and in that case, coincidence outputs (A=B) occur at multiple channel timings. However, once the load signal LD is generated based on the truncate channel signal TRUN, the AND circuit 260 outputs a coincidence output (A
=B) is now being prevented. The delay flip-flop 261 is cleared at the beginning of one key time by applying a signal "0", which is the inverted version of the signal S1 (FIG. 3), to the AND circuit 246, and the output of the inverter 262, which has inverted its output, is initially It is set to “1”. Inverter 2
The output of 62 is applied to an AND circuit 260. Therefore, initially, the coincidence output of comparator 240 (A=
B) passes through the AND circuit 260, and a truncated channel signal TRUN is generated. When the load signal LD is generated in the circuit of FIG. 10 based on this truncate channel signal TRUN, this load signal LD is also applied to the AND circuit 263 of FIG. is memorized. As a result, the output of the inverter 262 becomes "0", the AND circuit 260 becomes inoperable, and from now on, the coincidence output (A
Even if =B) occurs, the truncate channel signal
TRUN is not generated. The output of the NOR circuit 265, which is added to the other inputs of the AND circuit 263, is always "1" when assigning keys in the upper key range or the lower key range. The NOR circuit 265 includes AND circuits 266 and 2
67 outputs are added. The AND circuit 266 is supplied with the lower key range any key on signal LKAKO supplied from the lower key range key on memory 39 (Fig. 1), the arpeggio timing signal AT supplied from the arpeggio sound key data forming circuit 44 (Fig. 1), and the arpeggio sound key on signal LKAKO supplied from the lower key range key on memory 39 (Fig. A horizontal channel timing signal AchT is input.
The AND circuit 267 receives the signal LKAKO, the base timing signal BT supplied from the base tone key data forming circuit 42 (FIG. 1), and the base channel timing signal PchT. When the AND circuit 266 or 267 performs the process of assigning arpeggio notes or bass notes, a condition is satisfied, the output of the NOR circuit 265 is set to "0", and the AND circuit 263 blocks the load signal LD. This is the AND circuit 172 or 17 in Figure 10 for assigning arpeggio notes or bass notes.
This is to prevent the load signal LD generated from 3 through the OR circuit 174 from being stored in the delay flip-flop 261. As will be described later, the truncate channel signal TRUN is not used in the process of assigning arpeggio notes or bass notes, and the load signal LD is generated independently of the truncate channel signal TRUN. this signal
When the load signal LD unrelated to TRUN is stored in the delay flip-flop 261, key data in the upper key range (particularly those generated at the timing of the signal BT0.1 shown in FIG. 8) is processed in parallel. Since this would cause problems in the allocation process, the output of the NOR circuit 265 is used to prohibit the allocation process. Chord Detection in Finguard Chord Mode A detailed example of the chord detection control circuit 30 in FIG. 1 is shown in FIG. 12. In FIG. 12, key data supplied from the key scanning circuit 11 (FIG. 7)
KD and the lower key range scanning timing signal LK (see FIG. 8) are input to the AND circuit 268. Therefore, only the key data KD of the lower key range F#3 to C2 is selected by the AND circuit 268. Chord detection control circuit 3
0, chord detection is performed based on the lower key range key data LKKD output from the AND circuit 268. Lower key area key data LKKD is lower key area F#3~C
2, which key is being pressed is indicated by the presence or absence of a pulse in each key scanning time slot. The lower key range key data LKKD is applied to the AND circuit 269 and is also sent to the delay flip-flop 27 via the OR circuit 270 in the SF root note detection priority circuit 32.
1 is stored. The delay flip-flop 271 is driven every key period by the key scanning clock pulse φ _AB , and its output is sent to the AND circuit 2.
72 and is self-maintained via the OR circuit 270. A cancel signal is applied to the other input of the AND circuit 272 from the NOR circuit 145 (FIG. 7) of the key scanning circuit 11. As shown in FIG. 8, the cancel signal is a signal that remains "0" for 12 key periods before the lower key area scanning timing starts, and during this period, the delay flip-flop 271
memory is cleared. The output of the OR circuit 270 is output as a lower key range key-on signal LKO. This lower key range key-on signal LKO is generated when any key is pressed in the lower key range, from the scan timing of the highest note among the pressed keys (because it is scanned from the treble side) to the next scan cycle. Immediately before the signal falls to “0” (G4 shown in Figure 8)
It remains "1" continuously until the scanning timing of The output of delay flip-flop 271 is inverted by inverter 273 and applied to AND circuit 274. A single finger mode signal SF supplied from the latch circuit 14-4 (FIG. 4) of the mode selection circuit 13 is applied to the other input of the AND circuit 274. The output of AND circuit 274 is inverted by inverter 275 and applied to AND circuit 269. Signal SF when in Finguard code mode
is "0", so the output of the AND circuit 274 is "0", the output of the inverter 275 is "1", and
The AND circuit 269 always passes the lower key range key data LKKD provided from the AND circuit 268. Lower key range key data passed through AND circuit 269
LKKD is 12 via OR circuits 276 and 277
The data is input to a lower key range key data register 35 consisting of a stage/1 bit shift register. This register 35 is shift-driven by the key scanning clock pulse φ _AB , and is driven by the key scanning clock pulse φ AB, and is used for lower key area key data.
Move LKKD sequentially within register 35.
The output Q12 of the final stage of the register 35 is passed from the AND circuit 278 to the OR circuit 277 to the first
returned to the stage. The other inputs of the AND circuit 278 are a signal 5.6 supplied from the NOR circuit 279 (FIG. 7) of the key scanning circuit 11 and a signal BT14.6 supplied from the OR circuit 149 (FIG. 7).
A signal 14.15 which is an inversion of 15 is input. Signal 5.6 is generated at the generation timing (block timing) of outputs BT5 and BT6 of the decoder 135 in FIG. 7 (see BT0 to BT15 in FIG. 8).
In other words, 12 just before the lower key area scan timing starts.
During the key time, it becomes "0" and the memory of all stages of the register 35 is cleared. After that, the lower key area key data generated at the lower key area scanning timing
LKKD is taken into the shift register 35. Since the shift register 35 has 12 stages, key data for 12 notes from F#3 to G2 is taken in at block timings BT7 and BT8 (Figure 8), and each key data is delayed by 12 key times. is output from the final stage Q12. Since the signals 5.6 and 14.15 are both "1" at the lower key area scanning timing, the captured key data LKKD is self-held via the AND circuit 278. Block timing BT9, BT1
When it reaches 0, the imported key data of F#3 to G2 are read in order from the treble side according to the scanning order (F#3, F
3, E3...G2) from the final stage Q12 of the register 35, and is returned to the first stage Q1 via the AND circuit 278 and OR circuit 277. At this time, keys F#2, F2, . Therefore, in the OR circuit 277,
The currently scanned key data LKKD and the already stored key data with the same name one octave higher are OR-combined. Therefore, the lower key range key data register 35 stores which key with pitch name C to C# is pressed in the lower key range, regardless of the octave.
This memory is held until the AND circuit 278 becomes inactive at the timing of the signals BT14.15, that is, during the timings BT10 to BT13 (see FIG. 8) after the lower key area scanning is completed. Since the output of the final stage Q12 of the shift register 35 is the key data LKKD delayed by 12 key times, it corresponds to the scanning timing of each of the 12 note names C to C#. That is, the shift register 35
The note names of the data output from the final stage Q12 are indicated by note codes N1 to N4 generated from the key scanning circuit 11 (FIG. 7). Block timing BT10 or BT12
The first key time is the note timing of C, and the block timings BT10 and BT11 are 12
Key time or block timing BT12
Each key time in the 12 key times of BT13 (and BT14 and BT15) is the 12 note names C, B, A#,
...Sequentially corresponds to D and C#. The shift register 35 sequentially receives key data generated in the order of high notes, so data for each note name is arranged in order from the low note side in each stage from the first stage Q1 to the final stage Q12. When detecting a chord, the key data (substantially note data) output from the final stage Q12 of the shift register 35 is regarded as 1 degree (root note), and the interval relationship of a predetermined degree is determined. Check whether certain key data exists in other stages. Therefore, the output of the first stage Q1 of the shift register 35 is set to a minor second 2 ^b , Q2 is a major second 2,2, Q3 is a minor third 3 ^b , Q4 is a major third 3, and Q5 is a perfect fourth 4.
Q6 reduced 5th 5 ^b , Q7 perfect 5th 5, Q8 minor 6th 6 ^b , Q9 major 6th 6, Q10 minor 7th 7 ^b ,
Q11 is treated as a major seventh degree 7. Each stage Q1 of the shift register 35 at each key time of block timings BT10 and BT11 or BT12 and BT13 (see FIG. 8).
Table 6 shows some of the note names of the key data (note data) output from ~Q12.

[Table] The AND circuit 280 is for detecting a triad (major chord or minor chord), and shifts the output of stage Q12 of the shift register 35 corresponding to the 1st (root note) and the perfect 5th. The output of the stage Q7 of the register 35 is inputted, and the output of the stage Q2 corresponding to the major second and the perfect fourth are inputted.
Signals obtained by inverting the output of the stage Q5 corresponding to the degree and the output of the stage Q9 corresponding to the major 6th are inputted. The AND circuit 281 is for detecting a seventh chord (seventh chord), and receives the output of the stage Q12 corresponding to the 1st and the output of the stage Q10 corresponding to the minor 7th, and further inputs the output of the stage Q12 corresponding to the 1st chord, and the output of the stage Q10 corresponding to the minor 7th. Signals obtained by inverting the outputs of Q5 and Q9 are input. In addition, when a chord is not detected, an AND circuit 28 is used to determine the rhizoid.
2 is provided, and the output of stage Q12 of the shift register 35 is input thereto. The output of an AND circuit 283 is further added to the AND circuits 280, 281, and 282. The AND circuit 283 has a finger code mode signal FC.
and the OR circuit 147 of the key scanning circuit 11 (Fig. 7)
A signal delayed by one key time by a delay flip-flop 284 is added to the signals BT10 to BT13 (FIG. 8) supplied from the circuit. Therefore, when in the fine guard code mode (FC is “1”), the block timing
AND only occurs between the timing of the second key time of BT10 (Fig. 8) and the timing of the first key time of BT14 (Fig. 8) (signal generation interval when signals BT10 to BT13 are delayed by one key time). Circuits 280-282 are enabled and chord detection is performed. When a chord is established, the condition of the AND circuit 280 or 281 is established at the note timing of the root note of the established chord, and "1" (chord establishment signal CH) is outputted via the OR circuit 285. In the chord detection by the AND circuits 280 and 281, note name B is the first rhizoid.
This is because the output of the delay flip-flop 284 enables chord detection from the second key time of the block timing BT10. As shown in Table 6 above, at the second key time of block timing BT10, stage Q12 of register 35 is activated.
The key data for pitch name B is coming. As shown in Table 6, at the next key time, A# becomes the rhizoid,
After that, the rhizoid changes in the order of high notes (A, G#...),
When note name C is made into a rhizome at the first key time of signal BT12 (see Figure 8), 12 note names B~
The detection of the formation of a chord with each of C as the rhizoid is completed. Therefore, the output CH of the OR circuit 285 has B
The chord formation detection results for which the rhizoid is the rhizoid (“1” when the chord is formed, “0” when it is not formed) are displayed first, and then the chord formation detection results appear in the order of the high notes, and at the end (signal
At the first key time of BT12), a chord formation detection result with C as the rhizoid appears. In the root note shift register 41, which will be described later, multiple root note data are stored.
When RTLD occurs, a single root note data RTLD is selected based on last arrival priority (bass priority), so by placing C last, C will be given top priority. . The output of OR circuit 285 is applied to AND circuit 286. Other inputs of the AND circuit 286 include block timing signals BT12.13 generated from the OR circuit 148 (FIG. 7) of the key scanning circuit 11.
A signal obtained by inverting the signal (FIG. 8) delayed by one key time by a delay flip-flop 290 and by an inverter 291 is added. The output of the inverter 291 becomes "0" for 12 key times (from the note timing of B to the note timing of C) from the second key time of block timing BT12 to the first key time of block timing BT14. Therefore, the chord formation signal CH whose rhizoids are the 12 note names B, A#, . Then, the chord establishment signal CH is blocked from the next key time (second key time of signal BT12).
That is, as shown in the FC of Z in FIG. 8, chord establishment detection is performed only during the 12 key times from the second key time of block timing BT10 to the first key time of BT12. The chord establishment signal CH which has passed through the AND circuit 286 between the second key time of block timing BT10 and the first key time of BT12 is applied to the AND circuit 287 and is stored in the delay flip-flop 289 via the OR circuit 288. . The output of the delay flip-flop 289 is connected to the AND circuit 29.
2 through the OR circuit 288 and is self-maintained. The other input of the AND circuit 292 is supplied with the SF/
The FC mode switching signal Δ and the output of the NAND circuit 293 are added. As shown in FIG. 5, the signal Δ is a signal that becomes "0" temporarily (4.5 ms+.alpha., that is, a time period of at least one scanning cycle) at the time of mode switching, and is normally "1". nand circuit 2
93, a signal indicating the scanning timing of the lowest key C2 given from the key scanning circuit 11 (FIG. 7).
CLT (Fig. 8) and the lower key range key-on signal LKO output from the OR circuit 270 are connected to the inverter 29.
The inverted signal in step 4 is input. If any key is pressed in the lower key range, the output of the inverter 294 is always "0" (LKO is "1") at the timing when the signal CLT is generated, and the NAND circuit 2
The condition 93 is not satisfied, and the output of the NAND circuit 293 is always "1". Therefore, once a chord is established, normally "1" continues to be stored in delay flip-flop 289. The chord establishment memory in the delay flip-flop 289 is cleared when all the keys in the lower key range are released (LKO becomes "0" and the output of the NAND circuit 293 becomes "0" when CLT occurs). , or when the finger code mode FC is switched to the single finger mode SF (Δ becomes "0"). The other input of the AND circuit 287 is an OR circuit 29.
5 outputs are added. If it is not the memory mode, the memory mode signal M is “0”, “1” is given from the inverter 296 to the OR circuit 295, and the chord establishment signal selected by the AND circuit 286 is output.
CH always passes through AND circuit 287. The output of this AND circuit 287 is outputted as root note data RTLD via an OR circuit 297, and is also outputted via an OR circuit 298 to a delay flip-flop 29.
9, and is further input to the AND circuit 300 of the minor chord memory 36 and the AND circuit 301 of the seventh chord memory 37. Therefore, the root note data
RTLD corresponds to the timing of the note name of the root note of the detected chord (from the note timing of B in the second key time of block timing BT10 to the note timing of C in the first key time of block timing BT12). becomes “1” at any timing of the key time). Also, the AND circuit 30
0 and 301 become operable at the timing of the root note name. The output of stage Q3 of the shift register 35 corresponding to minor 3rd ^3b is added to the other input of the AND circuit 300, and the output of stage Q3 of the shift register 35 corresponding to minor 7th ^7b is added to the other input of the AND circuit 301. The output of stage Q10 is added. When a major chord is established, the outputs of stages Q3 and Q10 are both "0" (minor 3rd and minor 7th do not exist) at the chord establishment timing, and the AND circuits 300, 301, OR circuit 302, 303, "0" is taken into delay flip-flops 304 and 305. If a minor chord is formed, the stage Q is set at the chord formation timing.
The output of 3 is “1” (minor third exists),
“1” is taken from the AND circuit 300 to the delay flip-flop 304 via the OR circuit 302. When a seventh chord is established, the output of stage Q10 is “1” (a minor seventh exists) at the chord formation timing, and the AND circuit 3
01 is taken into the delay flip-flop 305 via the OR circuit 303. For the minor seventh chord, delay flip-flop 304,
“1” is taken into both of 305. The “0” or “1” taken into the delay flip-flops 304 and 305 is sent to the AND circuit 306,
307. AND circuit 30
The output of the NOR circuit 308 is added to 6,307. AND circuits 287 and 3 are included in the NOR circuit 308.
09 output and lowest key scanning timing signal CLT
is added. In short, the output of the NOR circuit 308 is "1" except when new chord type data is taken in or when the signal CLT is generated.
AND circuits 306 and 307 are enabled to self-hold the data taken into delay flip-flops 304 and 305. Therefore, after taking in new chord type data, the signal CLT of the next scanning cycle is
The data is temporarily stored until the occurrence of the event. The outputs of the delay flip-flops 304 and 305 are connected to AND circuits 310 and 311 and OR circuits 312 and 3.
13 through delay flip-flops 314, 31
5. delay flip-flop 314,
Reference numeral 315 is for permanently storing the chord type data temporarily stored in the delay flip-flops 304 and 305, and the data is taken in on the condition that the chord has changed (that the chord has been established). AND circuit 28 generated when chord establishment is detected
7 is stored in delay flip-flop 299 via OR circuit 298. The memory of this delay flip-flop 299 is stored in an AND circuit 316.
is held through the scan cycle pulse
4.5M is inverted at the beginning of the scanning cycle (block timing BT as shown in Figure 8).
Cleared at the 1st key time of 0). "1" is stored in delay flip-flop 299, and AND circuit 317 becomes operational. AND circuit 317
is the output of the delay flip-flop 299, the signal BT14.15 supplied from the OR circuit 149 (FIG. 7) of the key scanning circuit 11, and the AND circuit 1.
A delay flip-flop 318 converts the C-note timing signal CNT supplied from 50 (FIG. 7) to 1
A signal delayed by the key time is added. Therefore, the signal
When there is a delay of one key time from the generation timing (Figure 8) of the signal CNT during the generation period of BT14.15 (Figure 8), that is, the block timing
At the second key time of BT14, "1" is output from the AND circuit 317. The AND circuits 310 and 311 become operational due to the output "1" of the AND circuit 317, and the delay flip-flops 304 and 311 become operational.
305 is transferred to a delay flip-flop 314,
315. The outputs of delay flip-flops 314 and 315 are self-held via AND circuits 320 and 321. AND circuits 320 and 321 have NOR circuit 3
19 outputs are added. When taking in new chord type data by the output “1” of the AND circuit 317 (or at the time of initial clearing), the NOR circuit 3
The output of 19 becomes "0" and the old memory is cleared. Therefore, the delay flip-flop 314,3
The data once stored in 15 is continuously stored until the chord changes. The output of the delay flip-flop 314 is output as minor chord data min, and the output of the delay flip-flop 315 is output as seventh chord data 7th. data
min and 7th are "0", "0" for a major chord, "1", "0" for a minor chord, "0", "1" for a seventh chord, "1" for a minor seventh chord, It is “1”. If the chord is not established, "1" is not stored in the delay flip-flop 289 that stores the establishment of the chord, and the AND circuit 287 does not generate the signal CH indicating the timing of the root note of the established chord. The output of the delay flip-flop 289 is inverted by an inverter 323 to generate a chord failure signal NCHD.
The signal is input to the AND circuit 309 and the OR circuit 295 as follows. The other input of the AND circuit 309 is a signal obtained by delaying the signal BT12.13 (FIG. 8) supplied from the OR circuit 148 (FIG. 7) of the key scanning circuit 11 by one key time in the delay flip-flop 324, and the AND circuit 282. The output of is input. As mentioned above, the establishment of a chord is detected during the 12 key times from the 2nd key time of block timing BT10 to the 1st key time of block timing BT12 (see Figure 8), so the next 12 keys are detected. In other words, from the second key time of block timing BT12 to the first key time of block timing BT14 when the output of the delay flip-flop 324 becomes "1", the chord formation detection result is reliably stored in the delay flip-flop 289. There is. When a chord is established, the chord established signal NCHD is "0" and the AND circuit 309 does not operate.
However, if the chord is not established, the chord failure signal NCHD is “1” and the block timing is
Key data of B to C output from the AND circuit 282 between the second key time of BT12 (note timing of B) and the first key time of BT14 (note timing of C) (output of stage Q12 of shift register 35) ) are all AND circuits 309
pass through. The output of the AND circuit 309 passes through the OR circuit 297 and is output as root note data RTLD. Therefore, when a chord is not established, the root note data RTLD becomes "1" at the note timing of all keys pressed in the lower key range. In this case, the data (“1”) of the pressed keys appear in the root note data RTLD in the order of high notes, with B being the highest note, and the data of C appears last. Since the root note shift register 41, which will be described later, selects root note data RTLD with priority given to the last note (bass note given priority), when a chord is not established, the lowest note of the keys pressed in the lower key area is regarded as the root note. Also, the output of the AND circuit 309 is the output of the OR circuit 29.
8 and is stored in delay flip-flop 299 and applied to NOR circuit 308. Therefore, when the chord is not established, both the delay flip-flops 304 and 305 are cleared by the output "0" of the NOR circuit 308, and the contents "0" and "0" indicating the major chord are cleared.
becomes. Also, by storing "1" in the delay flip-flop 299, the outputs "0" and "0" of the delay flip-flops 304 and 305 are changed to the outputs of the delay flip-flops 314 and
15 and stored. In this way, if the chord is not established, both data min and 7th become "0", indicating a major chord. When not in the memory mode (M is "0"), the output of the OR circuit 295 is always "1", and a signal indicating the root note timing is output from the AND circuit 287 every time a chord is established. However, in the memory mode, the signal M becomes "1" and the inverter 2
The signal applied from 96 to OR circuit 295 becomes "0". The other inputs of the OR circuit 295 are applied with a lower key range any key-on signal LANKO and a chord failure signal NCHD. Therefore, in memory mode, the lower key area any key-on signal
The AND circuit 287 outputs data indicating the root note of the chord that was established when LANKO or the chord failure signal NCHD was generated. In particular, a chord is usually detected when the signal LANKO occurs, that is, when a new key is pressed in the lower key area (the chord failure signal CH is passed). The lower key area any key-on signal LANKO is
The signal is supplied from a lower key area new key-on detection circuit 38 whose details are shown in FIG. The lower key area key data LKKD output from the AND circuit 268 in FIG. 12 is the lower key area new key-on detection circuit 3 shown in FIG.
8. In FIG. 13, lower key range key data LKKD is applied to a shift register 326 via an OR circuit 325 and an AND circuit 3.
Added to 27. Shift register 326 has 19 stages/1 bit and is driven by key scan clock pulse φ _AB . shift register 3
The output of 26 is sent from the AND circuit 328 to the OR circuit 32.
5 and is applied to delay flip-flop 329. delay flip-flop 3
The output of 29 is inverted by an inverter 330 and then applied to an AND circuit 327. Initial clear signal
A signal obtained by inverting the IC or lower key area scanning timing signal LK by a NOR circuit 331 is applied to another input of the AND circuit 328. The number of stages of the shift register 326, 19, corresponds to the number of keys in the lower key area F#3 to C2. 19 keys F#3~ that occurred sequentially at the lower key area scanning timing
The key data LKKD of C2 is sequentially taken into the shift register 326 via the OR circuit 325. At this time, the output of the NOR circuit 331 becomes "0" due to the signal LK being "1", and the old stored data in the register 326 is cleared. When the lower key area scanning timing ends, the signal LK becomes “0” and the NOR circuit 3
31 enables the AND circuit 328 to operate, and the lower key area key data that has just been taken into the register 326 is stored and held. This memory is held until the signal LK is generated in the next scanning cycle. Therefore, when new key data LKKD is supplied in the next scanning cycle, the final stage of the shift register 326 outputs key data indicating the previous lower key area scanning result. One scan cycle consists of 16 block timings
It consists of BT0 to BT15, and one block timing consists of 6 key times, so one scanning cycle is 96
Consists of key times. Therefore, if the key data obtained in the previous scan cycle is delayed by 96 key times, it will match the key scan timing in the current scan cycle, but since the shift register 326 has 19 stages, the delay time when cycling through 5 times will match the key scan timing in the current scan cycle. is 95 key hours, which is one key hour short of 96 key hours. Therefore, the output of the shift register 326 is input to the delay flip-flop 329 and further delayed by one key time to match the key scanning timing. The output of delay flip-flop 329 is inverted by inverter 330. Therefore, when a key that was off in the previous scan cycle (the output of the inverter 330 is "1") is turned on in the current scan (LKKD is "1"), a new key is pressed in the lower key area. Then, the output of the AND circuit 327 becomes "1". The output "1" of the AND circuit 327 is applied to the delay flip-flop 333 via the OR circuit 332, and by the cancel signal (FIG. 8) applied to the self-holding AND circuit 334, the lower key area scan timing of the next scan cycle is determined. It is retained until it is cleared immediately before. The signal stored in the delay flip-flop 333 is outputted from an AND circuit 334 via an OR circuit 332 as a lower key range any key-on signal LANKO. this signal
When LANKO detects that a new key has been pressed in the lower key area, the scan timing of that key (block timing BT7 to BT9 and BT1
0's 1st key time scan timing)
Block timing BT of next scan cycle from
It remains "1" until 4 (just before it becomes "0"). Therefore, when any key is newly pressed in the lower key range, the signal LANKO is reliably set to "1" between BT10 and BT15, which includes the block timing for detecting a chord. This lower key area any key-on signal LANKO
is supplied to the chord detection control circuit 30 in FIG.
It is added to the AND circuit 287 via the OR circuit 295. Therefore, in the memory mode (M is "1"), the chord establishment signal CH generated when a new key is pressed in the lower key area is output as a valid chord detection result. Even if a chord is formed when a key is released in the lower key range, the chord formation signal CH at that time is blocked by the AND circuit 287 and becomes invalid. This is because in the memory mode, even if the key is actually released, the sound is processed as if the key continues to be pressed, so chord detection is also made so that it does not respond to the key release. By the way, in the case of memory mode, if you press an extra key by mistake and a chord is not formed, even if you immediately release only the extra key and make a chord, the lower key range any key-on signal will not be generated. LANKO
is not generated, and the AND circuit 287 cannot be enabled by this signal LANKO. Chord formation signal CH due to partial key release in the above case
In order to allow the chord to be detected by passing the chord, the chord failure signal NCHD is applied to the AND circuit 287 via the OR circuit 295. In other words, if the chord has not been formed yet (NCHD
is “1”), lower key range any key-on signal
Even if LANKO does not occur, AND circuit 28
7 becomes operational, and a chord establishment signal CH is outputted via AND circuits 286 and 287. In the chord detection control circuit 30 shown in FIG.
1 (Fig. 1) corresponds to all the parts explained so far. Next, the lower key area key-on memory 3 shown in FIG.
9 will be explained in detail. Lower key range key-on signal LKO output from the OR circuit 270 in FIG.
is supplied to OR circuit 335 in FIG. 14 and stored in delay flip-flop 336. The output of delay flip-flop 336 is self-held via AND circuit 337 or 338 and OR circuit 335. The output of the OR circuit 335 is supplied to other circuits as the lower key area any key-on signal LKAKO. In the memory mode, the memory mode signal M applied to the AND circuit 337 becomes "1", and the delay flip-flop 336 is always in a self-holding state.
Therefore, once a key is pressed in the lower key area, the signal LKO is generated.
When this occurs, the lower key area any key-on signal LKAKO is kept at "1" thereafter. If not in memory mode, AND circuit 338
The signal LKAKO is maintained by the function of . The output of the NOR circuit 339 is added to the AND circuit 338. A signal CLT indicating the scanning timing of the lowest key C2
(See FIG. 8) is added to the NOR circuit 339, and the AND circuit 339
38 becomes inoperable and enters a self-holding clear state. On the other hand, the lower key area key-on signal LKO applied to the OR circuit 335 is "1" from the scanning timing to just before the block timing BT5 of the next scanning cycle if any key is pressed in the lower key area.
is maintained (by the action of the AND circuit 272 in FIG.
35 to a delay flip-flop 336.
However, when no key is pressed in the lower key range, the signal LKO becomes "0" at the lowest key scanning timing when the AND circuit 338 becomes inactive, and the memory of the delay flip-flop 336 is cleared. Therefore,
As long as some key is pressed in the lower key range, the lower key range any key-on signal LKAKO remains “1”.
and becomes “0” when no keys are pressed in the lower key range.
becomes. In addition, if the memory mode is not set, the delay flip-flop 34 is also activated when the autorhythm stops.
The signal "1" from 0 clears the self-holding of the signal LKAKO. The rhythm run signal RUN from the autorhythm device 45 (FIG. 1) is inverted by an inverter 341 and applied to an AND circuit 342, and is also delayed by one key time by a delay flip-flop 343 and applied to the AND circuit 342. When the autorhythm stops, the rhythm run signal RUN falls to "0". At this time, the previous signal RUN
The output of the delay flip-flop 343 is "1", which indicates the state of "0", and the output of the inverter 341 which inverts the signal RUN, which has become "0", is "1", and the AND circuit 342 outputs a pulse "1" for one key time. Output. The output "1" of the AND circuit 342 is delayed by one key time in the delay flip-flop 340, and then applied to the NOR circuit 339 to clear the signal LKAKO. Base note key data formation and pronunciation assignment Next, the formation of base note key data and pronunciation assignment in the case of the Finguard chord mode will be explained. Bass sound key data formation circuit 42
automatic base code processing circuit 40 (FIG. 1) including
A detailed example is shown in FIG. OR circuit 297 (first
The root note data RTLD output from Figure 2) is the 15th
The signal is input to the root shift register 41 via the OR circuit 344 shown in the figure. The root shift register 41 is 12
The stage/1 bit is driven by the key scan clock pulse φ _AB . Therefore, the root note data RTLD taken into the shift register 41 from the OR circuit 344 is sequentially delayed (shifted) by one key time, and the data RTLD′ delayed by 12 key times is output from the 12th stage Q12. Ru. 1st stage Q1 to 11th stage Q of shift register 41
NOR circuit 345 that inputs all outputs up to 11
and the output of this NOR circuit 345 and the 12th stage Q
AND circuit 34 which inputs the output RTLD' of 12
6 constitutes a last arrival priority (bass priority) circuit. As mentioned above, the root note data RTLD indicates the root note by the presence or absence of a pulse at 12 time-divided note timings, starting with the note timing of B and continuing in treble order up to the lowest note C. This is divided and multiplexed data (same as key data KD). Therefore, in the root note data RTLD, it arrives at a later timing (later arrival).
The pulse indicates a more bass timbre. By preferentially selecting only one root note data RTLD that arrived the latest by a last arrival priority (bass priority) circuit consisting of a NOR circuit 345 and an AND circuit 346 and storing it in the shift register 41, the data is stored in the shift register 41. is stored with data indicating a single root note selected with bass priority. All of the root note data RTLD are initially input to the shift register 41, and data RTLD' which is delayed by 12 key times is output from the 12th stage Q12. The note timing of this delayed data RTLD' is completely synchronized with the note timing of data RTLD (that is, the note timing in key scanning). The AND circuit 346 and the NOR circuit 345 control whether to return the delayed root note data RTLD' to the shift register 41 via the OR circuit 344 or to prevent it, by giving priority to the last arriving (low tone). Root note data (“1”) that arrived later (lower tone) than data RTLD′ output from the 12th stage Q12 of the shift register 41
If there is, one of the outputs of stages Q1 to Q11 (corresponding to all the remaining 11 note names except the note name of RTLD') is "1", and the output of the NOR circuit 345 is "1". 0” and the data
RTLD' is blocked by an AND circuit 346. If the data RTLD' output from the 12th stage Q12 is the latest arrival (low tone), the data "1" that appeared before it (on the high tone side) is blocked by the AND circuit 346, so the stages Q1~ All the outputs of Q11 are “0”, and the NOR circuit 345
If the output is “1”, the root note data of this lowest note
RTLD' passes through the AND circuit 346 and is returned to the shift register 41 via the OR circuit 344.
When there is only one root note data stored in the shift register 41, from then on, that only root note data is circulated and stored and held. In this way, when "1" occurs at a plurality of note timings as the root note data RTLD, only the lowest note data "1" among them is selected and stored in the shift register 41. Of course, as is the case in many cases, if "1" is generated from the beginning with only a single note timing as the root note data RTLD, that data "1" is directly transferred to register 4.
1 is stored. Note that the NOR circuit 345 and the AND circuit 346 are not simple bass priority circuits, but function only as later arrival priority circuits. With this last arrival priority function, if the chord (root note) changes, old root note data will be deleted.
Clear RTLD′. That is, when new root note data RTLD arrives (even if it is at the note timing of B, which is considered to be the highest note in the priority judgment), the output of the register 41 that has received this new root note data RTLD is Due to Q1 to Q11, the output of the NOR circuit 345 becomes "0", and the old root note data RTLD' stored up to that point is cleared. An example of selecting single root note data by giving priority to the last arrival will be explained separately for cases in which a chord is established and cases in which a chord is not established. If a chord is formed, as mentioned above, AND circuit 2
86 (Figure 12), the root note is played only during the 12 key times from the second key time of block timing BT10 (note timing of B) to the first key time of block timing BT12 (note timing of C). Data RTLD occurs. 1st
In the CH column of FIG. 6, an example of root note data RTLD when a chord is established (CH is "1") and data RTLD' delayed from the root note data RTLD' are shown. Note that the note timing column in Figure 16 shows the block timing BT.
Block timing from 10 to next scan cycle
The tones corresponding to each key time up to BT1 are shown. In CH in Figure 16, two tones are C#,
An example in which root note data RTLD is generated in response to C is shown. For example, this means C, C in the lower key range.
This occurs when the four keys #, G, and G# are pressed. In the shift register 35 of FIG.
When the C# data “1” arrives at stage 12, the C# data “1” is in the perfect fifth stage Q7, and the C and G data “1” are in the stage Q11.
and Q6 (see Table 6 above), the AND circuit 280 detects that the C# major chord is established, and the root note data RTLD is generated at the note timing of C#. When data "1" of C arrives at stage Q12 of the next shift register 35, G enters stage Q7, C# enters stage Q1, and G# enters Q8 (see Table 6), and the AND circuit 280 enters C major. It is detected that a chord has been formed. When data RTLD', which is obtained by delaying the root note data RTLD of C# by 12 key times, is output from the 12th stage Q12 of the shift register 41 in FIG. 15 at note timing C# of block timing BT13, the note timing of block timing BT12 C root note data imported when C
Data "1" delayed by 11 key times from RTLD is output from stage Q11. Therefore, the root note data RTLD' of C# is the later (lower tone) C
Due to the existence of root note data RTLD, AND circuit 3
Blocked at 46. In this way, only the root note data of a single C is stored in the shift register 41, and after block timing BT14, the stored root note data
RTLD' becomes "1" only at the note timing of C. If the chord does not hold, as mentioned above, the AND circuit 309 (Fig. 12) changes the block timing from the second key time of BT12 (note timing of B) to the first key time of BT14 (note timing of C). Root note data RTLD is generated only during the 12 key times up to ). The column of FIG. 16 shows an example in which "1" is generated at the note timings of B, D#, and D as root note data RTLD when a chord is not established (CH is "0"). If the three keys B, D#, and D are pressed in the lower keyboard area,
The chord is not formed, and as shown in Figure 16,
Root note data for all note timings of pressed keys
RTLD occurs. Data RTLD', which is obtained by delaying the B root note data RTLD by 12 key times, is generated at the B note timing of block timing BT14, but at stages Q3 and Q4 of the shift register 41.
Since the data “1” of D and D# is output from the
will be blocked. Also, the root note data RTLD of D#
Data RTLD' delayed by 12 key times is generated at the note timing of D# of block timing BT15, but at stage Q1 of the shift register 41.
Since the data "1" from 1 to D is output, this data RTLD' of D# is also blocked by the AND circuit 346. At note timing D of block timing BT15, when data RTLD', which is delayed by 12 key times from the root note data RTLD of D, is generated, the data of B and D# generated before that is generated.
Since RTLD' is all blocked, the outputs of stages Q1 to Q11 of the shift register 41 are all "0", and the data RTLD' at the note timing of D is stored and held. In this way, when a chord is not established, the lowest note among the pressed keys is selected as the root note. The important function of the root note shift register 41 is to sequentially shift (delay) the single root note data RTLD' for each key time. This is to form note timing data of notes separated by a predetermined number of degrees. By delaying the root note data RTLD' input from the AND circuit 346 via the OR circuit 344 by one key time at each stage Q1 to Q12 of the shift register 41, the note timing of the root note is sequentially shifted to the bass side. "1" is output from each stage Q1 to Q12 at the note timing. Therefore, the output "1" of stage Q1 delayed by one key time corresponds to the note timing of the note one semitone below the root note, that is, the major seventh note, and the output "1" of stage Q2 delayed by two key times corresponds to the note timing of the note one semitone below the root note, that is, the major seventh note. 1” corresponds to the note timing of the note two semitones below the root note, i.e. the minor seventh ^7b . Similarly below,
Stages Q3, Q4, Q of shift register 41
5, Q6, Q7, Q8, Q9, Q10, Q11 output "1" is major 6th 6, minor 6th 6 ^b , perfect 5th 5, diminished 5th 5 ^b , perfect 4th 4, major 3rd 3, corresponding to the note timings of minor 3rd ^3b , major 2nd 2, and minor 2nd ^2b , respectively. Then, the output "1" of the stage Q12, that is, the OR circuit 344, corresponds to the same tone as the root note, that is, 1 degree. For example, when the root note data RTLD' is generated at the note timing of C, the timing at which the output of each stage Q1 to Q11 of the shift register 41 becomes "1" is as shown in FIG. ，
This is the timing of A, G#, . . . C#. These pitch names correspond to major 7th 7, minor 7th 7 ^b ... minor 2nd 2 ^b , when C is 1 degree. Also, root note data
When RTLD' occurs at the note timing of D, each stage Q1 to Q1 of the shift register 41
As shown in FIG. 16, the timing at which 1 becomes "1" is the timing of C#, C, B, A#...D#. These tones correspond to major 7th 7th, minor 7th ^7b ...minor 2nd ^2b, respectively, when D is 1 degree. A predetermined stage Q2 of the root shift register 41,
Q3,,Q5,Q8,Q9,Q12 (OR circuit 3
44) is output from the bass tone key data forming circuit 4.
The signal is input to the logic circuit 347 of No. 2. logic circuit 34
7 selects the stage output of the register 41 corresponding to the number of tones indicated by the bass pattern data BassPT, based on the bass pattern data BassPT supplied from the autorhythm device 45 (FIG. 1). It is multiplexed and output on one output line 348. Of course, while certain bass pattern data BassPT is occurring, only data corresponding to one note timing is sent to the output line 34.
8 is not output, but another base pattern data
When changing to BassPT, data "1" corresponding to another note timing is output to the output line 348. In that sense, the bass tone key data KP obtained on line 348 is
This is time-division multiplexed data with the same quality as the key data KD obtained from Figure). The one-at-a-time note timing data output from the OR circuit 344 (stage Q12 of the shift register 41) is input to the AND circuit 349. Note timing data of minor 7th ^7b output from stage Q2 of shift register 41 is input to AND circuit 350. The note timing data of major 6th 6 output from stage Q3 is sent to AND circuit 351, and the note timing data of perfect 5th 5 output from stage Q5 is sent to AND circuit 3.
52, respectively. Also, stage Q8,
The note timing data of major third 3 and minor third 3 ^b output from Q9 are sent to AND circuits 355 and 35.
6 to AND circuits 353 and 354, respectively. AND circuits 355 and 356 are for switching between a major third and a minor third. When the minor chord data min supplied from the delay flip-flop ³¹⁴ in FIG. At this time, the AND circuit 355 becomes inoperable and the output of the major third 3 is blocked. When the minor chord data min is “0”, the major chord data is played through the AND circuit 355.
The output of stage Q8 corresponding to degree 3 is selected and applied to AND circuit 353, and the output of stage Q9 corresponding to minor third ^3b is blocked by AND circuit 356. Therefore, the AND circuits 353 and 354 are supplied with either the note timing data of the major third 3 or the minor third 3 ^b depending on whether it is a minor chord or not. The bass pattern data BassPT is generated at the timing when a bass note is to be generated, and indicates the pitch (distance from the root note) of the bass note to be generated at that time, based on the contents of a 3-bit code. AND circuits 357-362 are for decoding data BassPT encoded into 3 bits. The output of the AND circuit 357 indicating the bass tone of 8th degree (root note one octave higher) and the output of the AND circuit 358 indicating the bass tone of 1st degree are applied to the AND circuit 349 via the OR circuit 363. The output of AND circuit 359 indicating the minor seventh bass note is applied to AND circuit 350 . The output of the AND circuit 360 indicating the bass tone of the major 6th is applied to the AND circuit 351. The output of AND circuit 361 indicating a perfect fifth bass note is applied to AND circuit 352. 3
The output of the AND circuit 362 indicating the bass tone of the degree is applied to AND circuits 353 and 354. As mentioned above, only the note timing data of either the major third or the minor third is applied to the AND circuits 353 and 354, so the output of the AND circuit 362 indicating the third determines whether the major third or the minor third. Only one of the three data is selected. When the base pattern data BassPT is generated, any one of the AND circuits 357 to 362
Output "1" occurs from only one. Therefore, AND circuits 349-354 select the note timing data from the only stage of shift register 41 that corresponds to the frequency indicated by base pattern data BassPT. AND circuit 3
Outputs 49 to 354 are multiplexed by an OR circuit 364 and then applied to an AND circuit 365. Other inputs of the AND circuit 365 are a lower key area any key on signal LKAKO supplied from the lower key area key on memory 39 shown in FIG. signal BT
0.1 (Figure 8) is added. The output of the AND circuit 365 is output via the multiplexing line 348 as bass tone key data KP. The reason why the signal BT0.1 is input to the AND circuit 365 is that the bass tone key data KP is generated only during the 12 key time periods of block timings BT0 and BT1 when the signal BT0.1 becomes "1", and the bass tone key data KP is generated during this period. This is to perform pronunciation assignment processing. The reason why the lower key range any key-on signal LKAKO is input to the AND circuit 365 is to generate automatic bass sound by generating bass sound key data KP only when some key is pressed in the lower key range. As shown in Fig. 14, in the memory mode (M is "1"), the lower key range any key-on signal LKAKO continues to be generated even after the key is released, so the bass tone key data KP is not changed after the key is released. are also occurring more and more. Therefore, in the memory mode, not only the notes (chords) in the lower key range but also the bass note continue to be generated even after the key is released. All bits of the base pattern data BassPT are input to the OR circuit 366, and the output of this OR circuit 366 is the base timing signal.
Output as BT. This base timing signal BT is some kind of base pattern data BassPT.
It becomes "1" while the bass tone is being generated, that is, when the bass tone should be generated. For example, suppose that the root note stored in the root note shift register 41 is C, and the base pattern data
If BassPT specifies the 5th, then the 16th
As shown in KP in the figure, the base tone key data KP is set at the G note timing of block timing BT0.
becomes “1”. In this case, the AND circuit 352 is enabled and the output of the stage Q5 of the shift register 41 is selectively output as the bass note key data KP. Since "1" is output from stage Q5 5 key times after "1" is input to the register 41 at the note timing of the root note C, "1" is output from the stage Q5 5 key times after the note timing of C (that is, the note timing of C). The key data KP is generated at the note timing of the note (a fifth above). The root note data RTLD supplied from the chord detection control circuit 30 (FIG. 12) is sent to the root note change detection circuit 367.
is also entered. In the root note change detection circuit 367, an AND circuit 370 is a circuit that detects that the root note has been changed. delay flip-flop 36
8 is for storing the output “1” of the AND circuit 370 (that is, the root note has been changed);
The memory is held via an AND circuit 369 and an OR circuit 371. The AND circuit 370 contains new root note data RTLD and the root note shift register 41.
Old root note data output from 12 stage Q12
A signal obtained by inverting RTLD′ is input. Therefore, if the root name detected this time is different from the root name detected and memorized last time, new root note data will be used.
At the note timing when RTLD is “1”, the old root note data RTLD′ is “0” (because it is not the note timing of the old root note), and the AND circuit 3
Condition 70 is satisfied, and the output "1" of AND circuit 370 is taken into delay flip-flop 368 via OR circuit 371. By the way, as mentioned above, root note data RTLD may occur at multiple note timings,
In that case, the root note data RTLD that arrived first is false root note data that is not stored in the root note shift register 41. However, the condition of the AND circuit 370 is satisfied even for the false root note data RTLD, and "1" is taken into the delay flip-flop 368. For this reason, the root note data RTLD is
AND circuit 36 for self-holding the signal inverted in step 2
I am trying to add it to 7. Therefore, the flip-flop 368 is delayed by the false root data RTLD.
Even if “1” is taken into the NOR circuit 372 by the true root note data RTLD that arrives after that,
The output of the AND circuit 369 is set to "0" to disable the AND circuit 369, and the false root note change record is cleared. Since no root data RTLD occurs after the true (that is, the last arriving) root data RTLD, the output of the AND circuit 370 regarding the true root data RTLD is stored and held in the delay flip-flop 368. A scan cycle pulse of 4.5M is applied to the other input of the NOR circuit 372;
At the first note timing of block timing BT0 when BT0 occurs, the memory of delay flip-flop 368 is cleared. Therefore, when the root note is changed, the pulse is changed from block timing BT10 to BT13 at which the root note data RTLD is generated.
The output of the OR circuit 371 is "1" until block timing BT15 immediately before the occurrence of 4.5M. The output of the OR circuit 371 is applied to an AND circuit 373. The other inputs of the AND circuit 373 are the C note timing signal CNT and the signal BT14.15 (first
8) is supplied from the key scanning circuit 11 (FIG. 7). Therefore, at the note timing of C at block timing BT14, the AND circuit 3
73 becomes operational, conducts the root note change signal (“1” when changing) from the OR circuit 371, and outputs the delay flip-flop 37 via the OR circuit 374.
Store in 5. Block timing BT14 C
The note timing is the last valid timing of the root note data RTLD that occurs when a chord is not established, and at this time, it is definitely known whether or not the root note has been changed. The output of delay flip-flop 375 is self-held via AND circuit 376 and OR circuit 374. The output of the OR circuit 374 becomes "1" continuously when the root note change is memorized, and the output of the AND circuit 374 becomes "1" continuously.
Added to 7. The other input of the AND circuit 377 is the base timing signal from the OR circuit 366.
BT joins. The output of the AND circuit 377 passes through the OR circuit 363 and is applied to the AND circuit 349 as a signal instructing the 1st (root note) bass tone. Also, the output of the OR circuit 374 is output from the inverter 3
AND circuits 359, 360, 361 for decoding base pattern data of 7 degrees, 6 degrees, 5 degrees, or 3 degrees, which is inverted at 78;
362 respectively. Therefore, when the root note is changed, at the timing of the bass pattern data BassPT that is generated immediately after that, the AND circuit 377 outputs " while the data BassPT is being generated (signal BT is "1"). 1” is output, and the bass sound key data is output at one note timing via the AND circuit 349.
Generate KP. At this time, even if the base pattern data BassPT specifies an interval other than 1st or 8th, the output "0" of the inverter 378 prevents the data BassPT from being decoded and output. The base timing signal BT output from the OR circuit 366 is delayed by one key time by a delay flip-flop 379 and input to a NAND circuit 381, and is also inverted by an inverter 380 and input to the NAND circuit 381. base timing signal
When BT falls to "0", that is, when one bass sound generation timing ends, the condition of the NAND circuit 381 is satisfied only during one key time, and the output of the NAND circuit 381 is held during that one key time. becomes “0”. The AND circuit 376 becomes inoperable due to the output "0" of this NAND circuit 381,
The root change storage signal ("1") in delay flip-flop 375 is cleared. In this way, when the root note is changed, by forcibly pronouncing the root note at the bass note generation timing immediately after the change,
I try to give the impression that the root note has changed (the chord has changed). The rhythm stop signal RSTP or initial clear signal IC supplied from the autorhythm device 45 (FIG. 1) is input to the OR circuit 374 via the OR circuit 382, and is stored in the delay flip-flop 375 in the same way as the root note change signal described above. It is becoming more and more common. The rhythm stop signal RSTP is generated when all the rhythm selection switches are turned off or when the rhythm run signal RUN becomes "0", that is, the pattern data is output from the pattern generation circuit 46 (FIG. 1) in the autorhythm device 45.
When the state is such that BassPT cannot be generated (rhythm stop state), it rises to "1". Therefore, when the rhythm stop state occurs, the signal RSTP becomes "1".
is stored in the delay flip-flop 375,
The output of the OR circuit 374 becomes "1". When in rhythm stop state, base pattern data
Since BassPT is not generated, base timing signal BT is also not generated, and the condition of AND circuit 377 is not satisfied. However, when the rhythm stop state is released and the first bass pattern data BassPT is generated, the condition of the AND circuit 377 is satisfied. Therefore, at the start of a rhythm performance, one bass note is forcibly produced as the first bass note, similar to when changing the root note described above. Bass note octave chord B1', B2', B
3' is formed by an octave code forming circuit 383. The octave chord forming circuit 383 is configured to meet the request to set the bass range as follows. Bass range setting request (1) The root note (1st degree) is in the range of C2, C#2, D2...B2. (2) The subordinate tone of the 8th (root note one octave higher) is C
3, C#3, D3...Set as a range of B3. (3) As a general rule, subordinate notes other than the 8th (3rd, 5th, 6th, or 7th) are in the same range as the root note, from C2 to
Set it to B2, but if the tone is lower than the root note, set it to 1.
The range is C3 to B3 an octave higher. By satisfying the requirement (3) above, all subordinate tones will be generated higher than the root tone.
"Walking base" becomes possible. By the way, if C (i.e., C2 note) is the root note, there is no subordinate note that can be lower than the root note (because C2 is the lowest note), or as shown in Table 5 above. In this system, C2 (or C3) octave chord B1~
The value of B3 is the value of other C#2~B2 (or C#3~
B3) is different from the values of the octave codes B1 to B3. Therefore, the processing to satisfy the above requirements (1) to (3) cannot be performed in common for all root note names C to B. Therefore, the octave codes B1 to B3 are determined in different manners when the root note is C and when the root note is C# to B, as shown in Table 7 below. When determining (forming) octave codes B1 to B3, any one of events a to g in Table 7 is applied.

[Table] In Table 7, the columns BQ1 and BQ2 show the states of the signals BQ1 and BQ2 generated from the OR circuit 384 and AND circuit 385 in the octave code forming circuit 383. Notes C2 and C3 shown in the range column or ranges C#2 to B2, etc.
The range of bass sounds that may be generated in each event a to g is shown. For example, in event a where the root note is C, it means that the sound C2 is generated as the root note. Furthermore, in event d where the root note is other than C, it means that sounds C#2 to B2 are generated as the root note. In order to satisfy the above requirements (1) to (3), it is necessary to define the range as shown in Table 7. In order to obtain that range, as is clear from the octave code table in Table 5, the octave codes B1 to B in Table 7 must be
As shown in column 3, octave codes B1 to B3
It is only necessary to determine the value of . In the octave code forming circuit 383, an exclusive OR circuit 386, an AND circuit 387, an inverter 38
8,389. In addition, in cases other than the root C in Table 7, when it comes to ``conjoint notes higher than the root note'' or ``subordinate notes lower than the root note'', note name C should be judged as the highest note and C# the lowest note. I have to. The bass sound that is about to be generated (7th, 6th, 5th
Whether the subordinate note of degree or third) is higher or lower than the root note is determined by the note timing of the root note data RTLD' output from the root note shift register 41 and the note timing of the base note key data KP (the subordinate note to be generated). The judgment is made based on the relationship between the timing of the note occurrence and the note timing of the note timing. The bass sound key data KP of line 348 is AND circuit 3
90, and further the output of this AND circuit 390 is applied to AND circuits 391, 392, 393 to form octave codes B1, B.
2, B3 to the corresponding AND circuits 391, 392, 39 at the note timing of this base tone key data KP.
3 to generate bass tone octave chords B1', B2', and B3'. Octave codes B1', B2', B are generated at the timing of generation of this bass note key data KP.
Extracting 3' helps in dynamically (based on timing) determining the pitch of the follower tone. Note that the AND circuit 390 includes the timing signal generation circuit 20.
The bass channel timing signal PchT (see Fig. 6) supplied from the AND circuit 118 (Fig. 2) is also added, but this is used for bass sound assignment processing, that is, the channel timing for bass sound assignment. Octave chord B1'~B
This is to ensure that 3' is output. Delay flip-flop 394, AND circuit 39
5,396, and an OR circuit 397 is a circuit that memorizes raising the pitch by one octave, and outputs "1" at the note timing of the subordinate note (or eighth note) that should be raised by one octave. AND circuit 3
A signal obtained by inverting the scanning cycle pulse 4.5M is input to 95 and 396. Root note data RTLD' output from the root note shift register 41 is applied to the other input of the AND circuit 396. The scan cycle pulse 4.5M becomes "1" at the scan timing of the highest key C7, that is, at the note timing of C at block timing BT0. Therefore, the C root note data RTLD' generated at block timing BT0 is blocked by the AND circuit 396,
It is not stored in delay flip-flop 394.
Furthermore, since the pulse 4.5M is "0" at the note timing of C in block timing BT2, the root note data RTLD' of C is stored in the delay flip-flop 394 at that time, but the octave codes B1' to B3' are Since it is output only at block timings BT0 and BT1 based on the base tone key data KP, the state of the delay flip-flop 394 from block timing BT2 to BT15 is completely meaningless. Root note data
When RTLD′ becomes “1” at a note timing other than C, the scan cycle pulse 4.5M is “0”
Therefore, "1" is taken in via the AND circuit 396 at the root note timing. The fetched "1" is thereafter self-held via the delay flip-flop 394 and the AND circuit 395. Pulse that occurs at the beginning of the next scan cycle
4.5M disables the AND circuit 395 and clears the self-holding state. Therefore, the block timing for generating octave codes B1' to B3'
Looking between BT0 and BT1, we can see that before the root note note timing (scanning is done in the order of high notes, so note timings higher than the root note (delayed flip-flop 3)
The output of 94 is "0", indicating that it is not necessary to raise the pitch by one octave. However, after the root note timing (note timing lower than the root note)
Then the output of the delay flip-flop 394 is “1”
, indicating a rise of one octave. Note that the output B8 of the AND circuit 357 indicating that the base pattern data BassPT is 8 degrees is sent to the delay flip-flop 394 via the OR circuit 397.
It is becoming more and more remembered. Therefore, when an 8th bass tone is to be generated, the output of delay flip-flop 394 is always "1", indicating that the bass tone should be raised by one octave. Next, the operation of the octave code forming circuit 383 will be explained for each event (a to g) shown in Table 7 above. When the root note is C, the root note data RTLD' becomes "1" at the note timing of C. Therefore, as described above, "1" is not stored in the delay flip-flop 394 at block timings BT0 and BT1. In the case of event a, block timing BT
At the note timing of the root note at 0, that is, C (see Fig. 16), the conditions of the AND circuit 385 to which the root note data RTLD' and the C note timing signal CNT (Fig. 8) are input are satisfied, and its output signal
BQ2 becomes “1”. At this time, the AND circuits 395 and 396 become inoperable due to the pulse 4.5M, so the signal given from the OR circuit 397 to the AND circuit 398 is "0". Furthermore, the output of the AND circuit 399 to which the signal "0" obtained by inverting the C note timing signal CNT is input is also "0".
The output signal BQ1 of the OR circuit 384 inputting the outputs of the AND circuits 398 and 399 is also "0".
Therefore, at the note timing of the root note C, the signal BQ1 becomes "0" and the signal BQ2 becomes "1". both signals
The output of the exclusive OR circuit 386 that inputs BQ1 and BQ2 (bit B1 of the octave code) is "1",
The output (bit B2 of the octave code) of the AND circuit 387, which receives signals obtained by inverting the signals BQ1 and BQ2 by the inverter 388, is "0".
(bit B of the octave code)
3) becomes “1”. Therefore, “1”, “0”,
Octave code B3, B2, with a value of “1”
B1 is input to AND circuits 391-393.
In the case of event a, the base note key data KP becomes "1" at the note timing of the root note C, so the above-mentioned "1" formed at the note timing of C,
The values “0” and “1” are AND circuits 391 to 39
3 is selected, and the octave code B3', B2',
Obtained as B1'. This shows the octave range of C2. In the case of event b, C of block timing BT0
At the note timing of , the condition of the AND circuit 385 is satisfied as described above, and the signal BQ2 becomes "1". On the other hand, since the signal B8 indicating the 8th is "1", the signal given from the OR circuit 397 to the AND circuit 398 is always "1" while the bass is being sounded.
At the note timing of C when the signal CNT is generated, the output BQ1 of the AND circuit 398 becomes "1". When BQ1 and BQ2 are both "1", the output B1 of the exclusive OR circuit 386 is "0", and the AND circuit 3
The output B2 of the inverter 87 is "0", and the output B3 of the inverter 389 is "1". Therefore, at the note timing of the eighth, that is, the root note C, where the base tone key data KP is "1", octave codes B3', B2', and B1' having a value of "100" are obtained. This shows the C3 octave range. In the case of event c, the subordinate note to be generated has a note name other than C. Signal at note timing other than C
CNT is “0”, AND circuits 385 and 3
The output of 98 becomes "0". The AND circuit 399 becomes operational, but since the output of the delay flip-flop 394 is "0" in the case of the root note C, the output of the AND circuit 399 also becomes "0". Therefore, the signal
Both BQ1 and BQ2 become "0", the output B1 of the exclusive OR circuit 386 is "0", the output B2 of the AND circuit 387 is also "0", and the output B3 of the inverter 389
becomes “1”. Therefore, the bass note key data of the subordinate note becomes “1” at note timing other than C.
Octave codes B3', B2', and B1' having a value of "100" are output at the timing of KP. This indicates that the secondary tone is in the range of C#2 to B2. When the root note is other than C, the C note timing signal CNT is “0” when the root note data RTLD′ becomes “1”, so the output BQ2 of the AND circuit 385 is
is always “0”. In addition, as mentioned above, the root note data RTLD' is the AND circuit 396 and the OR circuit 39.
7 and stored in delay flip-flop 394. When "1" is input to the delay flip-flop 394 at the note timing of the root note, the output of the delay flip-flop 394 rises to "1" with a delay of one key time. As an example, the output Q of delay flip-flop 394 when the root note is G is shown at 394-Q in FIG. Scanning cycle pulse 4.5M
When the old memory is cleared at the timing , the output of the delay flip-flop 394 falls to "0" at the note timing B one key time later. Root note data generated at note timing of G
When "1" of RTLD' is taken in, the output of the delay flip-flop 394 rises to "1" at the note timing of F# one key time later. Therefore, at block timings BT0 and BT1,
At the note timing of notes B to G# higher than the root note G, the output of the delay flip-flop 394 is "0", and at the note timing of notes F# to C lower than the root note G, the output of the delay flip-flop 394 is "1". First, in the case of event d, the signal CNT is always "0" at the note timing of the root note (notes other than C), and the output of the delay flip-flop 394 is output from the AND circuit 399 via the OR circuit 384 to the signal BQ.
It is given as 1. As also shown at 394-Q in FIG. 16, the output of the delay flip-flop 394 is still "0" at the note timing of the root note. Therefore, both signals BQ1 and BQ2 are "0", and the values of octave codes B3, B2, and B1 are "100" as in the case of event c described above. Key data that becomes “1” at the note timing of the root note
Based on KP, the value "100" is output as octave codes B3', B2', and B1'. This indicates that the range of the root note is C#2 to B2. In the case of event e, since the signal B8 indicating the 8th is always "1" while the bass note (eighth note) is being generated, the output of the delay flip-flop 394 is always "1", and the OR circuit 384 is output from the AND circuit 399. The signal BQ1 obtained through this is always "1". signal
When BQ1 is "1" and BQ2 is "0", the output B1 of the exclusive OR circuit 386 is "1", the output B2 of the AND circuit 387 is also "1", and the output B3 of the inverter 389 is "0". Become. Therefore, the bass note key data is generated at the note timing of the 8th or root note.
When KP becomes "1", octave codes B3', B2', and B1' having a value of "011" are output. This is the range one octave above the root note, C#3~
B3 is shown. In the case of event f, the note timing of the subordinate note higher than the root note occurs before the note timing of the root note at block timings BT0 and BT1. Therefore, when the base tone key data KP of the secondary tone higher than the root tone is generated, since "1" is not yet stored in the delay flip-flop 394 (see 394-Q in FIG. 16), the OR circuit is activated. 38
The output BQ1 of 4 is "0". Regarding the pitch order at block timings BT0 and BT1, C has the highest (priority), followed by B, A#...C#. A subordinate note higher than the root note is a note other than C, i.e. B, A#,...D (C# is the lowest note, the last note timing of BT1, so it cannot be a subordinate note higher than the root note) If the signal
When CNT is "0", the AND circuit 399 becomes operational, and the output "0" of the delay flip-flop 394 is used as the signal BQ1. At this time, since both signals BQ1 and BQ2 are "0",
As in the case of event c above, octave code B
"100" is obtained as 3, B2, and B1. Therefore, the octave range of the subordinate note higher than the root note (C#2 to B2) is the same as the root note (D2 to B2).
When the subordinate note higher than the root note is C, the AND circuit 398 becomes operational when the signal CNT is "1", and the output of the OR circuit 397 is used as the signal BQ1. When the C note timing signal CNT is generated at block timing BT0, a pulse of 4.5M is also generated, so the AND circuits 395 and 3
The signal applied from 96 to the OR circuit 397 is "0", and the signal BQ1 is "0". Therefore, "100" is obtained as octave codes B3, B2, and B1, and C as a subordinate note is always generated at the higher note of C3. In the case of event g, the note timing of the subordinate note lower than the root note occurs after the note timing of the root note at block timings BT0 and BT1. Therefore, when the base tone key data KP of the subordinate note lower than the root note is generated, "1" is already stored in the delay flip-flop 394 (see 394-Q in FIG. 16), and the AND circuit 399 The signal BQ1 outputted from the OR circuit 384
becomes “1”. When the signal BQ1 is "1" and BQ2 is "0", the octave codes B3, B2, B1 are "011", as in the case of event e.
is obtained, and the range of C#3 to C4 is set. However, as mentioned above, C is treated as a subordinate note higher than the root note, and B cannot be a subordinate note lower than the root note other than C, so this octave code B3, B2, The range of the subordinate tone lower than the root defined by B1 (“011”) is C
#3 to A#3. This is the root note range (C#2
~B2) is one octave higher than B2). The base tone key data KP generated from the base tone key data forming circuit 42 is supplied to the AND circuit 172 of the sound generation assignment control section 19 shown in FIG. The other inputs of the AND circuit 172 are applied with a second half period signal H2 indicating the second half of one key time and a base channel timing signal PchT (FIG. 6) supplied from the timing signal generation circuit 20 (FIG. 2). Therefore, block timing BT0,
When bass note key data KP occurs at the required note timing in BT1 (KP in Figure 16)
), the condition of the AND circuit 172 is satisfied at the second channel timing (PchT generation timing) in the latter 11 bit time within one key time when the key data KP is generated,
Based on the output "1" of the AND circuit 172, a load signal LD is generated from the OR circuit 174.
This load signal LD causes the current key-on memory 177 and key-on memory 178 to be set to "1" in accordance with the base channel timing (PchT).
is taken in. Further, the load signal LD is supplied to the key code memory 24 shown in FIG. bass key data
11 in the first and second half of 1 key time when KP occurs
Regarding the base channel timing in bit time, the conditions of the AND circuit 390 in the octave code forming circuit 383 are satisfied as shown in FIG. 15, and the base channel timing (PchT) is
Octave codes B1' to B3' are output in synchronization with. These octave codes B1' to B3' are supplied to the octave code conversion circuit 26 of FIG. 9, and are inputted to AND circuits 403, 404, and 405 via OR circuits 400, 401, and 402, respectively. The AND circuit 406 in the octave code conversion circuit 26 receives the bass channel timing signal PchT and the bass tone key data forming circuit 42.
(Fig. 15) Base timing signal BT supplied from the lower key area key-on memory 39 (Fig. 14)
Lower key range any key-on signal supplied from
LKAKO is entered. The output of the AND circuit 406 is passed through the OR circuit 156 to the AND circuits 403 to 4.
Join 05. Therefore, when some key is pressed in the lower key range (LKAKO is "1") and a bass note is to be produced (BT is "1"), at the bass channel timing (PchT is "1") , AND circuit 40
3 to 405 become operational, OR circuit 400 to
Selects the octave codes B1' to B3' of the bass tone given through the OR circuits 157 to 402.
159. At this time, the output of the inverter 155 is "0" so that the scan key display line 1
The octave codes B1-B3 given from 2 are blocked by AND circuits 152-154. The timing at which the octave codes B1' to B3' of the bass sound are selected and output from the octave code conversion circuit 26 coincides with the timing at which the load signal LD for bass sound assignment is generated in accordance with the bass channel timing. . In addition, the note codes N1 to N4 supplied to the scanning key display line 12 at this time indicate which note name the current note timing (that is, the current one when the bass note key data KP is generated) corresponds to. , that is, represents the pitch name of the bass note. This is because all the processing in the chord detection control circuit 30 in FIG. 12 or the automatic bass chord processing circuit 40 in FIG. 15 is performed in synchronization with the note timing in key scanning (see FIG. 8 or FIG. 16). This is clear from the fact that Therefore, when the load signal LD for bass tone assignment is generated, the key code memory 24
On the input side, note codes N1 to N4 indicating the name of the bass note to be generated (to be assigned) and octave codes B1 to B3 (B1' to B3') indicating the octave range of the bass note are given. The key codes N1 to B3 representing the bass tones are taken into the key code memory 24 and stored in synchronization with the bass channel timing, which is the generation timing of the load signal LD. In this way, the bass note is assigned a dedicated one as directed by the signal PchT.
channel. Note that the current key on memory 177 (10th
Although "1" is once taken in at the timing of the base channel in Fig. 2), this is meaningless data. This is because the output (KON') of the current key-on memory 177 is not used for bass tone assignment processing. The "1" stored in the key-on memory 178 at the timing of the bass channel is used as a key-on signal KO1 indicating that a bass tone should be generated. This base channel key-on signal KO1 is stored and held via an AND circuit 181. AND circuit 18
The output of an AND circuit 407 is applied to the other input of 1 via an OR circuit 408. AND circuit 40
Similarly to the AND circuit 406 (FIG. 9) described above, the lower key range any key-on signal LKAKO, base timing signal BT, and base channel timing signal PchT are input to 7. Signal LKAKO and BT
is “1”, the AND circuit 181 is passed through the AND circuit 407 at each generation timing of the signal PchT.
becomes operational and stores the base channel key-on signal KO1. When the bass sound timing ends, the bass timing signal BT becomes “0”
The key-on signal KO1 of the base channel is cleared when the key-on signal KO1 falls or when all keys in the lower key range are released (LKAKO is "0"). As mentioned above, the signal LKAKO retains "1" even after the key is released in memory mode (14th
(see figure), the memory function is also applied to the bass sound. Chord Detection in Single Finger Mode In Single Finger Mode (SF), the lower range of the keyboard is used to specify the root note and chord type of the chord, rather than specifying the note itself to be played. Ru. Conventionally, root notes and chord types in single finger mode were specified using separate keyboards (lower keyboard and pedal keyboard, for example) or switch rows, but with the electronic musical instrument of this invention ) keyboard (lower keyboard area) to specify both. That is, in the lower key range (F#3 to C2),
One key corresponding to the root note name is the lowest note (in this example, it is the highest note, but it may also be the lowest note)
, and other keys are used to specify the chord type. Specifically, when pressing a key with the root note name as the highest note, the chord type is pressed with a key on the lower note side than the root note name. The chord types are specified by pressing a white key to specify a seventh chord, by pressing a black key to specify a minor chord, and by pressing nothing other than the root key to specify a major chord. shall be. Note that the method of specifying chord types is not limited to the method of distinguishing between white keys and black keys, but it is possible to adopt other suitable methods, such as distinguishing by key range. The SF root note detection priority circuit 32 in the chord detection control circuit 30 shown in FIG. By preferentially detecting the scanning timing of pressed keys, the root note name specified in single finger mode performance is detected. Since key scanning is performed in the order of high notes, the note timing that first becomes "1" is the key scanning timing of the most pressed key. The delay flip-flop 271 of the SF root detection priority circuit 32 stores a cancel signal (eighth
(see figure) and is cleared before the lower key area scanning timing (see figure 8). Before the key scan timing of the highest note pressed in the lower key range,
The lower key range key data LKKD is "0", and the state of the delay flip-flop 271 is "0".
At the key scanning timing of the most pressed key in the lower key area, the lower key area key data LKKD becomes "1". At this time, the delay flip-flop 271 delays and outputs the key scanning result "0" one key time before, and the output of the inverter 273 becomes "1". Furthermore, the single finger mode signal SF applied to the AND circuit 274 is "1" in the single finger mode. Therefore, the output of the inverter 273 and the lower key range key data
The AND circuit 274 to which LKKD is input, when the lower key area key data LKKD becomes "1" for the first time in one scanning cycle, that is, at the scan timing (note timing) of the highest pressed key in the lower key area,
Outputs “1”. At the next key scan timing of the highest pressed key, the output of the delay flip-flop 271 rises to "1" (highest key data delayed by one key time), and thereafter, in the next scan cycle, the cancel signal goes to "0". It holds "1" until the value is reached. Therefore, key data is scanned at the scan timing of keys on the bass side (later in the key scan order) than the most pressed key in the lower key range.
Even if LKKD becomes “1”, the inverter 27 inverts the output “1” of the delay flip-flop 271.
3, the low-pitched key data LKKD is blocked by the AND circuit 274. In this way, only the key data (LKKD) of the most pressed key in the lower key area is selected with priority, and the AND circuit 27
Output from 4. The output of the AND circuit 274 is
It is added to the AND circuit 409 as data SFRTLD indicating the note timing of the root note of the chord in single finger mode performance, and is further added to the OR circuit 3.
97 and is output as root note data RTLD. The other input of the AND circuit 409 is an OR circuit 41.
Lower key range any key-on signal via 0
LANKO is added. As mentioned above, this signal LANKO is supplied from the lower key area new key-on detection circuit 38 in FIG. Here, assuming that the C3 key and the A#2 key (black key) are pressed in the lower key area, an example of the generation of the lower key area key data LKKD and the delay flip-flop 2
71 output (271-Q) and AND circuit 274
An example of the output SFRTLD is shown in FIG. Lower key range key data LKKD which is time division multiplexed data
C that appears at the beginning of (occurs between block timing BT7 and 1st key time of BT10)
Data SFRTLD is generated at timing 3, and delay flip-flop 271 is generated at the next timing.
When the output (271-Q) of A#2 rises to "1", the key data of A#2 is blocked by the AND circuit 274. As already explained with reference to FIG. 13, the lower key area any key-on signal LANKO rises to "1" at the scan timing of the newly pressed key (new key), and thereafter at the beginning of the next scan cycle. This signal maintains "1" until it is cleared by a cancel signal before the key range scanning timing. Therefore, if the highest pressed key in the lower key area is pressed for the first time, the signal is generated at the timing of data SFRTLD (timing of the highest pressed key).
LANKO becomes "1", but otherwise the signal LANKO is "0" at the timing of generation of the highest pressed key data SFRTLD. In the example of Fig. 17, if the highest pressed key in the lower key area, C3, is pressed for the first time, the signal LANKO is generated from the scanning timing of C3.
rises to “1” and the data generated at that time
SFRTLD is selected by the AND circuit 409 (Fig. 12), and the root note data is passed through the OR circuit 297.
Output as RTLD. However, the highest pressed key C
If the key A#2, which is lower than 3, is pressed for the first time, the signal LANKO is activated at the scanning timing of A#2.
rises to “1”, the signal LANKO is still “0” at the scanning timing of C3, and the data
SFRTLD is blocked by AND circuit 409, and root note data RTLD is not generated. Data SFRTLD is similarly blocked if no any key-on signal LANKO is generated. Therefore, in single finger mode, the root note data RTLD is generated only when the highest pressed key in the lower key range is newly pressed, that is, only when the root note is changed.
is output. The root note data RTLD in the single finger mode is generated during the lower key area scan timing (block timings BT7 to BT9 and the lowest key scan timing CNT), unlike in the finger chord mode. In FIG. 12, the SF root note detection priority circuit 32
An inverter 275 and an AND circuit 269 provided between the lower key area key data register 35 and
When storing the lower key range key data LKKD in the register 35, the key data (LKKD) of the highest note (root note) selected preferentially by the priority circuit 32 is canceled and only the key data specifying the chord type is selected. This is a circuit for When the data “1” of the highest pressed key (C3 in the example of FIG. 17) appears as the key data LKKD added to one input of the AND circuit 269, the output SFRTLD of the AND circuit 274
is "1", and the output of the inverter 275 is "0". Therefore, the key data LKKD of the most pressed key (ie, the root note) is blocked by the AND circuit 269 and is not added to the register 35. The output of the inverter 275 is "1" except for the scan timing SFRTLD of the highest pressed key, and the key data LKKD on the bass side (that is, specifying the chord type) is selected by the AND circuit 269 and the OR circuits 276, 2
The data is taken into the register 35 via 77. An example of the output of the AND circuit 269 is shown at 269 in FIG. The key data for the most pressed key C3 has been canceled, and only the key data for the key A#2 has been selected. Since the AND circuit 278 for memory retention is enabled to operate during the lower key area scan timing (
5.6 and 14.15 are “1”), register 35
The key data that specifies the chord type imported into
The data is stored while being circulated through the register 35 in 12 stages. Stages Q1, Q3, Q of register 35
The outputs of 6, Q8, and Q10 are OR circuit 4 for black key detection.
12, stages Q2, Q4, Q5, Q
7, Q9, and Q11 and the output of the OR circuit 277 are input to the OR circuit 413 for white key detection. The outputs of the OR circuits 412 and 413 are applied to an AND circuit 414 of the minor chord memory 36 and an AND circuit 415 of the seventh chord memory 37, respectively. The other inputs of AND circuits 414 and 415 have the lowest key C.
Signal CLT indicating the scanning timing of 2 (Fig. 8)
is supplied from the key scanning circuit 11 (FIG. 7).
AND circuits 414 and 415 become operable at the key scanning timing of the lowest key C2, and the outputs of OR circuits 412 and 413 become the AND circuit 41.
4,415 through the delay flip-flop 304.
and 305, respectively. At this time, the signal
The old storage states of delay flip-flops 304 and 305 are cleared by the output "0" of NOR circuit 308 which inverts CLT. When the signal CLT becomes "0" at the next timing, the output of the NOR circuit 308 becomes "1", and the OR circuit 308 prepared just before
12 and 413 output signal state is AND circuit 30
6 and 307 to delay flip-flop 30
4,305, each is self-maintained. When the lowest key scanning timing signal CLT is generated, the data of the lowest key C2 is generated as the key data LKKD, and the data output from the 12th stage Q12 of the register 35 is also the data of C (C3
key data). Therefore, OR circuit 277
Then, key data (note data) indicating whether or not the C key (C3 or C2 in the lower key range) is pressed is supplied to the white board detection OR circuit 413. At this time, from stages Q1 to Q11 of the register 35, the key data (note data) of C# to B corresponding to the scan timing 1 key time to 11 key hours earlier than the scan timing of C is sent for 1 key time to 11 key time, respectively. The output is delayed by 11 key times. Therefore, stages Q2, Q4, Q
5, Q7, Q9, Q11 are D, E, F, G,
Key data for A and B (that is, white keys) are output respectively. Also, stages Q1, Q3, Q6,
From Q8 and Q10, C#, D#, F#, G#, A
Key data of # (that is, black key) is output respectively. Therefore, if any white key is pressed as the key for specifying the chord type, at the lowest key scanning timing (CLT is "1"), the output of the OR circuit 277 or stages Q2, Q4, Q4 of the register 35, etc.
“1” from Q5, Q7, Q9, Q11
is output from the OR circuit 413 to the AND circuit 41
5, "1" is stored in the delay flip-flop 305 of the seventh chord memory 37. Also,
If some black key is pressed as the key that specifies the chord type, at the lowest key scanning timing,
Stages Q1, Q3, Q6, Q of register 35
8, Q10 outputs "1" from the OR circuit 412 to the delay flip-flop 304 of the minor chord memory 36 via the AND circuit 414.
“1” is stored in . Furthermore, if no key specifying the chord type is pressed, the outputs of the OR circuits 412 and 413 are both "0" at the lowest key scanning timing, and "0" is stored in the delay flip-flops 304 and 305. be done. As previously mentioned, the outputs of delay flip-flops 304 and 305 are transferred to delay flip-flops 314 and 315, but this transfer occurs only when a "1" is stored in delay flip-flop 299. In the case of single finger mode, the AND circuit 411 is enabled to operate by the single finger mode signal SF, and the OR circuit 41
The output "1" of 0 is stored in the delay flip-flop 299 via the AND circuit 411 and the OR circuit 298. As described above, the OR circuit 410 is supplied with the lower key range any key-on signal LANKO. Therefore, when a new key is pressed in the lower key range, that is, when the root note is changed (in the example in Figure 17, C3 is the new key).
Alternatively, when the chord type is changed (in the example of FIG. 17, A#2 is new key), "1" is stored in the delay flip-flop 299, thereby clearing the old memories of the delay flip-flops 314 and 315 and delaying the chord. The outputs of flip-flops 304 and 305 are taken into flip-flops 314 and 315. Note that the other input of the OR circuit 410 is a signal △ supplied from the mode switching control circuit 15 (FIG. 4).
A signal ΔF which is an inversion of ΔF is added. The signal △ is used when switching modes (including switching between finger code mode and single finger mode).
Since the signal is "0" only for 4.5ms+α (FIG. 5), conversely, the signal ΔF becomes "1" only for about one scanning cycle (4.5ms+α) at the time of mode switching. This signal ΔF functions to clear the stored data min and 7th in the minor chord memory 36 and the seventh chord memory 37 at the time of mode switching. For example, when switching from finger chord mode to single finger mode, the pulse
When the 4.5M timing signal △F rises to “1” (because △F falls to “0” as shown in Figure 5), the signal SF goes to “1” one key time later.
(see latch circuit 14-4 in FIG. 4).
Based on the signals SF and △F, the AND circuit 41
1 (FIG. 12) is "1" for 4.5 ms and is stored in delay flip-flop 299.
Based on the output "1" of the delay flip-flop 299, the delay flip-flops 314 and 3
The chord type data min and 7th in the fine guard chord mode stored in 15 are cleared. At this time, delay flip-flops 304 and 3
05 to delay flip-flops 314 and 315
The data taken in is "0". This is because, as shown in FIG. 4, when the signal Δ becomes "0" when switching from the finger code mode to the single finger mode, the signal ΔF (that is, Δ Mode switching pulse with the same time width as F)
This is because ABC is generated. By this mode switching pulse ΔABC, the key data (KD when LK is "1") in the lower key range is blocked for one scanning cycle in the AND circuit 142 (FIG. 7) of the key scanning circuit 11. Ru. Therefore, based on the signal ΔF input to the OR circuit 410 in FIG. 12, the minor chord memory 36 and the seventh chord memory 3
7 is cleared, the lower key range key data LKKD is not generated, and the data taken into the delay flip-flops 304 and 305 from the black key detection OR circuit 412 and the white key detection OR circuit 413 is "0".
It is. In the chord detection control circuit 30 of FIG. 12, the parts corresponding to the SF chord type detection section 33 (FIG. 1) are all the parts described so far, and the reference numerals are 35, 36, 37, 269, etc. 275,
299, 409 to 415, etc. Chord key data formation in single finger mode The root note data RTLD is the root note shift register 4 in Figure 15 in the same way as in the finger chord mode.
1 is stored. The difference from the finger chord mode is that the root note data RTLD in the single finger mode occurs at the lower key range scan timing (BT7 to BT9 and CLT, that is, the first key time of BT10), and The point is that it only occurs at the key scan timing. The data that becomes "1" at the note timing of the root note is sequentially delayed by the shift register 41, and from each stage Q1 to Q11, each degree 7, 7 ^b , 6, 6 ^b ,
As described above, "1" is output at note timings indicating subordinate note names corresponding to 5, 5 ^b , 4, 3 ^, 3 b , 2, 2 ^b . In addition, the NOR circuit 345
Since the later arrival priority circuit is configured by
RTLD' is cleared in the same manner as described above. The data corresponding to the minor 7th ^7b and perfect 5th 5 output from stages Q2 and Q5 of the shift register 41 are input to AND circuits 416 and 417 in the SF chord key data forming circuit 43, respectively.
In addition, stages Q8 and Q of the shift register 41
AND circuits 355 and 356 for switching between major third 3 and minor third ^3b to which the output of 9 is added also form part of the SF chord key data forming circuit 43. Depending on "1" or "0" of the minor chord data min supplied from the minor chord memory 36 in FIG. is selected in the same manner as described above. The seventh chord data 7th supplied from the seventh chord memory 37 in FIG.
6, and a signal obtained by inverting the data 7th is applied to the AND circuit 417. Therefore, in the case of a seventh chord, since the data 7th is "1", the subordinate note timing data corresponding to the minor seventh ^7b is selected in the AND circuit 416, and the subordinate note timing data of the perfect fifth is not selected. . When the chord is not a seventh chord, data 7th is "0", so the AND circuit 417 selects subordinate note timing data corresponding to a perfect fifth, and does not select subordinate note timing data for a minor seventh. The root note (1
The data indicating the note timing (degree) is OR-synthesized in an OR circuit 418, and is provided to one line 419 as time-division multiplexed data indicating chord constituent notes in a single finger mode. line 41
9 is supplied to an AND circuit 421 via an AND circuit 420. A single finger mode signal SF is input to the AND circuit 420, and the multiplexed data on the line 419 is selected only in the single finger mode. AND circuit 4
21 is supplied with a signal BT12.21 supplied from the OR circuit 148 (FIG. 7) of the key scanning circuit 11.
13 (FIG. 8) and a lower key region any key-on signal LKAKO supplied from the lower key region key-on memory 39 (FIG. 14). The output of the AND circuit 421 is supplied as single finger chord key data SFKL to the OR circuit 169 in the window circuit 21 of FIG. Therefore, single finger chord key data
SFKL sets block timings BT12 and BT13 (BT12.1) when in single finger mode (SF is "1") and under the condition that some key is pressed in the lower key range (LKAKO is "1").
3 is generated at "1"). During the 12 key times at block timings BT12 and BT13, the root note data goes through the root note shift register 41 once, and is transferred from each stage Q1 to Q12 to the root note and each degree 7, 7 ^b , ... 2 ^b , 2. “1” is sequentially output at the note timing of the corresponding note name. Each frequency 7,
Stages Q1 to Q1 corresponding to 7 ^b ,...2 ^b , 2
The note timing at which “1” is output from 1 (that is, the note name corresponding to each degree) is the root note data.
RTLD′ note timing (i.e. root note name)
What is determined according to is as already explained in connection with the bass note key data formation. SFKL in Figure 17 has C3 and A#2 in the lower key area.
The chord key data SFKL generated when (black key) is pressed is shown. Since the specified chord is a C minor chord, the key data SFKL becomes "1" at the note timings of C, G, and D#.
That is, at the note timing C of block timing BT12, the root note data RTLD' becomes "1", and the AND circuit 346 and the OR circuit 34
4 to the OR circuit 418 and output as key data SFKL. Since the seventh chord data 7th is "0", the output of the stage Q2 which is delayed by two key times from the root note data RTLD' is not selected by the AND circuit 416. However, AND circuit 4
17 is operable, and the output of the stage Q5 which delayed the C note timing data (RTLD') by 5 key times becomes "1" at the G note timing, and the output "1" of this stage Q5 is the AND circuit 417. to the OR circuit 418. Therefore, the key data SFKL becomes "1" at the note timing of G, which is the subordinate tone of the fifth. Since the minor chord data min is "1", the AND circuit 355 is inactive, the AND circuit 356 is enabled, and the C
The output of stage Q9 which delayed the note timing data (RTLD') by 9 key times becomes "1" at the note timing of D#, and the output "1" of stage Q9 is transferred from AND circuit 356 to OR circuit 41.
Added to 8. Therefore, the key data SFKL becomes "1" at the note timing of D#, which is a subordinate tone of a minor third. In addition, in the case of a major chord, the data min and 7th are both "0", so the key data is set corresponding to the three notes of the 1st and 5th (by the AND circuit 417) and the major 3rd (by the AND circuit 355). SFKL is generated. Also, in the case of a seventh chord, the data min
is "0" and the 7th is "1", so key data SFKL is generated corresponding to the three tones of the 1st, the minor 7th (by the AND circuit 416), and the major 3rd (by the AND circuit 355). . Further, in the case of a minor seventh chord, both data min and 7th are "1", so key data SFKL is generated corresponding to the three tones of the 1st, minor 7th, and minor 3rd. The key data SFKL supplied to the OR circuit 169 in FIG. 10 is supplied to the sound generation assignment control section 19 as lower key range key data KL. Therefore, in the same way as the allocation process of the lower key range key data KL mentioned above,
The three notes of the chord constituent notes (the three notes indicated by SFKL) are placed in any of the lower key area sounding channels indicated by the lower key area channel timing signal LchT.
are allocated respectively. However, at block timings BT12 and BT13 at which this single finger chord key data SFKL is generated, the values of octave codes B3, B2, and B1 supplied from the key scanning circuit 11 via line 12 are "110", and the actual does not correspond to the octave range (see Table 5). Therefore, the octave code conversion circuit 26 shown in FIG. 9 changes the values of the octave codes B1 to B3 to values corresponding to a predetermined musical range. That is, the single finger mode signal SF and the signal BT12.13 are input to the AND circuit 160, and the block timings BT12 and BT13 at which the key data SFKL is generated in the single finger mode (SF is "1") are determined.
(BT12 and BT13 are "1"), the output of the AND circuit 160 becomes "1". This AND circuit 1
The output "1" of 60 is inverted by inverter 161, making AND circuit 153 inoperable. Bit B2 of the octave codes B1 to B3 given from line 12 is input to this AND circuit 153, and the value of bit B2 is forcibly changed to "0". Therefore, the octave code conversion circuit 26
Octave code B of line 12 input to
The values of 3, C2, and B1 are changed from "110" to "100" and output. This indicates the range from C3 to C#2 as shown in Table 5 above.
The note codes N1 to N4 on line 12 indicate note names corresponding to each note timing of the key data SFKL, so they are used as they are.
Therefore, in this embodiment, chords in single finger mode are generated in the C3 to C#2 range. By the way, in the case of single finger mode, the key data KD in the lower key range does not directly indicate the chord constituent notes that are actually produced. Therefore,
The key data KD of the lower key area given from the key scanning circuit 11 is transferred to the current key-on memory 177 (first
(Figure 0) cannot be used. Therefore, an AND circuit 199 and a NAND circuit 202 (FIG. 10) are provided to block the key data KD used to clear the current key-on memory 177. When in single finger mode (SF is “1”), the output of the NAND circuit 202 is “0” at the lower key area scanning timing (LK is “1”)
Therefore, all the key data KD of the lower key range supplied via the OR circuit 198 is blocked. Therefore, in the case of single finger mode, even if "1" is temporarily loaded into the current key-on memory 177 at the lower key range channel timing by the load signal LD, a matching signal is subsequently generated at the same channel timing. Cleared immediately when EQ is generated from comparator circuit 25. The storage of the key-on signal KO1 of the lower key area channel in the key-on memory 178 is maintained based on the lower key area any key-on signal LKAKO in the single finger mode. The lower key area any key on signal LKAKO supplied from the lower key area key on memory 39 shown in FIG. 14 is inverted by the inverter 422 shown in FIG. 10 and applied to the OR circuit 211. When not in the memory mode, the lower key area any key-on signal LKAKO falls to "0" when no key is pressed in the lower key area. When the signal LKAKO becomes "0", the output of the inverter 422 becomes "1", and the output from the OR circuit 211 to the AND circuit 2
“1” is added to 12, and furthermore, at the lower key region channel timing (LchT is “1”) AND circuit 2
12, “1” is added to the NOR circuit 206. As a result, the output of the NOR circuit 206 becomes "0" at the lower key region channel timing, and the key-on signal KO1 of the lower key region channel is all cleared to "0". When in memory mode (M is “1”), the lower key range any key-on signal LKAKO is “1” as described above.
Therefore, even if the key specifying the root note and chord type in the lower key range is released, the key-on signal KO1 of the lower key range channel is not cleared and remains at "1". At this time, the AND circuit 421 in the SF chord data forming circuit 43 in FIG.
Since it is enabled by LKAKO, key data SFKL continues to appear. When in memory mode, the lower key range key-on signal of the key-on memory 178 is activated when a chord is changed.
KO1 is cleared. When the chord is changed, key data SFKL of the note that has not been assigned to the lower key range channel is generated. During 1 key time when this new key data SFKL is generated,
Comparison circuit 2 at lower key area channel timing
5 (FIG. 9), no coincidence signal EQ is generated.
Therefore, the output of the delay flip-flop 193 (FIG. 10) occurs at the 11-bit time in the latter half of the 1-key time when new key data SFKL is generated.
LKOEXT is "0" and the output of inverter 214 is "1". In addition, the output of the current key-on memory 177 corresponding to the lower key area channel
KON' has already been cleared and becomes "0".
Therefore, the 11-bit time in the second half of the 1-key time when new key data SFKL is generated (H2 is “1”)
In this case, the condition of the AND circuit 213 is satisfied, the output of the AND circuit 212 becomes "1" at the lower key region channel timing (LchT is "1"), and all key-on signals KO1 of the lower key region channel are cleared. On the other hand, if the chord does not change, the key data
Every time SFKL occurs, a matching signal EQ is generated at the timing of one of the lower key range channels,
It is applied to an AND circuit 183. In the case of single finger mode, the signal applied to the OR circuit 187
SF is "1", AND circuit 184 becomes inoperable, and AND circuit 215 becomes operable.
The key-on signal KO1 from the key-on memory 178 is applied to the other input of the AND circuit 215, and its output is applied to the other input of the AND circuit 183 via the OR circuit 185. Therefore, in single finger mode, the key-on signal KO
1 occurs, the above match signal
EQ is selected by AND circuit 183 and stored in delay flip-flop 193. Due to the output LKOEXT "1" of the delay flip-flop 193, the condition of the AND circuit 213 is not satisfied, and the key-on signal KO1 is not cleared. Note that even after the key is released in the memory mode, even if a key specifying the same chord as the stored chord is pressed anew, the key-on signal KO1 is not cleared. Since this is the same chord, the key data based on the new key press is
A coincidence signal FQ is also generated for SFKL, and the key-on signal KO1, which is stored and retained even after the key is released, is given from the AND circuit 215 to the AND circuit 183 via the OR circuit 185. The match signal FQ is selected, and the output LKOEXT of the delay flip-flop 193 becomes “1”.
Due to the fact that In this manner, in the memory mode of the single finger mode, the key-on signal KO1 of the lower key region channel is cleared not only when a new key is pressed but also when a chord is changed. Note that the formation of the bass note key data KP and its pronunciation assignment processing in the single finger mode are exactly the same as in the case of the finger chord mode described above. When forming chord key data in single finger mode, the contents of the root note shift register 41 (Fig. 15) were used at block timings BT12 and BT13, but when forming base note key data, The same contents of the root shift register 41 are set to block timing BT.
0, I am trying to use it with BT1. Arpegillo sound key data formation and sound generation assignment processing In this embodiment, automatic arpeggio performance is performed in conjunction with automatic bass chord performance (finger chord mode or single finger mode). Select one note (note name) in the pitch order specified by the arpeggio pattern data ArpPT from among the chord constituent notes (root note and subordinate note) assigned to the lower key channel, and select that note ( Note codes N1 to N4 (note names) and predetermined octave codes B1'' to B3'' are added to create a dedicated arpeggio channel (the channel indicated by the signal AchT).
By assigning it to , an arpeggio sound is generated. The arpeggio note key data forming circuit 44, a detailed example of which is shown in FIG. Arpeggio sound key data KA with name note timing
is generated and the octave chord B1''~B
Generates 3″.Arpeggio pattern data
The selection of note names in the pitch order indicated by ArpPT is performed by selecting the desired note name from the time-division multiplexed chord constituent tone key data AKD that becomes "1" at the note timing of each note name making up the chord. This is done by extracting one key data at note timing. The key codes N1 to N3 of the notes already assigned to the lower key area channel (these are output from the key code memory 24 in FIG. 9 according to high-speed channel timing) and the scanning key display line 1
The chord constituent note key data AKD is obtained based on the key codes N1 to N3 of No. 2 (which are output according to a key scanning timing that is slower than the channel timing). 25, an octave code conversion circuit 27 (FIG. 9), a delay flip-flop 193 (FIG. 10) that stores the coincidence signal EQ, and an ARP key data storage section that generates chord constituent note key data AKD based on its output LKOEXT. 34
(Fig. 1) is used. A detailed example of the ARP key data storage section 34 corresponds to the AND circuit 423 and the lower key range key data register 35 in FIG. In FIG. 18, the arpeggio key data forming circuit 44 includes a key data extraction circuit 424, a homophone name removal circuit 425, and an octave chord forming circuit 4.
It has 26. Key data extraction circuit 424
The outline of the processing performed in is as follows. Key-on signal KO given from key-on memory 178 (FIG. 10) via homophone name removal circuit 425
1 (each channel is given in a time-sharing manner according to high-speed channel timing), the counter 427 adds and counts the notes assigned to the lower key range channel, that is, the number n of chord constituent notes. , this count value and the autorhythm device 45
The comparator 428 compares the value of the arpeggio pattern data ArpPT given from (Fig. 1), and either the count value of the counter 427 and the value of the data ArpPT become the same, or the count value of the counter 427 is larger. The counter 427 multiplies the number n of notes constituting the chord by N (where N is an integer). The value of the arpeggio pattern data ArpPT indicates the number of chord constituent notes that should be generated as an arpeggio sound, counting from the bass side (that is, it indicates the pitch order counting from the bass side). Further, this arpeggio pattern data ArpPT is generated corresponding to the timing (period) at which the arpeggio sound of the pitch order indicated by the data is to be generated. When the value of the data ArpPT is larger than the number n of chord constituent tones, the multiplier N in the count value N·n of the counter 427 becomes a value of 2 or more. When the counter 427 completes the addition counting to obtain the above counted value N.n, 1 is decremented from the counted value of the counter 427 every time the chord constituent tone key data AKD is generated (every time it becomes "1"). Subtract. The chord constituent note key data AKD is the final stage Q1 of the lower key range key data register 35 in FIG.
2 to the AND circuit 429 of the key data extraction circuit 424 in FIG. This key data
AKD is time-division multiplexed data that is generated in order from the note name (note timing) on the treble side, similar to key data KD obtained by key scanning. The count value N·n of the counter 427 before the subtraction starts corresponds to the pitch order of the highest note among the chord constituent notes (that is, the first appearing key data AKD). This is because the number n of chord constituent notes corresponds to the pitch order of the highest note (nth one counting from the bass side), so N・n, which is an integer multiple of it, also corresponds to the pitch order of the highest note. This is because it will become a big deal. By subtracting 1 rank from the count value N・n corresponding to the highest note, the count value (N・n−1) when 1 is subtracted is the pitch rank of the chord component note one below the highest note (lower side The count value (N.n-2) when subtracted by 2 is the pitch order of the chord constituent notes two places below the highest note (N.n-1st counting from the bass side). 2nd),
In this way, the order of pitches on the bass side is sequentially adjusted. In addition, the key data that performs the above subtraction
AKD also gradually shifts to the bass side (because it is generated from the treble side). Therefore, the count value N·n−x of the counter 427 (where x is the number of times subtracted by 1) corresponds to the pitch order of the key data AKD that occurs next (the first one to arrive), and this calculation One chord constituent note key data AKD generated when the numerical value N・n−x and the pattern data ArpPT match corresponds to the note in the pitch order specified by the data ArpPT, and its The key data AKD (when in a matching state) is extracted as the arpeggio key data KA. For example, if the chord constituent notes are C, E, G,
Assuming that there are 3 sounds (n=3) and the value of the pattern data ArpPT is "7", they are summarized and illustrated in Table 8 below.

[Table] In other words, in "addition", the count value of the counter 427 becomes N by multiplying the number of chord constituent notes by an integer until it becomes equal to or larger than the value "7" of the pattern data ArpPT.・n=3×
3=9. In "subtraction", if 1 is subtracted at the timing of the highest note C and the next note G of the chord constituent note key data AKD generated from the treble side, the subtraction result is N・n-x=9-2= 7, which matches the data ArpPT. Therefore, the key data AKD generated at the next timing E is extracted as the arpeggio sound key data KA. The homophone name removal circuit 425 detects at block timings BT12 and BT13 whether tones with the same name in different octaves are assigned to different channels in the lower key range channel (ARP homophone processing shown in Z in FIG. 8). , if there are notes in the chord with the same name in different octaves, key-on signals for that number (not both channels with the same name, but only one)
BO1 is removed and the remaining key-on signal KO1 of the lower key area channel is supplied to the key data extraction circuit 424. The chord constituent note key data AKD used for arpeggios only supports note names and does not support the octave of the chord constituent notes assigned to the lower key range channel. This homophone name removal circuit 425 is used to reduce the signal KO1 to only one signal (for one channel).
is provided. Note that in the single finger mode, chord constituent tones with the same note name in different octaves are impossible, so the same note name removal circuit 425 is used only in the finger chord mode. Counter 427 of key data extraction circuit 424
The above-mentioned addition counting process (this is Z in Fig. 8)
) is the block timing BT14 and BT15 after the homophone name detection process.
It will be held in The octave code forming circuit 426 is a circuit for forming octave codes B1'' to B3'' indicating the octave range of the note name indicated by the arpeggio note key data KA, that is, the octave range of the arpeggio note. The values of the octave codes B1'' to B3'' are determined according to the value of the multiplier N of the count value N·n obtained as a result of the above-mentioned addition counting process in the counter 427 of the key data extraction circuit 424. That is, each time the number n of chord constituent notes is repeatedly added in the counter 427, it is incremented by one octave, and if the number n continues to be repeatedly added after reaching the predetermined maximum octave, then It is possible to lower the pitch one octave at a time. Next, the operation of the homophone name removal circuit 425 in the finger chord mode will be explained. In order to detect that notes with the same pitch name are assigned to different channels in the lower keyboard channels, a comparison circuit 25 (FIG. 9) is utilized at block timings BT12 and BT13. As already explained, this block timing BT
C or C in the 12 key time of 12 and BT13
The note codes N1 to N4 of the 12 note names up to # are sent from the key scanning circuit 11 to the comparison circuit 2 via line 12.
5 is sequentially applied to one input A every key time (see note timing in FIG. 16). Further, at block timings BT12 and BT13, the values of octave codes B3, B2, and B1 given from the key scanning circuit 11 via line 12 are "110". The values of the note codes N1 to N4 of the key codes N1 to N3 indicating the assigned sounds of each channel are output from the key code memory 24 in a time-divisional manner according to high-speed channel timing, and the note codes N1 to N4 given to the lines 12 In order to compare the value of N4 using the comparison circuit 25, the octave codes B1 to B1 outputted from the key code memory 24 are
Set the value of B3 to the octave code B1 of line 12.
I am trying to convert it to the same value as B3. That is, in the octave code conversion circuit 27 of FIG. 9, the fine guard code mode signal FC and the signals BT12 and BT13 (FIG. 8) are input to the AND circuit 430, and in the fine guard code mode (FC is "1"). ) block timing BT12 and
When BT13 occurs, the output of the AND circuit 430 becomes "1". The output “1” of this AND circuit 430 is passed through the OR circuit 431 to the OR circuit 163.
-165, and all octave codes B1, B2, and B3 output from the key code memory 24 are forcibly converted to "1". However, the AND circuit 4 to which the output "1" of the OR circuit 163 is added
32 becomes inoperable due to the output "0" of the inverter 433 which is the inversion of the output "1" of the AND circuit 430, so bit B1 of the octave code is forcibly set to "0". In this way, the octave code B output from the key code memory 24
The values of 3, B2, and B1 are converted into the same value "110" as the octave codes B3, B2, and B1 of line 12, and are input to the comparator circuit 25. Therefore, line 12 remains unchanged for one key time.
A matching signal EQ is generated from the comparison circuit 25 at the channel timing to which the note codes N1 to N4 having the same pitch name as the note codes N1 to N4 supplied to the channel are assigned. At this time, if sounds with the same pitch name are assigned to different channels, coincidence signals EQ are generated at a plurality of channel timings in the first 11 bit times and the second 11 bit times of one key time. As mentioned above, this coincidence signal EQ is applied to AND circuit 183 in FIG. block timing
In BT12 and BT13, the signal BT12.13 applied to the OR circuit 187 is "1", and the key-on signal KO1 from the key-on memory 178 is applied from the AND circuit 215 to the other input of the AND circuit 183 via the OR circuit 185. This match signal
If the EQ is generated corresponding to the lower keyboard channel timing during which the key is being pressed (KO1 is "1") (LchT is "1"), "1" is stored in the delay flip-flop 193. The output LKOEXT of the delay flip-flop 193 is applied to the AND circuit 434 of the homophone name removal circuit 425 in FIG. Other inputs of the AND circuit 434 are applied with the coincidence signal EQ from the comparison circuit 25 (FIG. 9), the finger code mode signal FC, and the signal BT12.13. Output signal of delay flip-flop 193
LKOEXT rises to "1" with a delay of one bit time from when the match signal EQ is generated. Therefore, the condition of the AND circuit 434 is not satisfied for the first match signal EQ, and the condition of the AND circuit 434 is satisfied when the match signal EQ is generated thereafter. The output of AND circuit 434 is applied to AND circuit 435. The other inputs of the AND circuit 435 include a signal 2 obtained by inverting the second half period signal H2 (FIG. 3) (that is, a signal that becomes "1" in the first 11 bits of one key period) and the output of the AND circuit 436. Added. The AND circuit 436 receives the key-on signal KO1 output from the key-on memory 178 in FIG.
and the lower key range channel timing signal LchT are added, and the lower key range channel key-on signal
Only KO1 is selected. For example, as shown in N1 to N4 in Figure 19b,
Assume that C (that is, C2 and C3), which have the same sound in a different octave, is assigned to lower key range channels "3" and "5", respectively, and G and E notes are assigned to lower key range channels "7" and "9", respectively. Assume that . As shown in FIG. 6, the lower key region channel timing signal LchT is generated at channel timings "3", "5", "7", and "9". 19th
Figure b shows the block timing shown in Figure 19a.
This is an enlarged view of the first key time of BT12, that is, the time during which note code C is given to line 12 as note codes N1 to N4. Since the note codes N1 to N4 of line 12 are C, a match signal EQ is generated from the comparator circuit 25 at channel timings 3 and 5 when the note codes N1 to N4 of C are output from the key code memory 24 (FIG. 9). be done. First matching signal EQ at channel timing 3 in the first half of 1 key time
is generated, one bit time later the output of the delay flip-flop 193 (FIG. 10)
LKOEXT rises to “1”. Therefore, the condition of AND circuit 434 in FIG. 18 does not hold at channel timing 3. This signal LKOEXT continues until it is cleared by signal S1 at the beginning of the next key time (see AND circuit 195 in Figure 10).
Retains “1”. Therefore, when the second match signal EQ is generated at subsequent channel timing 5, the condition of the AND circuit 434 is satisfied.
The signal 2 applied to the AND circuit 435 and the output KO1/LchT of the AND circuit 436 are generated as shown in FIG. 19b. In the AND circuit 435, the second coincidence signal EQ that satisfies the condition of the AND circuit 434 corresponds to the lower key area channel during key depression (including the case where the key is considered to be depressed in memory mode). On the condition that (KO1 and LchT
is “1”), limited to the first half period (2 is “1”),
Outputs “1”. The output "1" of this AND circuit 435 (shown at 435 in FIG. 19b) is output by the counter 4.
37 as a count pulse. The coincidence signal EQ is also generated at the timing of channels 3 and 5 in the second half period, and the condition of the AND circuit 434 is satisfied, but since the signal 2 is "0", no count pulse is given. Different octave homophone name detection processing as shown in FIG. 19b is performed at block timings BT12 and BT
Each note timing in 13 (Figure 19a)
It is repeated every time. The counter 437 is incremented by one each time a same-sound name in a different octave is detected. However, in the example shown in Fig. 19, the only homophonic name in a different octave in the lower key range channel is C, so in the end, block timing BT1
3 is completed, the count value of the counter 437 is 1 (binary "01"). In addition, the counter 43
7 is a signal obtained by inverting the cancel signal (Fig. 8) to set the block timings BT5 and BT6.
It is reset when As described above, at block timings BT12 and BT13 in the finger chord mode, the counter 437 counts the number (number of sets) of names with the same sound in different octaves. The key-on signal KO1 of the lower key range channel output from the AND circuit 436 is applied to the AND circuit 439 via the AND circuit 438, and further via the OR circuit 440 to the count input T of the counter 427.
join. The AND circuit 438 counts the pulse train (output of the AND circuit 436) of the time-division multiplexed key-on signal KO1 which becomes "1" corresponding to the lower key area channel timing during key depression by the counter 437. Pulses equal to the number of different octave homophone names (i.e. key-on signal KO1)
It is intended to remove. The count output of the counter 437 is added to one input of the comparator 441.
The output of the counter 442 is added to the other force of 1. Counter 442 is cleared at the beginning of the 1 key period by signal S1 (FIG. 3). counter 4
37 is a value other than 0, the two inputs of the comparator 441 do not match at the beginning of one key time (because the counter 442 has been cleared to 0), and the match output EQL is "0". The AND circuit 443 is supplied with a signal obtained by inverting the coincidence output EQL, and when the coincidence output EQL is "0",
That is, when the counter values of the counters 437 and 442 do not match, the key-on signal KO1 given from the AND circuit 436 is selected and the counter 44
Add to count input T of 2. The coincidence output EQL is also applied to the AND circuit 438, and when the count values of the counters 437 and 442 do not match, the AND circuit 438 is rendered inoperable and the key-on signal KO1 is blocked. counters 437 and 4
When the count value of 42 matches, it means that the same number of key-on signals KO1 as the number of different octave homophone names have been removed (blocked). Therefore, after a match, the AND circuit 438 is enabled (EQL
is "1"), and the remaining lower key range key-on signal KO1 is passed. Furthermore, the signal 2 obtained by inverting the second half period H2 is added to the other input of the AND circuit 438, and the lower key area key-on signal KO is generated only in the first half period of one key time.
Pass 1. This is because, since the counter 442 is cleared at the beginning of one key time, effective homophone number key-on signal removal processing can be performed during the first 11 bit times of one key time. Similarly to FIG. 19b, lower key area channel 3,
FIG. 20 shows an example of the above removal process assuming that four tones C, C, G, and E are assigned to keys 5, 7, and 9, and that all of these keys are being pressed and a key-on signal KO1 is generated. Shown below. In Figure 20
KO1.LchT indicates the key-on signal KO1 of the lower key range channel output from the AND circuit 436. 442-Q indicates the output of the counter 442.
Counter 4 that counted the number of homophone names in different octaves
The count value of 37 is 1 (binary "01").
At the beginning of 1 key time, the output of comparator 441
EQL is "0", and the first key-on signal KO1/LchT generated within one key time is blocked by the AND circuit 438. However, this first key-on signal increments the counter 442 by one. Then, the count value 1 of the counter 437 and the count value of the counter 442 match, and the match output EQL rises to "1". Therefore, in the first half period (2 is "1"), the three key-on signals KO1 and LchT generated thereafter pass through the AND circuit 438. The number of pulses generated within one key period of the key-on signal KO1n output from the AND circuit 438 corresponds to the number n of notes constituting the chord after removing homophone names. A key-on signal KO1n consisting of a pulse train of a number corresponding to the number n of notes constituting this chord.
occurs repeatedly every one key time, as shown in FIG. However, the process of counting the number of homophone names in different octaves in the counter 437 is surely completed at the block timing BT13 as described above.
Since this is the end of the chord, the key-on signal KO1n output from the AND circuit 438 after the next block timing BT14 effectively calculates the number n of notes constituting the chord.
It shows. Therefore, the signal BT14.15 is input to the AND circuit 439, and the key-on signal KO1n output from the AND circuit 438 (that is, the homophone name removal circuit 425) is selected and added to the counter 427 at block timings BT14 and BT15. There is. In addition, in the case of single finger mode, a counter 437 that counts the number of homophone names in different octaves
The output of comparator 441 is always “0” and
The output EQL of is always “1”. Therefore, all the key-on signals KO1 of the lower key region channel are outputted from the AND circuit 438 as the signal KO1n. The counter 427 is an up-down counter, and the signal BT14.15 is an up-down switching input.
In addition to UP, block timing BT14 and
Set to up count mode in BT15. Therefore, block timing BT14 and
In BT15, the key-on signal KO1n input from the AND circuit 439 to the counter 427 via the OR circuit 440 is added and counted by the counter 427. The output of the NAND circuit 444 is applied to the reset input R of the counter 427, which is normally always reset and the arpeggio pattern data
Block timing BT immediately after ArpPT occurs
The reset is released only in BT14, BT15, BT0, and BT1. All bits of the arpeggio pattern data ArpPT are given to the OR circuit 445, and when some arpeggio pattern data ArpPT is supplied, the OR circuit 44
The output of 5 rises to "1". The output "1" of the OR circuit 445 passes through the AND circuit 446 on the condition that some key is pressed in the lower key area (including the case where the key is considered to be pressed even after the key is released in memory mode), and is passed through the flip-flop 448. is input. The other input of the AND circuit 446 receives the lower key area any key on signal LKAKO supplied from the lower key area key on memory 39 (FIG. 14) to the shift register 447.
given via. The shift register 447 is controlled by the scan cycle pulse 4.5M.
This stage/1 bit is used to set the waiting time until all of the pressed keys in the lower key area are completely assigned to sound. The flip-flop 448 is an AND circuit 446
The signal given from the AND circuit 446 is taken in at the timing of signals BT12 and BT13 (that is, block timings BT12 and BT13), and when the output of the AND circuit 446 is "1", it is in the set state, and when it is "0", it is inverted to the reset state. . Therefore, the OR circuit 445 becomes "1" in response to the generation of pattern data ArpPT and becomes "0" in response to its disappearance.
The rise timing and fall timing of the output signal of the block timing BT12 and BT13 are
A signal synchronized with the flip-flop 448 is output from the flip-flop 448. The output Q of the flip-flop 448 is connected to the delay flip-flop 44 for rising edge detection.
9 and the AND circuit 450, and the AND circuit 429, and is further output as the arpeggio timing signal AT. FIG. 21 shows an example of the actual generation timing of the arpeggio pattern data ArpPT. This generation time width is about the same as a general key press time, and is a relatively long time of, for example, around several 100 ms. FIG. 21 also shows the arpeggio timing signal AT outputted from the flip-flop 448 in response to the generation timing of the data ArpPT. signal
The generation time width of AT approximately corresponds to the generation time width of data ArpPT. However, the rising and falling timing of signal AT is block timing BT12.
is synchronized with. BT0-15 in FIG. 21 indicate block timings BT0-BT15. The output AT of the flip-flop 448 is delayed by one key time by a delay flip-flop 449, and the inverted signal of the delayed output is input to an AND circuit 450. Therefore, the output of the AND circuit 450 is the second
As shown at 450 in FIG. 1, it becomes "1" only during one key time at the rising edge of the arpeggio timing signal AT. The output of AND circuit 450 is applied to set input S of flip-flop 451.
A reset input R of the flip-flop 451 is supplied with a signal obtained by inverting the cancel signal (FIG. 8). Therefore, as shown at 451-Q in FIG. 21, the output Q of the flip-flop 451 is output only from the block timing BT12 at which the arpeggio timing signal AT rises to the block timing BT4 of the next scanning cycle (actually, the clock pulse Output timing is 1 due to φAB
(albeit delayed by key time) becomes “1”. The output of flip-flop 451 is applied to NAND circuit 444. Signals BT0.1 and BT14.15 (FIG. 8) are applied to other inputs of the NAND circuit 444 via an OR circuit 453. Therefore, as shown at 444 in FIG. 21, the output of the NAND circuit 444 is at block timings BT14, BT15, BT15, and
It is "0" only in BT0 and BT1, and is always "1" in other cases. Only when the output of the NAND circuit 444 is "0", the reset of the counter 427 is released and counting becomes possible. Therefore, the counter 427 performs addition counting only at block timings BT14 and BT15 immediately after the arpeggio pattern data ArpPT is generated, and performs subtraction counting only at block timings BT0 and BT1 immediately after that (signals BT14.15 are " 0”, it enters the down count mode). A comparator 428 inputs the count value of the counter 427 to one input A and inputs the arpeggio pattern data ArpPT to the other input B.
Inverters 454 to 4 that invert the count value of 7
57 and the output 4 of this inverter 454 to 457
A 4-bit adder 458 that adds the bits and 4-bit data ArpPT, and an AND circuit 459 to which all 4-bit outputs of this adder 458 are input.
It consists of The carry signal CRO generated when the contents of the adder 458 overflows is used as a signal indicating that the value of the pattern data rpPT (B input) is larger than the count value of the counter 427 (A input) (B>A). used. For example, when the count value of the counter 427 (A input) is “0011” and the data ArpPT is “0100” (B
>A), the calculation formula is Therefore, the carry signal CRO becomes "1". When the count value A of the counter 427 and the value B of the data ArpPT are the same or the data ArpPT is smaller (B≧A), the carry signal CRO is not generated.
Count value A of counter 427 and data ArpPT
When the values of B and B match, all the outputs of the adder 458 become "1" and the output of the AND circuit 459 becomes "1". For example, if the count value A of the counter 427 is "0011" and the value B of the data ArpPT
When is also “0011”, the calculation formula is , and all outputs are "1". The output "1" of the AND circuit 459 is delayed by one key time by a delay flip-flop 460, and is applied to the AND circuit 452 as an arpeggio pattern data match signal ArppEQ. The carry signal CRO of the adder 458 is applied to an AND circuit 461 and delayed by one key time in a delay flip-flop 462.
Join 39. Therefore, the block timing BT14 (pattern data
At the first 1-key time (note timing of C) of BT14) immediately after the occurrence of ArpPT, the output from the adder 458 is at the last 1-key time (second note timing of C) of the immediately preceding block timing BT13. The state of the carry signal CRO is output from the delay flip-flop 462. At block timing BT13, the counter 427 has been reset as described above, so the value of the arpeggio pattern data ArpPT is larger, and the carry signal CRO is "1". Therefore, the output of the delay flip-flop 462 is always "1" during the first 1 key time of block timing BT14 when addition and counting is performed, and the number of chord constituent notes generated in the first half of this 1 key time is Key-on signal K01 corresponding to n
(n) (see Figure 20) are all AND circuits 439
through the OR circuit 440 to the counter 42
7 is given. As described above, the counter 427 always adds and counts the number n of chord constituent tones during the first one key period of the block timing BT14. If the value of the arpeggio pattern data ArpPT is the same as or smaller than the number n of notes that make up the chord, then in the process of counting the first n (that is, in the first 11 bit times of the first 1 key time of block timing BT14) ), comparator 428
, B>A no longer holds true, and the carry signal
CRO falls to “0” (see Figure 22). “0” of this carry signal CRO is the same key time (BT
In the latter half of the first key time of BT14), the clock pulse φA (see FIG. 3) is taken into the delay flip-flop 462, and at the next key time (the second key time of BT14, that is, the note timing of B). Clock pulse φB
(Fig. 3), the flip-flop 4
62. Therefore, if B>A is no longer established in the comparator 428, the signal applied from the delay flip-flop 462 to the AND circuit 439 becomes "0" at the next key time, and the key-on signal KO1(n) is blocked. , the count is stopped (see 462-Q in FIG. 22). On the other hand, if the value of the arpeggio pattern data ArpPT is larger than the number n of chord constituent notes, the comparator 428 still determines that B>A even after the counting of n in the first 1 key time of the block timing BT14 is completed. This holds true (see Figure 23). Therefore, the carry signal CRO is still "1", and the delay flip-flop 462 outputs "1" at the next key time as well. Therefore,
At the next key time (the second key time of BT14, that is, the note timing of B), n key-on signals KO1(n) are passed through the AND circuit 439 and given to the counter 427, and the counter 4
27 is further counted up by n. In the process of counting n for the second time, if B>A no longer holds true in the comparator 428, the output of the delay flip-flop 462 becomes "0" at the next key time, as described above, and the subsequent counting is will be stopped. On the other hand, if B>A still holds true in the comparator 428, the counter 427 further increments the count by n at the next key time. In this way, until the count value A of the counter 427 becomes equal to or larger than the value B of the pattern data ArpPT (until B>A no longer holds true), 1
The number of key-on signals KO1(n) is counted in key time units. That is, the number n of chord constituent tones is multiplied by an integral number (N times). When the comparator 428 no longer holds B>A, the count value N・n of the counter 427
The relationship between the value of the pattern data ArpPT and the value of the pattern data ArpPT is as follows. N.n≧ArpPT>(N-1).n On the other hand, in the octave code forming circuit 426, the counting operation of the octave counter 463 is performed in parallel with the addition counting operation of the counter 427. Octave counter 463 is an up-down counter, and the inverted output of T-type flip-flop (binary counter) 464 is applied to its up-down control input (UP). Octave counter 463 and T-type flip-flop 46
Similarly to the counter 427, the output of the NAND circuit 444 (FIG. 21) is applied to the reset input R of No. 4. Note that the T-type flip-flop 464 has two
A phase clock pulse φAB is applied, and the count input T or reset input R is connected to the pulse φA.
It takes it in, sets the state with pulse φB, and outputs it.
Therefore, there is generally a one key time delay between the input timing and the output timing of T-type flip-flop 464. The octave counter 463 receives “1” from the OR circuit 465 to the count input T.
is counted at the timing of clock pulse φB. The output of the AND circuit 466 or 467 is input to the count input T of the counter 463.
given through. T-type flip-flop 46
The output of an AND circuit 468 or 469 is applied to count input T of 4 via an OR circuit 470. The output of AND circuit 461 is given to AND circuits 466 to 469. AND circuit 461
The above-mentioned carry signal CRO and signal BT14.1
5 is delayed by one key time by a delay flip-flop 471. Block timing BT1 at which the reset of the counter 463 and flip-flop 464 is released.
4 and the first 1 key time of BT15 (the first 1 key time of BT14, that is, the note timing of C)
In this case, the output of the delay flip-flop 471 is "0" (see FIGS. 22 and 23), and the output of the AND circuit 461 is "0" and the outputs of the AND circuits 466 to 469 are "0". The state of does not change. That is, the inverted output Q of the flip-flop 464 is set to "1" by the reset, and the counter 463 is in the up-count mode. Further, the outputs Q2 and Q1 of the counter 463 are set to "00" by the reset. The outputs Q2 and Q1 of the counter 463 are the AND circuit 472 and the NOR circuit 4.
A code conversion circuit 475 consisting of 73 and 474 converts it into octave codes B3, B2, and B1. This code conversion table is as shown in Table 9.

[Table] Therefore, when the counter 427 first counts the number n of chord constituent notes (first key time of BT14), the values of octave codes B3, B2, and B1 output from the code conversion circuit 475 are C. #2~C
It is "100" indicating the range of 3. This is the lowest octave range for arpeggio notes. From the second key time (note timing of B) of block timing BT14 to the first key time of block timing BTO, the output of the delay flip-flop 471 becomes "1" (the 22nd key time).
(See Figure 23). During the initial counting process of the number n of notes constituting a chord in the counter 427, a carry signal is generated.
When CRO becomes “0” (see Figure 22), the number n of chord constituent notes is the pattern data.
If the value is equal to or larger than ArpPT, the signal CRO is already at "0" when the output of the delay flip-flop 471 rises to "1".
The condition of AND circuit 461 is not satisfied. Therefore,
“1” is not given to the count input T of the octave counter 463, and the output Q of the counter 463
1, the value of Q2 remains unchanged at "00" (see Figure 22). If the carry signal CRO remains "1" even after the counter 427 completes the first count of the number n of notes making up the chord (see Figure 23), that is, the number n of notes making up the chord is greater than the value of the pattern data ArpPT. If it is smaller, the condition of AND circuit 461 is satisfied when the output of delay flip-flop 471 rises to "1", and "1" is supplied to AND circuits 466 to 469. AND circuits 466 and 46
The inverted output of flip-flop 464 indicating the up-count mode is added to 8, and this signal is currently "1". AND circuit 4
A signal obtained by inverting the inverted output of flip-flop 464 by inverter 476 is applied to 67 and 469. In addition, a signal obtained by inverting the output of an AND circuit 477 which inputs the outputs Q1 and Q2 of the counter 463 by an inverter 478 is added to the other input of the AND circuit 466. Output Q of counter 463
1 and Q2 reach the maximum value "11", the output of the AND circuit 477 becomes "1". Outputs Q1 and Q2 of the counter 463 are also applied to a NOR circuit 479. When the outputs Q1 and Q2 of the counter 463 are "00", the output of the NOR circuit 479 is "1". The output of NOR circuit 479 is applied to AND circuit 469. A signal obtained by inverting the output of NOR circuit 479 by inverter 480 is applied to AND circuit 467.
Further, the output of the AND circuit 477 is
Added to 8. Initially, flip-flop 46
Since the inverted output of 4 is "1" and the output of inverter 478 is "1", the condition of AND circuit 466 is satisfied and "1" is given to count input T of octave counter 463. The octave counter 463 immediately counts "1" of the count input T that rises with the rise of the output of the delay flip-flop 471 in accordance with the pulse φB.
The outputs Q2 and Q1 change to “01” (23rd
(see figure). Along with this, code conversion circuit 475
Octave code B3, B2, B output from
The value of 1 changes to "011" (see Table 9), indicating the range C#3 to C4 one octave higher. 2 of the number n of chord constituent notes in the counter 427
During the second counting process, the carry signal CRO becomes “0”
When the count pulse φB falls (see Figure 23), the next time the count pulse φB rises (A of BT14
Note timing of #) The output of the AND circuit 461 is "0", and the octave counter 463 does not count. Thereafter, the count values Q2 and Q1 of the counter 463 are kept at "01" (see FIG. 23). 2 of the number n of chord constituent notes in the counter 427
Carry signal CRO remains “1” even after the end of the first count
If it remains, the next key time (BT1
4 A# note timing) At the beginning of the pulse φ
When B rises, the octave counter 463 is further set to 1 by the signal "1" from the AND circuit 466.
It will be counted up. In this way, the carry signal
Every 1 key time until CRO falls to “0”,
That is, each time the counter 427 repeats addition of the number n of notes constituting the chord, the octave counter 463 performs counting. In addition, block timing BT1
When the values Q2 and Q1 of the octave counter 463 reach the maximum value "11" by the third up-count performed at the 4th key time of 4 (note timing of A), the condition of the AND circuit 468 is satisfied, and the 1st After the key time (note timing of G#), the output of flip-flop 464 becomes “0”
to be reversed. As a result, the counter 463 enters the down count mode, and now the AND circuit 467
It counts down by 1 every key time based on the signal "1" given from . After that, the carry signal CRO continues to be "1" and the outputs Q2 and Q1 of the counter 463 become "00" due to the third down count performed at the 1st key time of block timing BT15 (note timing of F#). Then, the condition of AND circuit 469 is satisfied, and one key time later (note timing of F)
At this point, the output of flip-flop 464 is inverted to "1". In this way, until the carry signal CRO falls to "0", the octave counter 463
Now repeat the up count and down count.
In this way, up-counting and down-counting are repeated when the value of the pattern data ArpPT is much larger than the number n of chord constituent tones. FIG. 22 shows an example of the operation of the key data extraction circuit 424 and the octave chord formation circuit 426 when the chord constituent tones are C, E, and G and the value of the arpeggio pattern data ArpPT is "1". This is a timing chart. Also, the second
FIG. 3 is a timing chart showing an example of operation when the chord constituent tones are the same three tones C, E, and G, and the value of the arpeggio pattern data ArpPT is "4". 22 and 23 show the 21st
As shown in the figure, the output of the NAND circuit 444 is “0”
The block timings BT14 to BT1 when the reset of the counter 427 is released are shown in an enlarged manner. In this case, the chord constituent notes (C,
Key-on signal KO1(n) corresponding to E, G)
may be considered to occur in the same way as the one shown enlarged in FIG. 20. 22 and 23, 427-Q indicates the count value of the counter 427, 462-Q indicates the output of the delay flip-flop 462, 471-Q indicates the output of the delay flip-flop 471, and 461 indicates the AND circuit 461. 463 indicates the state of outputs Q1 and Q2 of the octave counter 463. In the case of the example in Figure 22, the block timing BT
When the first pulse of the key-on signal KO1(n) is added by the counter 427 at the first 1 key time (note timing of C) of 14, the count value of the counter 427 is "1" and the value of the pattern data ArpPT is "1". '' match, and the carry signal CRO output from the comparator 428 falls to "0". However, since the state of the delay flip-flop 462 does not change yet (remains "1"), the counter 427 continues counting, and the second and third key-on signals KO1(n) generated in the first half of one key time are counted. Each pulse is counted, and the count value 427-Q changes from "1" to "2" and then to "3". At the next note timing of B, the output 462-Q of the delay flip-flop 462 falls to "0". Therefore, the AND circuit 439 becomes inactive and the key-on signal KO1
(n) is blocked and counting is stopped. Thereafter, the count value 427-Q of the counter 427 remains at "3". 1st time (at note timing of C)
Since the carry signal CRO falls to "0" due to the addition, the output 471-Q of the delayed flip-flop 471 is output at the next note timing of B.
When the signal rises to "1", the condition of the AND circuit 461 is not satisfied. Therefore, the octave counter 46
3 holds the reset value "00" without being counted. In the case of the example in Figure 23, the block timing BT
Key-on signal at the first 1 key time of 14
Even if you count all the pulses of KO1(n),
The count value 427-Q of the counter 427 is "3"
, which is smaller than the value "4" of the pattern data ArpPT. Therefore, in the comparator 428, B>A is first established, and the carry signal CRO continues to be output. At the next note timing of B, when the first pulse of the key-on signal KO1(n) is counted by the counter 427, the counter 427
The count value 427-Q is "4". Therefore, at this time, the carry signal CRO falls to "0". On the other hand, the output 4 of the delay flip-flop 471
Since signal 71-Q has already risen to "1" several bit times ago, the condition of AND circuit 461 is satisfied for a short time until carry signal CRO falls to "0" (461 in FIG. 23). At this time. As mentioned above, the output of the AND circuit 466 is the output of the AND circuit 461.
It becomes "1" in response to the output "1" of the octave counter 463, and is applied to the count input T of the octave counter 463. The output of the AND circuit 461 becomes "1" during several bit times in the first half of one key time, and since pulse φB is generated at this time (see Fig. 3), the octave counter 463 counts 1. It will be uploaded. As a result, the outputs Q2 and Q1 of the counter 463 change to "01". On the other hand, the counter 427 counts the successively generated key-on signal KO1(n), and the count value changes from "4" to "5" and then to "6".
Changes to. At the note timing of the next A#, the generation timing of the pulse φA just before that (1
Since the carry signal CRO has already become "0" in the second half of the key time, the output 462-Q of the delay flip-flop 462 falls to "0" and the counter 427 stops adding the key-on signal KO1(n). be done. At block timings BT14 and BT15, while the counter 427 is adding or counting the octave counter 463 as described above, the lower key area key data register 3 in FIG.
5, key data is taken in corresponding to each note timing of chord constituent notes. A circuit that captures key data of chord constituent notes (notes assigned to the lower key channel) for arpeggio performance.
The portion corresponding to the ARP key data storage section 34 (FIG. 1) is a portion consisting of the lower key range key data register 35, an AND circuit 423, and OR circuits 276 and 277 in the detailed example of FIG. AND circuit 423 has block timing BT14.
and the output of a delay flip-flop 193 (FIG. 10) which stores the signal T14.15 indicating BT15 and the matching signal EQ for the lower key range channel.
LKOEXT is input, and at block timing BT14.15, this signal LKOEXT is selected and input to the lower key range key data register 35 via OR circuits 276 and 277. During this time, the signal 14.15 obtained by inverting the signal BT14.15 is "0", and the self-holding AND circuit 278 is inoperative. Therefore, block timing BT1
4. The key data previously stored in the register 35 (in the case of finger chord mode, it is the key data of the keys pressed in the lower key range stored for chord detection; in the case of single finger mode, it is the key data for chord type detection) The stored key data (corresponding to the white key or black key) is blocked by the AND circuit 278 and is not fed back to the register 35 (cleared). 12 note timings (C to C#) occurring at block timings BT14 and BT15
Among them, a note timing having the same note name as a note (chord constituent notes) already assigned to the lower key range channel is selected, and "1" is taken into the lower key range key data register 35 in correspondence with that note timing. . The note name corresponding to each note timing is indicated by note codes N1 to N4 applied from the key scanning circuit 11 to the scanning key display line 12. Therefore, the comparison circuit 25 (9th
Figure) is used. Block timing BT14
And since the values of octave codes B3, B2, and B1 given to the scanning key display line 12 in BT15 are "111", the key code memory 24
Of the key codes N1 to B3 of each channel output from (Fig. 9), octave codes B1 to B
It is necessary to change the value of 3 to "111" and input it to the comparison circuit 25. The reason is that in this case, comparison circuit 2
5, it is only necessary to compare note codes N1 to N4, so the values of octave codes B1 to B3 are forcibly fixed to the same value. Therefore, in the octave code conversion circuit 27 shown in FIG.
Input BT14.15 to OR circuits 163 to 165 via OR circuit 431, and set the block timing.
In BT14 and BT15, the values of octave codes B1 to B3 are forcibly changed to "111". At this time, since the signal BT12.13 is "0", the output of the AND circuit 430 is "0", the output of the inverter 433 is "1", and the OR circuit 16
3 passes through the AND circuit 432. Note codes N1 to N4 from line 12 that maintain the same value for one key time and key code memory 24 that changes at high speed for each channel timing.
The note codes (N1 to N4) from are compared in the comparator circuit 25, and a match signal EQ is generated at the channel timing when both match. The occurrence of the matching signal EQ at the lower key channel timing means that the current note timing (its note name is indicated by note codes N1 to N4 on line 12) and the note with the same note name are chord constituent notes ( This means that it exists in the lower key range channel assigned note). The coincidence signal EQ generated at the lower key range channel timing (LchT is "1") is selected by the AND circuit 189 (FIG. 10) and stored in the delay flip-flop 193, and the output LKOEXT of this delay flip-flop 193 is output at the next key time. “1” until the start of S1 (until the timing of occurrence of S1)
becomes. The circuit operation until this signal LKOEXT is generated is exactly the same as the example shown in FIG. 19b. Although FIG. 19b shows block timing BT12, the same applies to BT14. Furthermore, an AND circuit 183 is used to select the matching signal EQ on the condition that it is the channel that is currently being pressed.
(FIG. 10), the key-on signal KO1 from the key-on memory 178 is applied via the AND circuit 215 and the OR circuit 185. This is OR circuit 1
This is because the signal BT14.15 applied to 87 becomes "1". As is clear from the above, the output LKOEXT of the delay flip-flop 193 becomes "1" (at least in the latter half of one key period) corresponding to the note timing of the chord constituent notes. Note that when notes with the same name in different octaves are assigned separately to the lower key range channels, naturally only one signal LKOEXT is generated corresponding to one note timing (see FIG. 19b). For example, if a chord consists of three tones, C, E, and G, C at block timings BT14 and BT15.
and the second corresponding to the note timing of G and E.
As shown in FIG. 4, the signal LKOEXT becomes "1". If we look at the generation timing of the signal LKOEXT in detail, as shown in FIG. 19b, it rises to "1" in the middle of the first half of one key period, and falls to "0" at the beginning of the next one key period. However, when this signal LKOEXT is taken into the register 35 in FIG. 12, the pulse φ _A generated in the latter half of one key time
(Fig. 3), the state of the input signal LKOEXT is acquired, and the pulse φ _B (Fig. 3) generated in the first half of the next one key time sets the storage state of the register 35 (the output state of each stage). setting), it is sufficient for the signal LKOEXT to be in the correct state in the latter half of one key time. The above signal is taken into the lower key range key data register 35 via the AND circuit 423 (FIG. 12) at block timings BT14 and BT15.
LKOEXT is delayed by 12 key times in the register 35 and block timings BT0 and BT1
is output from the twelfth stage Q12. The output of the twelfth stage Q12 of this register 35 is supplied to the AND circuit 429 in FIG. 18 as chord constituent note key data AKD. Signal shown in Figure 24
The state of the key data AKD output from the register 35 after 12 key hours based on LKOEXT is shown in the figure. Note timing is in treble order (C,
B...C#), so the treble side key data AKD is generated first. In the examples of FIGS. 22 and 23, it is assumed that the chord constituent tones are C, E, and G, so generated key data AKD is shown in the same way as the key data AKD of FIG. 24. In FIG. 18, the other input of the AND circuit 429 is the arpeggio timing signal AT (21st
) and a signal BT0.1 (FIG. 8) indicating block timings BT0 and BT1 are added. When an arpeggio sound should be generated (AT is “1”), the block timings BT0 and BT1 (BT
0.1 is "1"), chord constituent tone key data AKD is selected by the AND circuit 429. The key data AKD selected by AND circuit 429 is applied to AND circuits 452 and 481. The other input of the AND circuit 481 is a signal S1 (FIG. 3).
is provided via delay flip-flop 482. Delay flip-flop 482 delays signal S1 by one bit time in accordance with system clock pulse φ. Therefore, when the key data KD becomes "1", the AND circuit 481 outputs a pulse "1" for only one bit time at the timing immediately after the signal S1 (timing of channel "2" in the first half of one key time). do. This AND circuit 481
The output pulse is applied to the count input (T) of the counter 427 via the OR circuit 440. At block timing BT0 and BT1, the signal
BT14.15 is “0” and counter 427
is in down count mode. Therefore,
At block timing BT0 and BT1,
The counter 427 is counted down by one each time chord constituent note key data AKD is generated. In the example of FIG. 22, addition counting is stopped when the count value of the counter 427 reaches "3" (427-Q). The key data with the highest value C first at block timing BT0 and BT1
When AKD is applied, the count value of counter 427 is decreased to "2". pattern data
Since ArpPT is "1", the comparator 428
=B does not hold. Therefore, the key data AKD of C
is blocked by AND circuit 452. Next, when the key data AKD of G is given, the counter 427 further counts down by one, and the count value becomes "1". At this time, in the comparator 428, A=
B is established, and the output of the AND circuit 459 becomes "1" (see 459 (A=B in FIG. 22). The condition of the AND circuit 452 in which the output "0" of the AND circuit 459 (see ArpEQ in FIG. 22) is not satisfied, and the key data AKD generated at the note timing of G is also output to the AND circuit 45.
Blocked by 2. The output signal of the delayed flip-flop 460 at the next F# note timing.
ArpEQ rises to “1”. Therefore, the key data at the note timing of E
When AKD occurs, the conditions of the AND circuit 452 are satisfied, the output of the AND circuit 452 becomes "1" corresponding to the note timing of E, and the arpeggio key data corresponding to the note timing of E is generated.
KA is obtained. The output of the flip-flop 451, which is added to the other input of the AND circuit 452, is input to the counter 451, as shown at 451-Q in FIG.
When addition/subtraction counting is performed in step 27, the value is "1". On the other hand, the counter 427 is further counted down by one based on the key data AKD of E, and the count value becomes "0". As a result, A=B in the comparator 428 no longer holds true,
signal at the next D# note timing
ArpEQ falls to “0”. Therefore, even if key data AKD is generated thereafter (although it does not occur in the example of FIG. 22), they are all blocked by AND circuit 452. As described above, the arpeggio pattern data is created from among the multiple chord constituent note key data AKD.
Only one key data KA corresponding to the rank specified by ArpPT is extracted. In the example shown in Figure 22, the pattern data ArpPT is "1", so at the note timing of E, which is the first note from the bass side of the chord constituent notes (C, G, E), that is, the lowest note. Arpeggio sound key data KA
is generated. The arpeggio key data KA is applied to an AND circuit 483 in the octave chord forming circuit 426. The other input of the AND circuit 483 receives the arpeggio channel timing signal AchT (FIG. 6) from the timing signal generation circuit 20 (FIG. 2), and its output is applied to AND circuits 484-486. Octave codes B1-B3 are applied from a code conversion circuit 475 to other inputs of AND circuits 484-486. Therefore, when arpeggio sound key data KA is generated (KA is "1"), octave codes B1 to B3 are selected at the arpeggio channel timing (AchT is "1"), and the octave code B of the arpeggio sound is selected.
1'' to B3''. In the case of Figure 22,
Since the outputs Q1 and Q2 of the octave counter 463 are "00", the octave codes B3", B2", B1" have the value "100" indicating the range of C#2 to C3.
is output. Therefore, the arpeggio note in this case is E2. In the example of FIG. 23, addition counting is stopped when the count value of the counter 427 is "6". Therefore, at block timings BT0 and BT1, when the count is down by one based on the C and G chord constituent note key data AKD, the count value becomes "4", and the output of the AND circuit 459 (second
459 (A=B) in Figure 3 becomes "1". Part 1
After the key time, the signal ArpEQ becomes "1", and when the key data AKD is generated at the note timing of E, "1" is output from the AND circuit 452. Therefore, similar to the example shown in FIG. 22, arpeggio key data KA is generated at the note timing of E. However, in the example of FIG. 23, the outputs Q2 and Q1 of the octave counter 463 are "01", so the values of the octave codes B3'', B2'', and B1'' are the value "011" indicating the range of C#3 to C4. It is.
Therefore, the arpeggio note in this case is E3. The arpeggio key data KA is supplied to an AND circuit 173 (FIG. 10) of the sound generation assignment control section 19. The other inputs of the AND circuit 173 are applied with the arpeggio channel timing signal AchT and the second half period signal H2. As mentioned above, when the arpeggio sound key data KA becomes "1" at the note timing of the sound that should be generated as an arpeggio sound, the single arpeggio key data KA in the second half of that one key time (H2 is "1") Figure 6
AchT), the condition of the AND circuit 173 is satisfied, and one load signal LD is generated via the OR circuit 174. In the key code memory 24 (Fig. 9), the note codes N1 to N4 from the line 12 are stored based on this load signal LD.
(This indicates the note name of the current note timing at which key data KA is generated) and octave code B from the octave code conversion circuit 26.
1'' to B3'' are stored in correspondence with the arpeggio channel. At this time, the octave codes B1'' to B3'' of the arpeggio sound supplied from the octave code forming circuit 426 in FIG. 18 are input to the OR circuits 400 to 402 of the octave code conversion circuit 26, respectively. Also, an AND circuit 487 to which the lower key range any key-on signal LKAKO, the arpeggio channel timing signal AchT, and the arpeggio timing signal AT supplied from the arpeggio sound key data forming circuit 44 in FIG. 18 are input.
is, as long as some key is pressed in the lower key range and the arpeggio note is generated (LKAKO).
and AT is “1”), outputs “1” at the arpeggio channel timing (AchT is “1”),
AND circuits 403 to 40 via OR circuit 156
5 to be operational. Therefore, the AND circuit 403~
Octave codes B1'' to B3'' of the arpeggio sound are selected through key code memory 24
is supplied to On the other hand, a key-on signal KO1 is stored in the key-on memory 178 based on the load signal LD generated at the arpeggi-yo channel timing (KO1
becomes “1”). Further, "1" is temporarily stored in the current key-on memory 177 in correspondence with the arpeggio channel, but it is cleared based on the output of the AND circuit 196 the next time the match signal EQ is generated. Therefore, the current key-on memory 177 is not used at all in the process of allocating arpeggio sounds. The AND circuit 488 holds the key-on signal KO1 stored in the arpeggio channel. Similar to the AND circuit 487 in FIG. 9, the AND circuit 488 receives the lower key range any key-on signal LKAKO, the arpeggio timing signal AT, and the arpeggio channel timing signal AchT. Therefore, when the sound timing of one arpeggio note ends, the signal AT becomes "0", so that the key-on signal of the arpeggio channel that was held until then is
KO1 is cleared. Further, even when the signal AT is being generated, if all the keys in the lower key range are released, the signal LKAKO becomes "0" and the key-on signal KO1 of the arpeggio channel is cleared. In addition, block timing BT14 and BT are used to perform processing for forming arpeggio key data KA.
15, as described above, the octave code conversion circuit 27 (FIG. 9) converts the octave codes B1 to B3 of the key codes N1 to B3 of each channel.
is changed so that the output EQ of the comparator circuit 25 is used for arpeggio processing. Therefore, the coincidence signal EQ is generated regardless of the key data KD actually output from the key scanning circuit 11. As described above, this coincidence signal EQ is also used by the AND circuit 196 (FIG. 10) to control the clearing of the count key-on memory 177. Therefore, block timing BT14 and BT
In order to prevent the count key-on memory 177 from being cleared by the coincidence signal EQ generated at 15 and the assignment of the upper key range and lower key range channels to be canceled, block timings BT14 and BT15 (BT14.15 is set to "1") are set. ), when
OR circuit 19 via OR circuit 201 in FIG.
8 is always given "1", and the signal given from the inverter 197 to the AND circuit 196 is made "0" (that is, a pseudo key-on state is made).
In addition, in the finger guard mode, the above-mentioned also occurs at block timings BT12 and BT13 (see AND circuit 430 in FIG. 9), so in the finger code mode (FC is "1")
At this time, the block timings BT12 and BT13 (BT1
2.13 is "1"), "1" is also input to the OR circuit 201. Details of the multiplexing circuit 28 The multiplexing circuit 28 shown in FIG. 9 receives key codes (note codes N1 to N4 and Octave chord B1~
B3), a key-on signal KO1 which is also time-divisionally output from the key-on memory 178 (Fig. 10) at each channel timing, and an automatic base code mode signal supplied from the mode switching control circuit 15 (Fig. 4). ABC (see FIG. 5), the lower key region any key-on signal LKAKO supplied from the lower key region key-on memory 39 (FIG. 14), and the signal S1 (refer to FIG. 2) supplied from the timing signal generation circuit 20 (FIG. 2). (Fig. 3), lower key area channel timing signal LchT, and key scanning circuit 11 (Fig. 7)
The scanning cycle pulse 4.5M supplied from the autorhythm device 45 (FIG. 1), the chord generation timing pattern pulse CT and the rhythm stop signal RSTP supplied from the autorhythm device 45 (FIG. 1) are input. Inverter 495 lower key area channel timing signal LchT
The inverted signal is applied to the AND circuit 489, and the key-on signal KO1 of channels other than the lower key range channel passes through the AND circuit 489 as it is, and is sent to the AND circuit 49 via the OR circuit 490.
given to 4. In normal mode (without automatic bass chord playing), all channels are upper key range channels, and the signal is
Since LchT is not generated, the key-on signal KO1 of all channels passes through the AND circuit 489 as is. On the other hand, the key-on signal KO1 relating to the lower key region channel is gated by the chord generation timing pattern pulse CT, and is changed to the key-on signal KO1' which becomes "1" only when the pattern pulse CT is generated. Furthermore, if the autorhythm is stopped (RSTP is "1") in the automatic base code mode (ABC is "1"), a normal gate signal NG is generated. The multiplexing circuit 28 outputs the note codes N1 to N4 and octave codes B1 to B3 of the sounds assigned to each channel and the key-on signals KO1 and KO.
1', the normal gate signal NG, automatic base code mode signal ABC and scanning cycle pulse 4.5M are time-division multiplexed into 4-bit data KC1 to KC4 as shown in FIG. data
KC1 to KC4 are time division multiplexed data in which one cycle consists of 22 time slots, and in the time slot column of Fig. 25, each time slot is numbered ``1'' to ``22'' in the order of occurrence. . The time width of one time slot is one bit time of the system clock pulse φ. Therefore, data KC
One repeat cycle of 1 to KC4 takes 1 key time (22
bit time). In the channel column of Fig. 25, there is a time-sharing channel “1” shown in Fig. 6.
to "11" (each channel timing in the sound generation assignment circuit 18 and key code memory 24). For example, the channels for time slots "3" and "4" are "3", which means that the key codes N1 to B3 of the sound assigned to channel "3" and the key-on signals KO1 and KO1' are data KC1 to
This indicates that it will be sent as KC4. Second
The symbols U, L, P, and A shown in the key range column of Figure 5 are as follows:
In the case of automatic bass chord mode, each channel "1" to "11" is an upper key range channel (U), a lower key range channel (L), a bass sound channel (P), or an arpeggio sound channel (A). It shows whether it corresponds to It is clear from the above that in the normal mode, everything switches to "U", that is, the upper key range channel. In time slot "1" of channel "1" which does not correspond to the actual sound generation channel, data KC1 to KC4 are all "1". This is to indicate the reference timing of data KC1 to KC4, that is, time slot "1". Time slot "2" has control signals NG, ABC,
4.5M is sent as data KC1, KC2, and KC3. In the time slots "3" to "22" corresponding to the pronunciation channels, two time slots are assigned to each channel, and in the first time slots "3", "5"..."21", octave codes B1 to B3 are assigned. and key-on signal KO
1. Send KO1' as data KC1 to KC4,
At the next time slot "4", "6"..."22", write note codes N1 to N4 as data KC1 to KC4.
Send as. In addition, although data KC1 to KC4 are shown in FIG. 25 as using all 10 sounding channels (when 10/7 is "0"), data KC1 to KC4 are shown in the 7 channel mode (when 10/7 is "1"). ), it goes without saying that there are time slots in which data N1 to B3 and KO1 are not sent. In the multiplexing circuit 28 of FIG. 9, the AND circuit 496 includes a chord generation timing pattern pulse.
The output of the OR circuit 497 inputting the CT and rhythm stop signal RSTP, the lower key range any key on signal LKAKO and the lower key range channel timing signal
LchT is input and its output is AND circuit 498
join. When the autorhythm is operating, pattern pulses CT are generated intermittently according to the chord sounding pattern, and the rhythm stop signal RSTP is always "0". Therefore, when the autorhythm is operating (when pattern pulse CT can be generated)
Of the key-on signals KO1 that are applied to other inputs of the AND circuit 498, the lower key channel channel (generated when LchT is "1") is used only when the pattern pulse CT is generated, that is, the predetermined chord. It is selected by the AND circuit 498 only at the sound generation timing, and is applied to the AND circuit 494 via the OR circuit 490 as a key-on signal KO1' for the lower key range (chord). Therefore, the notes (chord constituent notes) assigned to the lower key channel channel based on this key-on signal KO1' are all sounded simultaneously and intermittently according to the chord sounding timing pattern (that is, the chord is automatically played in increments). ). When the autorhythm stops, pattern pulse CT is no longer generated. Instead, the rhythm stop signal RSTP continues and becomes “1”,
The key-on signal KO1 in the lower key range passes through the AND circuit 498 without being disturbed. Automatic base code mode (signal ABC is “1”)
When the autorhythm stops (signal RSTP is "1") and some key is pressed in the lower key range (signal LKAKO is "1"), AND circuit 49
9 is satisfied, "1" is applied to the delay flip-flop 501 via the OR circuit 500, and is self-held via the AND circuit 502. The output "1" of this delay flip-flop 501 is inputted to an AND circuit 503 as a normal gate signal NG. This normal gate signal NG is used to control the production of automatic performance sounds (chords, bass sounds, arpeggio sounds) when the autorhythm stops.
When all keys in the lower key range are released (LKAKO is "0") or when switching to normal mode (ABC is "0"), the AND circuit 502 becomes inactive and the normal gate signal NG is deleted. . When the signal S1 (see FIG. 3) is generated at the beginning of one key time, "1" is given to the OR circuits 507 to 510 via the OR circuits 504 to 506, and output from the OR circuits 507 to 510. Data KC1
~KC4 becomes all “1”. This time is the reference timing, that is, time slot "1" in FIG. In the next time slot "2",
The output of the delay flip-flop 511, which delays the signal S1 by one bit time, becomes "1", and the normal gate signal NG and automatic base code mode signal ABC are output via AND circuits 503, 512, and 513.
and scanning cycle pulse 4.5M are selected, and OR circuits 507-5 are selected via OR circuits 504-506.
Given on 09. Therefore, data KC1, KC2,
As KC3, as shown in Fig. 25, signal NG,
ABC, 4.5M is sent. The signal S1 is also applied to a delay flip-flop 515 via an OR circuit 514. The output of the delay flip-flop 515 is connected to an AND circuit 517.
~ 520 and the inverter 516
is inverted and returned to the OR circuit 514. The output of OR circuit 514 is applied to AND circuits 491-494. Octave codes B1 to B3 of each channel, which are output from the key code memory 24 in a time-division manner, are input to AND circuits 491 to 493. The AND circuit 494 receives the key-on signal KO1 of each channel (for the lower key range channel, the KO
1') is input. AND circuit 517-520
A signal obtained by delaying the note codes N1 to N4 of each channel outputted from the key code memory 24 in a time-divisional manner by one bit time by delay flip-flops 521 to 524 is applied to the key code memory 24. AND circuit 51
The outputs of 7 to 520 and 491 to 494 are sent to OR circuits 507 to 510 via OR circuits 525 to 528.
and output as data KC1 to KC4. When the signal S1 is generated (time slot "1"), the output "1" of the OR circuit 514 enables the AND circuits 491 to 494 to operate, but since this is the timing of the unused channel "1", the signals B1 to The values of B3 and KO1 are all “0”. Also, after one bit time (time slot "2"), the delay flip-flop 5
15 becomes "1", and the AND circuit 517~
Note codes N1 to N4 corresponding to channel "1", which enables 520 to operate but is not used.
(that is, all “0” data) is delayed by 1 bit time and transferred to the delayed flip-flops 521 to 5.
It is output from 24. Therefore, the transmission of signals NG, ABC, and 4.5M in time slot "2" is not adversely affected. Further, in time slot "2", a signal "0" obtained by inverting the output "1" of delay flip-flop 515 by inverter 516 is applied to OR circuit 514, and AND circuits 491-494 are inoperable. Therefore, at this time, the octave codes B1-B3 and key-on signal KO1 of channel "2" (FIG. 6) which are applied to AND circuits 491-494 are not selected. The output "0" of this OR circuit 514 is delayed and outputted from the delay flip-flop 515 at the next time slot "3". When the time slot is "3", the "0" output from the delay flip-flop 515 is inverted by the inverter 516, and the output of the OR circuit 514 becomes "1". Therefore, at this time, the AND circuit 491
Octave codes B1 to B3 and key-on signals KO1 and KO1' of channel "3" (FIG. 6) given to channels 494 are output as data KC1 to KC4 as shown in FIG. 25. At the next time slot "4", the output of delay flip-flop 515 becomes "1" and the output of OR circuit 514 becomes "0". Therefore, note code N of channel "3" delayed by one bit time by delay flip-flops 521-524.
1 to N4 are the data KC as shown in FIG.
Output as 1 to KC4. At this time, AND circuits 491-494 do not operate, so octave codes B1-B3 of channel "4" and key-on signal KO1 are blocked. In this way, the outputs of the OR circuit 514 and the delay flip-flop 515 become "1" alternately, and every other channel, the octave codes B1 to B3 and the key-on signal KO1 (KO1) of the same channel are output.
1') and note codes N1 to N4 are selected in order and output as data KC1 to KC4. Since the channel time of 11 (odd number) cycles twice during one key time, "1", "3",
Octave codes B1 to B3 of odd channels of "5", "7", "9", "11", key-on signal KO
1 (KO1'), note codes N1 to N4 are selected, and in the second half even channels "2", "4",
“6”, “8”, “10” octave chords etc. B1~
B3, KO1, and N1 to N4 are selected. Therefore, as shown in FIG. 25, the key codes for each channel are N1 to N4, B1 to B3, KO1, KO.
1' is multiplexed as data KC1 to KC4.
In addition, in Fig. 25, key codes N1 to N4, B1
~B3, KO1, KO1' are partially omitted, but like the others, B1~ is displayed in the first time slot.
B3 and KO1 (or KO1') are sent out, and N1 to N4 are sent out in the next time slot. Demodulation of multiplexed data and musical tone generation Detailed examples of the demodulation circuit 50, timing signal generation section 52, and musical tone control circuit 53 in FIG.
This is shown in Figure 6. In FIG. 26, data KC1 to KC4 supplied from the multiplexing circuit 28 of FIG. added to. The latch circuit 530 includes note codes N1 to N4, octave codes B1 to B3, and key-on signals KO1,
It is for latching KO1' and has 8 latching positions corresponding to each. Also, data
KC1, KC2, and KC3 are also input to latch circuit 532. This latch circuit 532 has a signal NG,
This is for latching ABC, 4.5M. In addition, in the demodulation circuit 50, data KC1 to KC4
All bits of are input to AND circuit 529. When all data KC1 to KC4 become "1" in time slot "1" shown in FIG. 25, the output of the AND circuit 529 becomes "1". The output "1" of the AND circuit 529 is supplied to the OR circuit 534 and delay flip-flop 533 of the timing signal generating section 52 as a reference pulse SY indicating time slot "1". The output of the OR circuit 534 is applied to a delay flip-flop 535, and the output of the flip-flop 535 is applied to an inverter 536.
is inverted and returned to the OR circuit 534. Therefore, similar to the OR circuit 514 and the delay flip-flop 515 in the multiplexing circuit 28 of FIG. 9, the OR circuit 534 and the delay flip-flop 5
35 outputs "1" alternately every 1 bit time. The output of the OR circuit 534 is the AND circuit 5
37, the outputs of the delay flip-flops 535 are input to AND circuits 538, respectively. A clock pulse φ ₂ (one of the two-phase system clock pulse φ as shown in FIG. 3) that rises in the first half of one bit time is applied to the other inputs of AND circuits 537 and 538. Therefore, the clock pulses φ output from AND circuits 537 and 538, respectively.
_A ' and _φB ' occur as shown in FIG. Second
Figure 7 shows the time slots "1" to "22" of data KC1 to KC4 (see Figure 25) and the reference pulse SY.
is also shown. A reference pulse is output from delay flip-flop 533.
Pulse S2 is obtained by delaying SY by one bit time. This pulse S2 corresponds to time slot "2" of data KC1 to KC4. This pulse S2 is input to an AND circuit 539. The clock pulse φ _B ' outputted from the AND circuit 538 is input to the other input of the AND circuit 539. Therefore, the output of the AND circuit 539 becomes "1" in the first half of time slot "2", and the output of the latch circuit 532 becomes "1".
is added to the control input (L) of This causes the normal gate signal NG, automatic base code mode signal ABC, and scan cycle pulse to be sent as data KC1 to KC3 in time slot "2".
4.5M are latched into latch circuits 532, respectively. The clock pulse φ _B ' output from the AND circuit 538 is supplied to the control input L of the latch circuit 530. Therefore, the latch circuit 530 takes in and latches input data every even numbered time slots "2", "4", "6", . . . "22". Furthermore, the data to be latched at time slot "2" (NG, ABC,
4.5M, etc.) is meaningless data for the latch circuit 530, and will be erased at the next latch timing (time slot "4") without being used at all. 6"
...By latching every "22", the note codes N1 to N4 sent out at that time as data KC1 to KC4 and the delay flip-flop group 5
The octave codes B1 to B3 of the same channel one time slot before and the key-on signals KO1 and KO1' delayed by 31 are simultaneously latched in the latch circuit 530. Latch circuit 5 every 2 bit times
Since the contents of the 30 latches are rewritten, the time width of the data N1-N4, B1-B3, KO1, KO1' of the same channel output from the latch circuit 530 is 2 bit times. Data N1 to N4, B1 to B3, output from the latch circuit 530,
Channels of KO1 and KO1' are shown at 530 in Figure 27.
Shown below. The note codes N1 to N4 and octave codes B1 to B3 output from the latch circuit 530 are the second
Frequency division ratio ROM (abbreviation for read-only memory) 540 and decoder 541 in the musical tone generation circuit 51 shown in FIG.
is supplied to The frequency division ratio ROM 540 stores in advance frequency division ratio data for obtaining a predetermined pitch frequency corresponding to each of the 12 note names C to C#, and the latch circuit 530 (FIG. 26) Outputs predetermined frequency division ratio data (note frequency division ratio data NFD) corresponding to the note names indicated by the note codes N1 to N4 supplied from the controller. The decoder 541 receives a frequency division ratio of 2 ⁿ in octave units supplied from the latch circuit 530.
Obtain octave frequency division ratio data OFD indicating the frequency division ratio. The note frequency division ratio data NFD and the octave frequency division ratio data OFD output from the frequency division ratio ROM 540 and the decoder 541 are sent to the latch circuit 54, respectively.
2 is input. Control input L of latch circuit 542
is given a clock pulse φ _A ' (see FIG. 27) outputted from AND circuit 537 in FIG. Therefore, the channels of the note frequency division ratio data and the octave frequency division ratio data output from the latch circuit 542 are as shown in FIG. In the timing signal generating section 52 of FIG. 26, the signal "1" output from the delay flip-flop 533 when the time slot is "2" is input to the latch circuit 543. A clock pulse φ _B ' is applied to the latch control input L of the latch circuit 543, and the "1" taken in at time slot "2" is transferred to just before time slot "4", that is, between time slot "2" and " It is held and output for a 2-bit time of "3". The output of latch circuit 543 is delayed by two bit times in delay flip-flop 544. Output FB of the flip-flop 544
0 is time slot "4" as shown in Figure 27.
and "5" becomes "1". This delay flip-flop 544 is connected to AND circuits 537 and 538.
The output state is set at the timing of the clock pulse φ _{B '} based on the input signal taken in at the timing of the clock pulse φ _{A '} .
Therefore, a two-bit time delay corresponding to the period of clock pulses φ _A ' and φ _B ' is performed. The output FB0 of delay flip-flop 544 is
The signals are input to a 10-stage/1-bit shift register 545, and are sequentially delayed by 2 bit times in accordance with two-phase clock pulses φ _A ' and φ _B '. From each stage of the shift register 545, pulses FB1 to FB1 with a 2-bit time width are output as shown in FIG.
0's are generated sequentially. These pulses FB1
-FB10 is supplied to the musical tone generation circuit 51 shown in FIG. 28, and is used to distribute the frequency division ratio data supplied from the latch circuit 542 in a time-divisional manner as shown in FIG. 27 to each channel. In FIG. 28, the musical tone generation circuit 51 includes ten musical tone generation sequences ch1 to ch10 corresponding to the time-sharing channels "2" to "11" formed by the sound generation allocation circuit 18, respectively. The musical sound generation series ch1, ch2, ch3, ch4, ch5, ch6 are time-divisionally formed channels "3", "5",
These correspond to "7", "9", "11", and "2", respectively, and in automatic bass chord mode (ABC is "1"), these correspond to lower key range channel L, arpeggio channel channel A, and bass They respectively correspond to the channel P (that is, the sound generation channel group for the second musical tone generation mode) (see FIGS. 6 and 25). The musical tone generation series ch7, ch8, ch9, ch10 are time-divisionally formed channels "4", "6",
These correspond to "8" and "10", respectively, and correspond to the upper key range channel U (that is, the sound generation channel group for the first tone generation mode) (see FIGS. 6 and 25). Of course, in normal mode (ABC is “0”), all musical tone generation sequences
CH1 to CH10 are switched to the upper key range channel U, that is, the channel group for the first tone generation mode. (See Figure 6). Details are shown only for musical sound generation series ch1, ch6 and ch7, but ch2~ for the lower key range channel
ch4 and ch5 for arpeggio channel channel are ch1
It has the same configuration as , and also has a
ch8 to ch10 have the same configuration as ch7. The musical tone generation sequence ch6 for the bass channel is almost the same as the musical tone generation sequence ch1 for the lower key range channel, but the number of feet of the signal extracted as the bass sound source is different from the lower key range tones (chords). There is. Each musical tone generation series ch1 to ch10 includes latch circuits 546, 547, 548..., variable frequency divider 54
9, 550, 551, ..., 3-stage 1/2 frequency divider 55
2, 553, 554, etc., respectively. Latch circuits 546, 547 for each series ch1 to ch10,
Frequency division ratio data (NFD, OFD) output from the latch circuit 542 in a time-division manner is input to 548, . . . . AND circuit 55 for each series ch1 to ch10
5, 556, 557, ... are pulses FB1 output from the shift register 545 (Fig. 26).
.about.FB10 are supplied separately, and a clock pulse _φB ' (FIG. 27) is inputted in common. The output of each AND circuit 555, 556, 557, . . . is applied to a latch control input L of a latch circuit 546, 547, 548, . Therefore, in musical tone generation series ch1, the condition of AND circuit 555 is satisfied when pulse FB1 and clock pulse φ _B ' become "1", and at that time, the time division channel "3" output from latch circuit 542 is satisfied. The frequency division ratio data of the latch circuit 546
(See Figure 27). Similarly below,
In series ch2, the division ratio data of time division channel "5" is latched, and in ch3, "7",
4 is "9", ch5 is "11" (i.e. arpeggio channel A), ch6 is "2" (i.e. bass channel P), ch7, ch8, ch9, ch1
At 0, the frequency division ratio data of "4", "6", "8", and "10" (ie, upper key range channel U) are latched, respectively. In this way, the time-division frequency division ratio data based on the key codes N1-B3 of each time-division channel is distributed to the predetermined tone generation series ch1-ch10 corresponding to each time-division channel and converted into DC. The variable frequency dividers 549, 550, 551, . . . divide the sound source clock pulse φ _jk by a frequency division ratio corresponding to the frequency division ratio data supplied from the latch circuits 546, 547, 548, . A 2-foot system 2' sound source signal corresponding to the pitch of the sound being played is output. The sound source clock pulse φ _jk is generated from the sound source master clock oscillator 558. The frequency of this sound source clock pulse φ _jk can be changed periodically according to the vibrato frequency from the vibrato signal generator 559. The 2-foot sound source signal 2' output from the variable frequency dividers 549, 550, 551, etc. is 1/2 of the 3-stage sound source signal 2'
Frequency dividers 552, 553, 554, etc. sequentially 1/
The frequency is divided by two. Therefore, the frequency dividers 552, 553,
From each stage of 554, 4 feet system 4' and 8
Sound source signals of foot system 8' and 16 feet system 16' are obtained, respectively. Musical sound generation series ch7 to ch1 dedicated to the upper key range channel (dedicated to the first musical sound generation mode)
At 0, the sound source signals of each foot system 2', 4', 8', 16' are controlled to open and close by the switching circuit 560, and so on.
Melody sound source signal line M for each foot system
2', M4', M8', and M16', respectively.
Musical sound generation series channels with different musical sound generation modes
For 1 to ch6, each foot system 2', 4', 8', 1
The sound source signal 6' is sent to the opening/closing circuit 56 through gate sections 561, 562, etc. consisting of four AND circuits.
3, 564,... After being controlled to open and close,
Melody sound source signal line M for each foot system
2', M4', M8', and M16', respectively.
The gate sections 561, 562... are the musical tone control circuit 53
(Fig. 26), as described later, when the automatic base code mode signal ABC is "0", that is, in the normal mode, conduction occurs, and each feed system 2' to 1
6' sound source signal is led to opening/closing circuits 563, 564, . . . In this case, the musical sound generation series ch1 to ch6 are used to generate upper key range channel sounds, that is, melody sounds, and the sound source signals are applied to the melody sound source signal lines M2' to M16'. In the automatic base chord mode (ABC〓 is "1"), the gate sections 561, 562, etc. are inactivated by a signal obtained by inverting the signal ABC〓, and the sound source signals 2' to 16' of each foot system are blocked. Series ch1 to ch1 on melody sound source signal lines M2' to M16'
No sound source signal from 6 is given. Instead, the AND circuits 565, 566, . . . of the series channels ch1 to ch6 become operable due to the automatic base code mode signal ABC which is set to "1". Series ch1
~ch5 (lower key range channel L and arpeggio channel A) AND circuit 565, ... other inputs are synthesized by AND circuit 567... signal is added. By combining the 2-foot system and the 4-foot system, the sound source signal of the 4-foot system frequency (although the waveform is different from that of the frequency divider output) is transmitted to each system channel 1 ~
It is output from the AND circuit 567 of ch5 and input to the opening/closing circuit 563 via the AND circuit 565. The other input of the AND circuit 566 of series ch6 (base channel P) is a 4-foot system 4'.
A signal obtained by combining the frequency divider output signal of the 8-foot system 8' with the AND circuit 568 is added. As a result, a sound source signal with an 8-foot frequency (the waveform is different from that output from the frequency divider) is output from the AND circuit 566 and input to the switching circuit 564. series
In ch1 to ch4 (lower key area channel L),
The 4-foot sound source signals output from the AND circuits 565 through the opening/closing circuits 563 are supplied to the chord sound source signal line C4'. In series ch5 (arpeggio channel channel A), a 4-foot sound source signal output in the automatic base chord mode (ABC = "1") is supplied to the arpeggio sound source signal line A4'. In the series ch6 (base channel P), the 8-foot sound source signal outputted from the AND circuit 566 via the opening/closing circuit 564 is supplied to the base sound source signal line P8'. The music control circuit 53 in FIG. 26 is a circuit that reproduces the automatic bass chord mode signal ABC and the mode switching pulse ΔABC based on the automatic bass chord mode signal ABC and the scanning cycle pulse 4.5M given from the latch circuit 532. Contains. FIG. 29 shows an example of the scan cycle pulse 4.5M output from the latch circuit 532 and the automatic base code mode signal ABC. Since the latch circuit 532 performs latch control at the timing of time slot "2" (Fig. 27) of data KC1 to KC4, the output pulse 4.5M or
The rising and falling edges of ABC are synchronized with the timing of time slot "2", that is, pulse FB10 (FIG. 27). scan cycle pulse
As already mentioned, the pulse width of 4.5M is one key time, and the period is 4.5ms. Pulse FB0~
The repetition period of FB 10 is 22 bit times, or one key time. Therefore, the pulse 4.5M output from the latch circuit 532 rises to "1" at the timing of pulse FB10, and falls to "0" at the same timing of pulse FB10 one key time later. The signal ABC output from the latch circuit 532 is transferred to the delay flip-flop 569 and the exclusive OR circuit 5.
70 is input. delay flip-flop 569
takes in an input signal at the timing of pulse FB6 (FIG. 27), and produces an output corresponding to the previous input signal at the timing of pulse FB0 (FIG. 27). Therefore, when the output signal ABC of the latch circuit 532 rises to "1" at the timing of the pulse FB10, the output signal ABC' of the delay flip-flop 569 is output for approximately 1 key time (to be exact, 24 bit times) as shown in FIG. ) After a delay, it rises to “1” at the timing of pulse FB0. Exclusive OR circuit 57
The output ABC' of the delay flip-flop 569 is added to the other input of 0, and its output △
ABC'' is a latch circuit 532 as shown in FIG.
Approximately 1 key time immediately after the rise and fall of the signal ABC output from the
It becomes “1” during the 24-bit time from FB0 to the next FB0. In other words, when this signal △ABC'' is "1", it means that the mode has changed from normal mode to automatic base code mode or vice versa.This mode change detection signal △
ABC'' resets the counter 571 and sets the flip-flop 572. The set output Q of the flip-flop 572 is output as a mode switching pulse ΔABC. cycle pulse
4.5M is input via AND circuit 573.
The counter 571 takes in the signal applied to the count input T at the timing of pulse FB0, and outputs a count value corresponding to the signal ("1" or "0") taken in at the timing of FB6. When seven pulses of 4.5M are generated after the counter 571 is reset by the signal △ABC'', the outputs Q1 to Q3 of the counter 571 become "111" and the AND circuit 574
The output of becomes "1". The flip-flop 572 is reset by the output "1" of the AND circuit 574. Therefore, the mode switching pulse △ABC〓 outputted from the flip-flop 572 is approximately as shown in FIG.
It becomes “1” for 31.5ms (7 cycles of 4.5M pulses). When the output of the AND circuit 574 becomes "1", the output of the inverter 575 becomes "0", and the pulse
4.5M is blocked by the AND circuit 573, and no further counting is performed. Also, the output of the AND circuit 574 is the output of the AND circuit 5
Joins 76 and 577. The other input of the AND circuit 577 receives a signal from the delay flip-flop 569.
ABC' is applied to the AND circuit 576.
A signal obtained by inverting ABC' is given. Further, the outputs of AND circuits 576 and 577 are input to NOR circuits 578 and 579, respectively, forming a flip-flop. Therefore, the automatic base code mode signal ABC output from the NOR circuit 578 is the second
As shown in FIG. 9, the signal ABC rises approximately 31.5 ms after the signal ABC rises, and falls approximately 31.5 ms after the signal ABC falls. The key-on signals KO1 and KO1' latched by the latch circuit 530 of the demodulation circuit 50 are transmitted to the latch circuit 58.
It is input to 0. A clock pulse φ _A ' (FIG. 27) is input to the latch control input L of the latch circuit 580. This latch circuit 580 sets the channel timing of the key-on signal KO1 to the channel timing (27th
(See output channel 542 in the figure). The key-on signal KO1, which is time-divisionally outputted from the latch circuit 580 at the same timing as the output channel timing of the latch circuit 542, is input to the AND circuits 581, 582, and 583 of the key-on rising pulse generation circuit 54, and is also input to the AND circuit 584. is input. If some tone is selected in the tone selection circuit 585, the AND circuit 58
The output of the inverter 586 that is added to the other inputs of the latch circuit 580 is always "1", and normally the key-on signal KO1 output from the latch circuit 580 is input to the AND circuit 5.
Pass through 84. In the key-on rising pulse generation circuit 54,
2-bit adder 587 and two 11 stages/1
Bit shift registers 588 and 589 constitute a counter that can perform time-division counting operations. The shift registers 588 and 589 are shift-controlled by two-phase clock pulses φ _B ' and φ _A ' with a 2-bit time period output from the AND circuits 538 and 537, and are input to each stage at the timing of the pulse φ _B '. Take in the signal and pulse φ
Set the output state of each stage at the timing of _A ′. The outputs of shift registers 588 and 589 are input to adder 587 and added to the signal provided to adder 587 from AND circuit 590. The output of adder 587 is input to shift registers 588 and 589 via AND circuits 582 and 583. The AND circuit 590 receives the scan cycle pulse 4.5M from the latch circuit 532 and the output of the NAND circuit 591. nand circuit 591
The outputs of the shift registers 588 and 589 are input to the input terminals. At the timing of the channel where the key is not pressed, the latch circuit 580 to the AND circuits 582 and 5
The _key -on signal KO1 applied to the shift register 83 is _" 0", and the shift register 588, The signal output from the NAND circuit 589 is "00" and the output from the NAND circuit 591 is "1". The channel timing of the outputs of shift registers 588 and 589 is the same as the output channel timing of latch circuit 542 shown in FIG. Due to the output "1" of the NAND circuit 591, the AND circuit 590 passes the scan cycle pulse 4.5M and adds it to the adder 587, but the key-on signal
As long as KO1 is "0", the output of adder 587 is blocked by AND circuits 582 and 583 and is not provided to registers 588 and 589. When a key is newly pressed and the sound associated with the key is assigned to a certain channel, the key-on signal KO1 becomes "1" at the timing of that channel. When the key-on signal KO1 becomes "1", the AND circuits 582 and 583 become operational at the channel timing, and counting of 4.5M scan cycle pulses is started. When three scan cycle pulses of 4.5M are generated counting from when the key-on signal KO1 of a certain channel rises to "1", the outputs of shift registers 588 and 589 both become "1" at the timing of that channel, The output of the NAND circuit 591 becomes "0".
As a result, counting of 4.5M pulses is stopped for that channel timing, and from then on, as long as the key-on signal KO1 of that channel is generated, the count value "11" is shifted to the shift registers 588 and 58.
Hold the cycle at 9. The output of the NAND circuit 591 is input to the AND circuit 581. The output of the NOR circuit 592, which is added to the other inputs of the AND circuit 581, is normally "1". Therefore, if you extract only one channel,
As shown in FIG. 29, the time from when the key-on signal KO1 of that channel rises to "1" (the key is pressed) until the output of the NAND circuit 591 falls to "0" is 9 ms (2 x 4.5 ms). ) to 13.5ms (3
×4.5ms), the output of the AND circuit 581 is “1”
becomes. The output "1" of the AND circuit 581 is used as a key-on rising pulse KO2 to form a percussive envelope. This key-on rising pulse KO2 is generated in a time-division manner for each channel for about 9 ms to 13.5 ms from the rising edge of the key-on signal KO1 of each channel. The channel timing of this key-on rising pulse KO2 is the same as the key-on signal KO1 output from the latch circuit 580.
This corresponds to the output channel timing in Figure). The pulse FB0 output from the delay flip-flop 544 of the timing signal generator 52 is applied to the set input S of the flip-flop 593, and the pulse FB6 output from the shift register 545 is applied to the set input S of the flip-flop 593.
is applied to the reset input R of flip-flop 593. This flip-flop 593 is controlled by clock pulses φ _A ' and φ _B '. pulse
When FB0 is generated, “1” is taken into the set input S at the timing of the pulse φ _A ′, and the output Q is set to the set state (“1”) at the timing of the next pulse φ _B ′. . Furthermore, when pulse FB6 is generated, "1" is taken into reset input R at the timing of pulse _φA ', and the next pulse pulse φ
Output Q is in reset state (“0”) at timing _B ’.
is set to Therefore, the output signal LAPch of the flip-flop 593 is a pulse as shown in FIG.
It becomes "1" from FB1 to FB6. this signal
During the period when LAPch is "1", the musical tone generation series ch1 to ch6, that is, the series used for the second musical tone generation mode (lower key range channel L, arpeggio channel A, bass channel P), is The timing to latch the divided data, in other words, the key-on signal from the AND circuit 584
The above channels L, A, P as the key-on rising pulse KO2 from KO1 and AND circuit 581.
Time division channels "3", "5", corresponding to
This is when data "7", "9", "11", and "2" appear (see output channel 542 in FIG. 27). The tone color selection circuit 585 can select, for example, the following tone colors corresponding to the upper key range (melody), lower key range (chord), arpeggio, and bass. Upper keyboard range (melody): piano, harpsichord, organ, strings, plus. Lower key range (chords) and arpeggios...piano, guitar bass...string bass Multiple preset buttons (not shown) are provided for tone selection, and by pressing the desired preset button, A timbre selection signal TC is generated using a predetermined combination of the timbres. For example, if you press one preset button,
A tone selection signal TC is generated which selects "piano" as the upper key range melody tone, "piano" as the lower key range (chord) and arpeggio tone, and "string bass" as the bass tone. Furthermore, in the tone selection circuit 585, if a percussive envelope tone (for example, piano) is selected as the upper key range (melody) tone,
Generates upper key range percussive signal U.PERC. Furthermore, if the tone selection switch (preset button) is not operated at all, a tone selection off signal TSOF is generated. Tone select off signal
TSOF becomes "1" when no tone is selected, and is inverted by inverter 586 to disable AND circuit 584, and is inverted by NOR circuit 592 to disable AND circuit 581. Therefore, when no tone is selected, generation of the key-on signal KO1 and the key-on rising pulse KO2 is prohibited. In the musical tone control circuit 53, the key-on signal KO1 output from the AND circuit 584 and the AND circuit 58
Key-on rising pulse KO2 output from 1,
Signal output from flip-flop 593
It includes logic for generating an attack signal AT and a decay signal DC based on LAPch, a normal gate signal NG given from a latch circuit 532, and an upper key range percussive signal U.PERC. The attack signal AT and decay signal DC are as shown in Table 10 below.
1, the key-on rising pulse KO2, or its inverted signals 1 and 2 are selected.

[Table] In Table 10, "U" indicates the upper key range channel. "U.PERC" is the upper key range percussive signal U.
Indicates when PERC occurs. "L, A, P" indicates the lower key range channel, the arpeggi top channel, and the bass channel. "NG" indicates when the normal gate signal NG is generated. When the key-on rising pulse KO2 is used as the attack signal AT, the amplitude envelope of the musical tone becomes percussive. In automatic bass chord mode, the noise circuit 57
8 to the AND circuit 594 is "1", and the signal is output in accordance with the timing of the lower key range channel L, the arpeggio left channel A, and the bass channel P.
When LAPch becomes "1", the output of the AND circuit 594 becomes "1". The output “1” of this AND circuit 594 is sent to the AND circuit 5 through an OR circuit 595.
Added to 96. A key-on rising pulse KO2 is applied to the other input of the AND circuit 596 via an OR circuit 597. Therefore, at the timing of the lower key area channel L, the arpeggio channel A, and the bass channel P, the key-on rising pulse
KO2 is selected by AND circuit 596 and output as attack signal AT via OR circuit 598. At this time, the output of the OR circuit 595 is "1".
A signal "0" obtained by inverting the key-on signal KO1 by the inverter 600 is applied to the AND circuit 599, so that the key-on signal KO1 is not selected. Further, at the timing of channels L, A, and P, the output “1” of the AND circuit 594 is inverted by the inverter 601, and “0” is added to the NOR circuit 602. Therefore, the output of the NOR circuit 602 is determined by the state of the key-on rising pulse KO2 applied to the other inputs. While the key-on rising pulse KO2 is “1”, the NOR circuit 602
The output of is “0”, but the pulse KO2 is “0”
Then, the output of the NOR circuit 602 becomes "1",
Decay signal DC is generated via OR circuit 603. When the auto rhythm stops in automatic bass chord mode and a normal gate signal NG is generated, the AND circuit 60 is activated at the timing of the signal LAPch.
Condition 4 is satisfied, and the key-on signal KO1 is applied from the AND circuit 604 to the OR circuit 597.
The output of the OR circuit 597 is the key-on rising pulse
KO2 and key-on signal KO1 are superimposed, and pulse KO2 is effectively replaced by KO1. Therefore, AND circuit 596 and NOR circuit 6
02 operates based on the key-on signal KO1,
Also at the timing of channels L, A, and P, an attack signal AT corresponding to the key-on signal KO1 and a decay signal DC corresponding to its inverted signal KO1 are obtained. At the timing of the upper key range channel (that is, the timing of all channels in the normal mode or the timing of a predetermined part of channels in the automatic base chord mode), the output of the AND circuit 594 is "0". this is a signal
This is because ABC〓 or the signal LAPch becomes "0". Therefore, the output of inverter 600 becomes "1", and AND circuit 599 becomes operable. As a result, the key-on signal KO1 is selected by the AND circuit 599 and outputted as the attack signal AT via the OR circuit 598. At this time,
Since the output of the OR circuit 595 is "0", the key-on rising pulse KO2 is not selected by the AND circuit 596. Also, the output of the AND circuit 594 is “0”
As a result, the output of the inverter 601 becomes "1", and the output of the NOR circuit 602 is fixed to "0". Therefore, the decay signal DC corresponding to the inversion 2 of the key-on rising pulse KO2 is not generated. When the key-on signal KO1 falls to "0", the output of the inverter 605 becomes "1", and the OR circuit 6
Inversion 1 of the key-on signal KO1 via 03
A decay signal DC corresponding to is generated. When the upper key range percussive signal U.PERC is "1", the output of the OR circuit 595 is always "1",
Also at the timing of the upper key range channel, the key-on rising pulse KO2 is generated via the AND circuit 596.
is selected as the attack signal AT. On the other hand, in the upper key range channel timing, the AND circuit 594
Since the output of is always “0”, the inverted signal 2 of the key-on rising pulse KO2 is sent to the NOR circuit 602.
Not generated from Therefore, the inverted signal 1 of the key-on signal KO1 is used as the decay signal DC. Key-on signal KO1 and key-on rising pulse
At the same channel timing as KO2, that is, at the same channel timing as the division ratio data output from the latch circuit 542 (FIG. 28), the attack signal AT and decay signal DC, which are generated in a time-division manner, are connected to each tone generation series ch1. ~ch10 (28th
latch circuits 606, 607, 608, . . .
is supplied to The latch control inputs L of the latch circuits 606, 607, 608, .
. . . Similarly, the outputs of the AND circuits which input the pulses FB1 to FB10 corresponding to the respective series ch1 to ch10 and the clock pulse φB' are provided. Therefore, similarly to the latch circuits 546, 547, 548..., the latch circuits 60 of each series ch1 to ch10
6, 607, 608... are the attack signals AT supplied at the corresponding channel timings.
and Decay signal DC are latched. In this way, the attack signal AT and decay signal DC of each channel are distributed to predetermined series ch1 to ch10, and converted into direct current in the latch circuits 606, 607, 608, . . . . The DC-converted attack signal AT' and decay signal DC' latched in the latch circuits 606, 607, 608... are sent to the envelope generating circuits 609, 6
10, 611... Series ch1~ch
Envelope generation circuit 609 used in 6, 6
10... An example is shown in Figure 30a, and the series ch7
~Envelope generation circuit 6 used in ch10
An example of 11... is shown in FIG. 30b. In Fig. 30a or b, when the attack signal AT' is "1", the capacitor Ce or Ce' is connected to the attack resistor R1.
or R1' and transistor Tr1 or Tr1'
charged via. Decay signal DC′ is “1”
, the capacitor is connected via the decay resistor R2 or R2' and the transistor Tr2 or Tr2'.
Ce or Ce′ is charged. The charging/discharging waveform of the capacitor Ce or Ce' is supplied to the switching circuits 563, 564, 560, . . . as an envelope control signal. Note that a discharge circuit including a resistor R3 or R3' is provided in parallel with the capacitor Ce or Ce'. This is to discharge slowly through the resistor R3 or R3' when the decay signal DC' does not rise to "1" immediately after the attack signal AT' falls to "0". It is a circuit. For example, this applies when the upper key range percussive signal U.PERC is generated (see Table 10 above). Incidentally, the combined value of all the decay resistances R2 of the envelope generating circuits of the series ch1 to ch6 (Fig. 30a) is the decay resistance R2' of the series ch7 to ch10.
(It is larger than the value in FIG. 30b. The automatic base code mode signal ABC outputted from the NOR circuit 578 in FIG. 26 is supplied to the envelope generation circuits 609, 610, . When this signal ABC〓 is "1", the transistors of the envelope generation circuits 609, 610...
Tr3 (Figure 30a) is turned off and the decay resistance R2 is set to its maximum value. That is, in the case of the automatic bass chord mode, the inverted signal 2 of the short pulse KO2 becomes the decay signal DC', so that the discharge state occurs immediately after the start of sound generation. Therefore, the discharge time is increased to obtain a percussive envelope waveform that decays slowly. When the signal ABC〓 is “0”, the transistor
Tr3 turns on and the value of Decay resistance R2 becomes series.
The value is set to be the same as the value of the decay resistance R2' of ch7 to ch10. This means that when the signal ABC〓 is “0”, that is, in normal mode, series ch1
This is because ch6 is used as an upper key range channel like ch7 to ch10. The mode switching pulse △ABC〓 output from the flip-flop 572 in FIG.
6 envelope generating circuits 609, 610, . . . When this mode switching pulse △ABC〓 occurs, the envelope generation circuits 609 and 61
0...The transistor Tr4 in FIG. 30a is turned on, and the value of the decay resistance R2 becomes the smallest. This mode switching pulse △ABC〓 is also input to the AND circuit 612 in FIG. Series ch1 in which the tone generation mode is switched to or vice versa
~Channel “3”, “5” corresponding to ch6,
At timings "7", "9", "11", and "2", the output of the AND circuit 612 becomes "1".
The output “1” of this AND circuit 612 is the OR circuit 6
03 and is output as a decay signal DC. Therefore, when the mode switching pulse △ABC〓 is generated, the transistor Tr4 of the envelope generating circuits 609, 610, etc. of series ch1 to ch6
(Fig. 30a) is turned on, and the corresponding series ch1~
The decay signal DC is forcibly applied to ch6, and the decay transistor Tr2 is turned on. As a result, the capacitor Ce is rapidly discharged, and the musical tones that have been produced in the series ch1 to ch6 are rapidly erased. Furthermore, on the side of the sound generation assignment circuit 18 (FIG. 1), the mode switching control circuit 15 also
(Figure 4) Mode switching pulse generated from △
Off-channel timing signal by ABC
OFchT is connected to the timing signal generation circuit 20 (20th
The channel timings "3", "5", "7", which occur from the diagram) and correspond to the above series ch1 to ch6,
Memory (key-on signal) of key-on memory 178 (Fig.
I try to clear KO1). but,
Only clearing the key-on signal KO1 (that is, only generating the decay signal DC in conjunction with it) does not necessarily eliminate the sound immediately due to the decay resistance R2. Therefore, by using the mode switching pulse ΔABC to reduce the decay resistance R2 and causing rapid discharge, the sound is immediately muted when the mode is switched. This two-stage processing (signal OFchT and envelope rapid discharge) makes it possible to reliably perform temporary mute control of the sound generation channel whose musical sound generation mode is switched when switching modes. To reliably prevent strange sounds from occurring at times. On the other hand, in FIG. 26, the mode switching pulse △
ABC〓 is also input to the NOR circuit 592 of the key-on rising pulse generating circuit 54. Due to the generation of the mode switching pulse △ABC〓, the output of the NOR circuit 592 becomes "0", making the AND circuit 581 inoperable. As a result, the mode switching pulse △ABC〓
The generation of the key-on rising pulse KO2 is prohibited for approximately 31.5ms during which the key-on rising pulse KO2 is generated. This is to prevent the following inconvenience from occurring. For example, assume that the normal mode is switched to the automatic bass chord mode while a key is being pressed in the upper key range (the upper key range that is not changed to the lower key range).
If the upper key range tone being pressed has been previously assigned to a channel (for example, channel "3") that should be changed to the lower key range channel, the off-channel timing signal OFchT generated by mode switching will (By clearing the key-on signal KO1, it is forcibly treated as a key release.) However, in reality, the key continues to be pressed in the upper key range, so the key press sound is Channels “4” and “6” dedicated to the upper key range,
It will be newly reassigned to either "8" or "10". Due to this new assignment, the key-on signal KO1 rises to "1" in the new assigned channel even though the key press continues, and the key-on rising pulse generation circuit 54 (FIG. 26) generates a key-on rising signal. Pulse KO2 is generated. In this case, if a percussive tone (for example, piano) is selected as the tone in the upper keyboard range,
Signal U.PERC generated from tone selection circuit 585
Key-on signal of upper key range channel based on
KO2 is selected as the attack signal AT. Therefore, in the above case, even though the key continues to be pressed in the upper key range, the attack signal AT is 2 in response to the key-on rising pulse KO2 before mode switching (in normal mode) and immediately after mode switching.
Occurs frequently. If left as is, there will be the inconvenience that the bark-cussive envelope sound will be generated twice (on different channels) even though the key is pressed only once. Therefore, the key-on rising pulse KO2 (particularly the key-on rising pulse KO2 of the upper key range channel, which is generated immediately after mode switching by the mode switching pulse △ABC), because the lower key range channel etc.
(cleared by OFchT, key-on signal KO1 is not generated, and therefore pulse KO2 is not generated), and the attack signal AT is not generated based on the second key-on rising pulse KO2. . Considering the above points, the generation time width of the mode switching pulse △ABC〓 (or △ABC) is
Set the time longer than the sum of the time required for reallocation processing, that is, the time required for one key scanning cycle, 4.5 ms, and the time width of 9 ms to 13.5 ms of the key-on rising pulse KO2, for example, 31.5 ms, so that the pulse generated at the time of mode switching is set to 31.5 ms. The false key-on rising pulse KO2 can be reliably removed. The sound source signals generated from each musical sound generation series ch1 to ch10 are on lines M2' to M16', C4', and A.
4' and P8' to the tone forming circuit 613. In the timbre forming circuit 613, the timbre selection circuit 585
Based on the tone selection signal TC given from (Fig. 26), the melody sound source signal lines M2' to M1 are
Melody tone is applied to the sound source signal of 6', chord tone is applied to the sound source signal of chord sound source signal line C4' and arpeggio sound source signal line A4', and chord tone is applied to the sound source signal of bass sound source signal line P8'. Add a base tone to each. Therefore, series ch
When channels 1 to ch6 are used for the upper key range (melody) (in normal mode), the series
A melody tone is added to the output sound source signals of ch1 to ch6 (signals of M2' to M16'), but when used for an accompanist (in automatic bass chord mode), the output sound source signals of the series ch1 to ch6 are A predetermined accompaniment tone is given to the output sound source signals C4', A4', and P8'. In the above embodiment, an example is shown in which the present invention is applied to a single-keyboard type electronic musical instrument, but the present invention can also be applied to an electronic musical instrument having multiple keyboards.
For example, if the upper keyboard area in the embodiment is replaced with the upper keyboard, and the lower keyboard area is replaced with the lower keyboard, the present invention can be implemented in substantially the same manner as in the embodiment. In addition, in the example,
Performance modes (normal mode and automatic bass chord mode) for how to use multiple musical sound generation channels
However, this point is not the gist of the invention. Further, in the above embodiment, the musical tone signal of the bass tone or chord is generated based on the key data KP or SFKL output from the bass tone key data forming circuit 42 or the SF chord key data forming circuit 43 (FIGS. 1 and 15). A complicated path (pronunciation assignment circuit 18, key information conversion unit 23,
demodulation circuit 50, musical tone generation circuit 51, etc.), however, it is not an essential requirement of the present invention to provide these complicated paths. The pulse generation timing in the bass note key data KP or chord key data SFKL (see KP in Figure 16 or SFKL in Figure 17) is data sufficient to specify the note name of the bass note or chord component note to be generated. Therefore, in short, it is only necessary to generate a musical tone signal having a tone name corresponding to this pulse generation timing. Bass sound key data KP
The configuration for generating musical tone signals based on the chord key data SFKL can be simplified as follows, for example. In other words, there are 12 tone generators dedicated to bass sounds (or chords).
A timing pulse synchronized with each note timing of the 12 note names is generated separately as note name data corresponding to each note name, and base note key data KP (or chord The timing pulse generated at the same timing as the pulse generation timing in key data SFKL) is selected, and the selected timing pulse is distributed to the tone generator corresponding to the note name of the pulse to generate a musical tone signal. It's okay. In addition, when the reference frequency of the pulse input to the shift register 41 (FIG. 15) is other than 1 degree (root note), each stage Q1 to Q12 in the shift register 41 and the tone degree number (1 to The correspondence relationship 7) differs from that of the above embodiment depending on the frequency of the reference. For example, if the standard frequency is 3 major thirds, stage Q1 of the shift register 41 corresponds to minor 3rds ^3b . Along with this, the shift register 41 which should be input to the AND circuits 349 to 354 in the logic circuit 347 of the bass note key data forming circuit 42 or the AND circuits 355, 356, 416 and 417 of the SF chord key data forming circuit 43 The output stage is also different from the above embodiment. By the way, SF chord key data formation circuit 43
In the above embodiment, the data min and 7th specifying the chord type used in (Fig. 15) are generated based on the keys pressed in the key range for specifying the root note, that is, the lower key range. , but not limited to this. For example, a chord type selection switch may be specially provided and the above-mentioned data min and 7th may be generated based on the output of this switch, or a pedal keyboard or the like may be used. The data may be read from a data generating device. As explained above, according to the present invention, the pulses generated at the timing of the note names corresponding to the reference frequency are sequentially shifted, and the output pulses and base pulses corresponding to the timings of the note names of the chord constituent notes are output from an appropriate shift stage. Since the output pulses corresponding to the specified frequency of the pattern signal are respectively extracted and the timing data corresponding to the note name of each chord component note and the note name of the bass note are obtained, the simplified circuit configuration allows This has the excellent effect of making it possible to obtain data on both chord constituent notes and automatic bass notes. In addition, by making the time periods for extracting output pulses from the required stages of the shift register different for chords and bass notes, key data SFKL indicating the note name timing of the chord constituent notes and key data indicating the note name timing of the bass note are created. KP can be generated in different time zones, and this allows the means to convert key data indicating note timing into static note name data to be generated at different times using both chord key data SFKL and bass note key data KP. Another advantage is that it can be divided and shared.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of an electronic musical instrument to which the present invention is applied. FIG. 2 is a circuit diagram showing a detailed example of the timing signal generation circuit in the sound generation allocation circuit in FIG. 1. FIG. 3 is a timing chart showing an example of generation of control signals in the circuit of FIG. 2. FIG. 4 is a circuit diagram showing a detailed example of the mode selection circuit in FIG. 1. FIG. 5 is a timing chart showing an example of the operation shown in FIG. FIG. 6 is a timing chart showing an example of the channel timing signal generated from the circuit of FIG. 2. Figure 7 is the first
FIG. 3 is a circuit diagram showing a detailed example of the key scanning circuit shown in the figure.
FIG. 8 is a timing chart showing an example of timing signals generated from the circuit of FIG. 7 and the time relationships of various processes executed within one scanning cycle under time control by these timing signals. FIG. 9 is a circuit diagram showing a detailed example of the key information conversion section in FIG. 1. FIG. 10 is a circuit diagram showing a detailed example of the sound generation allocation control section and window circuit in FIG. 1. FIG. 11 is a circuit diagram showing a detailed example of the truncate circuit in FIG. 1. FIG. 12 is a circuit diagram showing a detailed example of the chord detection control circuit in FIG. 1. FIG. 13 is a circuit diagram showing a detailed example of the lower key area new key-on detection circuit in FIG. 1. FIG. 14 is a circuit diagram showing a detailed example of the lower key area key-on memory in FIG. 1. FIG. 15 is a circuit diagram showing a detailed example of the automatic base code processing circuit in FIG. 1. 16th
The figure is a timing chart showing an example of the circuit operation of FIG. 15, particularly an example of operation centered on the root tone shift register. FIG. 17 is a timing chart showing an example of processing operation in the single finger mode in the circuit of FIG. 12. FIG. 18 is a circuit diagram showing a detailed example of the arpeggio key data forming circuit in FIG. 1. FIG. 19 is a timing chart showing an operation example until the number of homophone names is counted in the homophone name removal circuit in FIG. 18. FIG. 20 is a timing chart showing an example of the operation of the homophone name removal circuit in FIG. 18 until a key-on signal from which homophone names are removed is obtained. FIG. 21 is a timing chart showing a time relationship in which addition and subtraction can be performed in the key data extraction circuit of FIG. 18. 22 and 23 are timing charts respectively showing an example of the operation of the circuit of FIG. 18 until arpeggio key data is extracted. FIG. 24 is a timing chart showing an example of how chord constituent note key data for arpeggio is generated from the lower key range key data register of FIG. 12. FIG. 25 is a diagram showing an example of the state of multiplexed key codes outputted from the multiplexing circuit of FIG. 9 for each time division time slot. Figure 26 is the first
FIG. 2 is a circuit diagram showing a detailed example of a demodulation circuit, a timing signal generator, and a musical tone control circuit in the figure. FIG. 27 is a timing chart showing an example of output signals from each part in FIG. 26. FIG. 28 is a block diagram showing an example of the musical tone generation circuit in FIG. 1. Figure 29 is the 26th
A timing chart showing an example of re-occurrence of mode switching pulses, etc. and an example of generation of a key-on rising pulse in the circuit shown in the figure. 30a and 30b are circuit diagrams showing detailed examples of the envelope generating circuit in FIG. 28, respectively. 10... Key switch matrix, 11... Key scanning circuit, 18... Sound generation assignment circuit, 23...
Key information conversion unit, 30...Chord detection control circuit, 3
2... SF root note detection priority circuit, 33... SF chord type detection section, 41... Root note shift register, 42...
...Base note key data forming circuit, 43...SF chord key data forming circuit, 46...Pattern generation circuit. KD...Time-division multiplexed key data,
SFRTLD, RTLD...data corresponding to the note timing of the root note, SFKL...single finger chord key data, KP...bass note key data, min, 7th...data specifying the chord type.

Claims (1)

[Claims] 1. Pulse generating means for outputting a pulse at the timing of a desired note name corresponding to a reference frequency among the time division timings assigned to each note name; a shift register in which the interval between stages corresponds to a musical pitch and sequentially shifts the pulses output from the pulse generating means in synchronization with the time division timing; a chord type specifying means for specifying a desired chord type; In accordance with the chord type specified by the chord type specifying means, the output pulses of a plurality of stages of the shift register that have a pitch relationship of the chord with respect to the reference frequency are pulses indicating the note names of chord constituent notes. a first pulse extracting means for extracting the frequency of the bass sound, and a pattern signal indicating the frequency of the bass sound to be generated at the timing at which the bass sound should be generated; a bass sound pattern generating means that corresponds to the difference; and a pitch difference in the frequency of the pattern signal with respect to the reference frequency among the stages of the shift register according to the pattern signal generated by the bass sound pattern generating means; a second pulse extracting means for extracting an output pulse from a stage corresponding to the stage; and a second pulse extracting means for extracting an output pulse from a stage corresponding to the stage; At the same time, the output pulse extraction operation of the required stage of the shift register in the second pulse extraction means is controlled to be executed in a first time period having a time width, and the time division timing of each note name is at least one cycle. a control means for performing control in a second time period having a time width and different from the first time period; and each pulse extracted by the first pulse extraction means in the first time period. A sound that converts each pulse into pitch name data corresponding to its generation timing, and converts the pulse extracted by the second pulse extraction means in the second time period into pitch name data corresponding to its generation timing. generating a plurality of musical tone signals corresponding to each note name data converted by the note name data converting means in the first time period as musical tone signals of chord constituent notes; an automatic accompaniment device for an electronic musical instrument, comprising: musical tone generating means for generating a musical tone signal corresponding to the note name data converted by the note name data converting means as a musical tone signal of the bass tone in the time period of item 2; 2. The musical tone generating means generates a plurality of musical tone signals corresponding to each note name data converted by the note name data converting means in the first time period as musical tone signals of chord constituent notes. and bass tone musical tone forming means for forming a musical tone signal corresponding to the note name data converted by the note name data converting means in the second time period as a musical tone signal of the bass tone. An automatic accompaniment device according to claim 1.