JPS625659A - Hetero junction bipolar transistor and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a heterojunction bipolar transistor with excellent high frequency characteristics.

Prior Art A typical structure of a conventional bipolar transistor is shown in FIG. In the figure, 1 is an n-type silicon substrate, 2 is an n-type collector provided thereon by epitaxial growth, 3 is a p-type base provided by diffusion, 4 is an n-type emitter provided by diffusion or alloying, and 5 is a collector electrode, 6 is a base electrode, and 7 is an emitter electrode.

Although this is an npnl-transistor, a pnp transistor may be used as well. This example uses the same semiconductor material, silicon, to form the emitter, base, and collector.

By the way, it is known that when the emitter is formed using a semiconductor having a higher forbidden band energy than the base, a very high current gain can be obtained.

This is due to the fact that, by choosing materials appropriately, the band structure of the emitter-base junction can be configured so that it does not provide much of a barrier to electrons, but provides a large barrier to holes. A typical example is AJxG on the emitter.
&I XASt, using GaAs for the base and collector.

Furthermore, it is known that such a structure can significantly improve high frequency characteristics. The maximum cutoff frequency FO of a bipolar transistor is Fc=1/(2πRbCc) (1) Rbi
Base resistance Cc: Served as collector capacitance. As mentioned above, if the emitter is formed using a semiconductor with higher forbidden band energy than the base,
By choosing materials appropriately, the band structure of the emitter-base junction can be modified to be less of a barrier to electrons.
It can be configured to provide a large barrier to holes. Therefore, the carrier concentration (hole concentration) of the base can be made very high. Therefore, the base resistance can be made extremely small, and as a result, a very large maximum cutoff frequency Fc can be obtained.

However, obtaining this structure is extremely difficult in terms of process. In particular, when attempting to shorten the base length in order to improve high-frequency characteristics, it becomes difficult to remove the base electrode.

FIG. 5 shows a conventional example (Japanese Patent Publication No. 55-3829) in which the extraction of the base electrode is improved. In the figure, 8 is n
type GaAs substrate, 9 is an n-type Gaλg forming the collector.
, 10 forms the base p-type Ga 5111 forms the emitter n Saint 1 x Ga 1x A S
112 is the base electrode extraction p saint ExGa1
-xASl 13 is a collector electrode, 14 is a base electrode,
15 is an emitter electrode.

First, layers 9, 1o, and 11 are formed on a GaAs substrate 8 by a liquid phase epitaxy method. Next, a part of the collector layer 9 was exposed by mesa etching, and a p-type AJxGa1-xAs layer for taking out the 12 base electrodes was formed on that part again by liquid phase epitaxial method, and an electrode was formed on each of them. .

Another method for reducing the collector capacitance is to form the emitter on the substrate side, the base, and the collector on it, as proposed by H. Kreomer (Proc, IEE Jvol. 7).
0. No. 1.1982. p13). FIG. 6 is a structural diagram thereof. In the figure, 16 is a substrate, 17 is an emitter, 18 is a base, and 19 is a collector. The p-type region 20 for taking out the base electrode was formed later by ion implantation. With such a configuration, the collector base junction area becomes smaller, so the collector capacitance becomes smaller. However, with this configuration, even if the collector capacitance becomes smaller, the emitter capacitance does not become smaller.

Since the collector capacitance has a larger influence on the high frequency characteristics, this structure improves the high frequency characteristics, but it is still not sufficient because the emitter capacitance is large.

Problems to be Solved by the Invention In such a conventional configuration, the collector capacitance and emitter capacitance are still large, and therefore it is not possible to obtain sufficiently excellent high frequency characteristics. The present invention has been made in view of this point, and while maintaining the ease of taking out the base electrode,
The purpose is to provide a structure with small collector capacitance and emitter capacitance.

Means for Solving the Problems The present invention solves the above problems by forming a semi-insulating semiconductor layer between the emitter region and the base electrode extraction layer in a structure having an emitter on the substrate side. , while maintaining the ease of taking out the base electrode, the structure has a small emitter capacitance, and by making the area of the collector base junction smaller than the area of the semiconductor layer for exposing the collector electrode area, the collector capacitance is small. It provides structure.

Effects The present invention improves high frequency characteristics because the collector capacitance and emitter capacitance are reduced by the above-described structure.

Example FIG. 1 shows an embodiment of the structure of the present invention.

In FIG. 1, 21 is a semi-insulating GaAs substrate, 22 is an n-type GaAs layer for taking out the emitter electrode, and 23 is n-saint 7! xGa, -xAs (x = 0.3) emitter layer, 24 is p-type GaAs base layer, 26 is n-type Gaps
collector layer; 26 is an n-type GaAs layer for electrode extraction;
2 is a semi-insulating AlyGa1, As (y=o, 3) layer formed on the n0-type Ga layer 22, and 28 is a 2
A p-type GaAs layer is formed on 7 adjacent to the p-type GaAs space layer 24, 29 is an emitter electrode, 3o is a base electrode, and 31 is a collector electrode.

The junction area between the collector layer 26 and the base layer is smaller than the area of the n+GaAs region 21 formed thereon for taking out the collector electrode.

The thickness of each layer is 400p for the 210 semi-insulating GaS substrate.
m, 22 n+ type GaAg layer is 4000X.

23 n saints 1xGa1-xAs emitter layer, 200
0A124 p type G turtle S base layer is 1000 people, 25
1500 people for the n-type GaAs collector layer, 1500 people for the n10 type G & S layer for taking out the 26 collector electrodes, 2
The semi-insulating AJy G aly human S layer of 7 is 15oO^,
There are 2,000 people in the 28 Nor type Gaps group. 22-2
Each layer of 8 was formed by molecular beam epitaxy (MB]i:).

Next, a method of manufacturing an element having the structure of this example will be described.

First, layers 22 to 26 were formed to a predetermined thickness on a semi-insulating GaAs substrate 21 by molecular S epitaxy. Next, by chemical vapor deposition (CVD) method, 30%
A 5i02 film of 00X was formed. Next, a resist mask was formed by a conventional photolithography method, and etching was performed using this resist mask in a mesa shape, as shown in FIG. 2, to expose 22 n+ type GaAs layers.

In FIG. 2, 32 is a 5i02 film and 33 is a resist. Etching of 5i02 was performed using HF (hydrofluoric acid), and etching of GaAs and 1xGa1-xAs was performed using a mixed solution of H2SO4-H2O2-I20.

Next, only A7IxGa1-xAS was selectively etched from the cross section of the mesa portion using a KI-I2-I20 etching solution, thereby making the collector portion concave as shown in FIG. The depth of the depression could be arbitrarily controlled by changing the etching time.

Next, the resist was removed with acetone, and a 1500x semi-insulating AlyGa1-S film and a 2000x p-type CaAs film were formed by molecular beam epitaxy. The film formed on the n-type GaAs of No. 22 was epitaxially grown and was a perfect single crystal film, but the film formed on the S-02 film was a polycrystalline film. ko H2SO4-I202
-I20 When etching is performed using a mixed solution, there is a large difference in etching speed between the single crystal film and the polycrystalline film, and the polycrystalline film can be removed while the newly grown single crystal film is hardly etched. Ta.

Next, a resist mask is formed on the portion where the collector and base will be formed by photolithography, and each layer of 27.28 is formed using H2BO3 using this resist mask.
Etching was performed using a -H2O2-H20 mixed solution to expose the etching electrode forming part.

Next, the resist portion was removed with acetone and the 5102 film was removed with HF, and ohmic electrodes 29, 30, and 31 were formed using conventional photolithography, fee, vacuum evaporation, and heat treatment techniques.

The collector capacitance Cc of the structure of this embodiment is proportional to the collector pace junction area of the mesa portion. Therefore, it is clear that Cc is significantly smaller than when the collector is formed on the substrate side.

The emitter capacitance Ce of the structure of this example is 23 and 24 pn.
It is the sum of the junction capacitance of the junction and the junction capacitance of the junctions 27 and 28.

Generally, the capacitance Cpn of a pn junction is a; Joint area q; electric charge N people 1 + acceptor concentration of p-type semiconductor Donor concentration of ND2Hn type semiconductor ε1; dielectric constant of p-type semiconductor Dielectric constant of ε2in type semiconductor Vbi bias voltage is given by

From this, it can be seen that when the difference between the acceptor concentration and the donor concentration is large, the difference is approximately determined by the smaller one. In this embodiment, the acceptor concentration of the p-type GaAs space layer is 1-1o"/cft, and the donor concentration of the Xn-type GaAs emitter layer is 6.10"/ad.

Therefore, the emitter capacitance is approximately c p n oc 7 ports 1 (3). On the other hand, the n-type GaAg layer and the semi-insulating A, 1y
The junction capacitance with Gs1-AmS layer is semi-insulating AJ y
G a 1ym S layer acceptor concentration is 1-10”/c
Since yj or less, the junction capacitance is proportional to the square root of this acceptor concentration, and its value is much smaller than the value of equation (3). If there is no semi-insulating layer, the emitter capacitance of the junction capacitance between 27 and 28 will be large because the carrier concentration of the n+GaAs layer is as high as 1·1018//c4. Even if a p-type film 1xGa1 or As is used instead of p-type GaAs, the junction capacitance remains almost unchanged. For the above reasons, as in this embodiment, the GaAs layer for counting the p-type base electrode and the n0-type GaAs layer are
By forming a semi-insulating layer between the As layer and the As layer, the collector capacitance can be made much smaller if the area is the same.

Further, in this embodiment, the semi-insulating layer was formed on the n+ type GaAs layer for taking out the collector electrode, but it is clear that the same effect can be obtained even if it is formed on the n-type GaAs collector region.

In this example, AlyGa1-As is used as the semi-insulating layer.
(0,3), but y=o In other words, even if GaAs is used, the collector capacitance will not be reduced.
It is clear that they have the same effect.

In this example, y−〇, 3 was used, but 7 > 0.3
Since the forbidden band energy is larger than that of the emitter, the leakage current between the GaAs layer for exposing the p-type base electrode area and the n-type emitter layer can be further reduced. It can be reduced. Since leakage current reduces the current amplification factor of the transistor, the current amplification factor can be improved by reducing the leakage current.

Furthermore, the maximum frequency Ft at which the current amplification factor of the transistor is 1 is the lower column 'T, "+Lj" x 3°Ft = (1/2π)
-(Person, Ce+B) (4) Oe; Emitter capacitance M+Bi constant Therefore, by reducing the emitter capacitance Co, the high frequency characteristics can be further improved.

The heterojunction bipolar transistor obtained in this example exhibited the following characteristics as expected.

First, we were able to form a good ohmic electrode on a very thin base of 10○○X. In addition, since the collector capacitance and emitter capacitance have become extremely small, the high-frequency characteristics are greatly improved compared to conventional products when the dimensions are the same.

Further, in this embodiment, molecular i-epitaxy was used to obtain a predetermined structure, but it can also be created using, for example, metal organic chemical vapor deposition (MO-CVD) method.

In addition, in this example, GaAs-man 1xGI is used as a semiconductor.
L1. ．． ．． ．． Although the semiconductor device 1 is made using x-man S, other semiconductor materials such as InP-1nGaAsP can also be used. Another person! As concentration, X=0.3.7=0.3
was used, but this can be arbitrarily selected within the range of 0 to 1. When the value of X is large, HF can be used as a selective etching solution for the emitter and collector layers.

Furthermore, in this example, a 5i02 film was used, but a Si3N4 film was used.
Films made of other materials may also be used.

In this example, the emitter and collector are n-type and the base is p-type, but if the emitter and collector electrode types and the base are n-type, the base extraction layer 9 may be n-type. .

Effects of the Invention As described above, the present invention provides a heterojunction bipolar transistor with excellent high frequency characteristics by significantly reducing the collector capacitance and emitter capacitance while maintaining the ease of taking out the base electrode. This is what we provide.

[Brief explanation of drawings]

Fig. 1 is a structural diagram showing an embodiment of the present invention, Figs. 2 and 3 are structural diagrams of a device in the process of manufacturing to realize the structure of the present invention, and Fig. 4 is a structural diagram of a conventional bipolar transistor. , FIG. 6, and FIG. 6 are structural diagrams of a conventional heterojunction bipolar transistor. 21... Semi-insulating GaAs substrate, 22...
... n 10 GaAs layers, 23... n saints 4 x Ga
, -xAs emitter layer, 24... p-type GaAs
Base layer, 26...n-type GaAs=r rectifier layer, 28...-n+Ga S layer, 27...
・Semi-insulating muiy Ga, □mu S layer 228...
... p-type GaAs layer, 29 ... emitter electrode,
3o...Base electrode, 32...Collector electrode, 33...SiO□ film, 34...
・Resist. Name of agent: Patent attorney Toshio Nakao and one other person δ−
-Collector Figure 2, ? 9 Q(-- CXJN Figure 4 Figure 5

Claims (4)

[Claims] (1) A semiconductor having at least a collector region, a semiconductor layer for taking out the collector electrode provided adjacent thereon, a base region, and an emitter region, and in which at least the emitter has a higher forbidden band energy than the semiconductor forming the base. The collector and base junction areas are smaller than the area of the semiconductor layer for taking out the collector electrode, a semi-insulating layer is provided on the emitter or a part of the region for taking out the emitter electrode, and at least A heterojunction bipolar transistor characterized in that electrical contact is made to the base via a semiconductor region provided in contact with the base region. (2) The heterojunction bipolar transistor according to claim (1), wherein a semiconductor having a higher forbidden band energy than the semiconductor forming the base is used as the semi-insulating layer. (3) Form an emitter region on the semiconductor substrate using a semiconductor with higher forbidden band energy than the semiconductor forming the base, then form the base region, collector region, and collector electrode extraction region, and then insulate Using a film mask, etching is performed to leave a part of the collector, the base, and the emitter region in a mesa shape to expose the emitter region, and further, using a selective etching solution, only the collector layer is etched in a concave shape, After that, a semi-insulating layer is formed on the exposed emitter region and the insulating film mask, a semiconductor region is further formed thereon in contact with at least the base region, and the insulating film mask is etched. The semiconductor region and a portion of the semi-insulating layer are further removed by etching to expose a portion of the emitter, and a collector electrode, a collector electrode, and a A method for manufacturing a heterojunction bipolar transistor, characterized in that a base electrode and an emitter electrode are formed. (4) The method for manufacturing a heterojunction bipolar transistor according to claim (3), wherein a semiconductor having a higher forbidden band energy than the semiconductor forming the base is used as the semi-insulating layer.