JPS6258176A - Logic waveform generation circuit - Google Patents

Abstract

PURPOSE:To make it possible to form a logical wave form having a pulse width smaller than that of an input clock, by forming several kinds of fundamental wave forms not depending on the pulse width of the input clock and synthesizing said fundamental wave forms. CONSTITUTION:The logical data signal 308 and control data signal 309 received by a decoding circuit 304 are outputted as fundamental wave form data 310-312 to be inputted to D-type FFs 305-307 and outputted as fundamental wave form data 334-336 in synchronous relation to a fundamental cycle clock 313. Next, D-type FFs 305-307 sample the fundamental wave form data outputted from an output circuit 301 on the basis of clock signals 322-324. A setting/ resetting control circuit 321 receives the signals 308, 309 to output control signals 325-328 for controlling the opening and closing of AND circuits 317-320 and controls the continuity of the clock 313. The output signals 329-332 of the circuits 317-320 set and reset FFs 315, 316. By this method, fundamental wave forms 337-339 are outputted from FFs 314-316 and outputs are judged through AND gates 340-342 and an OR gate 343.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a logic waveform generation circuit, and in particular to a logic waveform generation circuit for generating various logic waveforms used in a logic circuit testing device, which output logic waveform. The present invention relates to a logic waveform generation circuit suitable for generating a logic waveform having a pulse width smaller than the pulse width of a clock signal that determines the timing of a clock signal.

[Background of the invention]

Conventional logic waveform generation circuits are based on N RZ (Non Re
TurnZero) waveform, RZ (Return Z
ero) waveform, EOR (fixclusive OR)
It is configured to generate various logical waveforms such as waveforms.

However, the logic circuit under test is E CL (Emitter
In the case of a high-speed device such as a coupled logic device, the pulse width of the output logic waveform is required to be sufficiently small. On the other hand, in the conventional technology described above, the problem is that the minimum pulse width of the output logic waveform is limited by the pulse width of the clock input to the RS flip-flop, which is one component of the logic waveform generation circuit. There is. Next, the above problems will be explained using FIGS. 3 to 5.

FIG. 3 is a diagram showing an example of a conventional logic waveform generation circuit, and FIGS. 4 and 5 are time charts showing its operation. In FIG. 3, logic data signals 111 and 112 of opposite polarity are input to the circuit unit 101 via an OR circuit 103, and a control data signal 104 is input to the seven circuit unit 101. .112
and the lock signal 108 . based on the control data signal 104 .
Select 109.110, RS flip-flop 102
A reset signal 105 and a cent signal 106 are output to the terminals (indicated as F and F in the figure). The RSS flip-flop 10 is set and reset based on the selected clock signal and outputs a logic waveform 107.

FIG. 4 is a time chart showing an example of RZ filter waveform formation using the conventional logic waveform generation circuit shown in FIG. As shown in the figure, in the circuit section 101, a reset signal 105 is generated based on clock signals 108 to 110.
and a set signal 106 is formed.

Based on the reset signal 105 and set signal 106, the RS flip processor 102 outputs an RZ filtered waveform as a logic waveform 107. FIG. 4 shows a case where RSS flip-flop set priority is given (a configuration in which when the set signal 106 is "1", even if the reset signal 105 is set to "L", it is not reset), and the RS flip-flop 10
The reset signal 105 of No. 2 cannot be set in the range where the set signal 106 is "1" (the shaded area a in the figure).

Therefore, the pulse width TWI of the logic waveform (RZ filtered waveform 107) output from the RS flip-flop 102 is limited by the pulse width TSW of the reset signal 106,
I>TSW. That is, the logical waveform (RZ filter waveform 107
The pulse width of the set signal 105 cannot be made smaller than the pulse width of the set signal 105.

Similar to FIG. 4, FIG. 5 is a time chart showing an example of generating an RTO waveform using the conventional logic waveform generation circuit shown in FIG. 3. Priority is given to resetting the RS flip 20 knob 102 (when the reset signal 105 is “1”, the set signal 106 is “1”)
” (configuration in which it is not set even if it is set).

If the RS flip-flop 102 with reset priority is used, it is possible to make the RZ filter waveform pulse width smaller than the pulse width of the cent signal 106 (not shown).
When generating the RTO waveform as the logic waveform 107 as shown in FIG. 5, the pulse width TW2 of the RTO waveform is limited by the pulse width TRW of the reset signal 105, and TW2>
Becomes TRW. That is, the cent signal 106 of the RS flip-flop 102 cannot be set in the range where the reset signal 105 is "1" (the shaded area b in the figure), and the pulse width is smaller than the pulse width T'RW. R of
The 'r' O waveform cannot be generated.

As explained above, the conventional logic waveform generation circuit has a problem in that the pulse width of the generated logic waveform cannot be made smaller than the pulse width of the clock signal.

[Purpose of the invention]

An object of the present invention is to control the pulse width of the generated logic waveform without being limited to the pulse width of the input clock signal.
It is an object of the present invention to provide a logic waveform generation circuit capable of generating a logic waveform having a pulse width that can be arbitrarily varied and smaller than the pulse width of a manually inputted clock signal.

[Summary of the invention]

The logic waveform generation circuit of the present invention includes a first means for outputting a plurality of basic waveform data independent of the pulse width of a clock signal based on an input logic data signal and a control data signal; Based on the control signal generated from the control data signal and the basic cycle clock, a plurality of basic waveform data output from the first means are sampled at the input timing of the clock signal, and the data is dependent on the pulse width of the clock signal. and a third means for synthesizing the plurality of fundamental waveforms outputted from the second means and outputting a desired logical waveform.

[Embodiments of the invention]

The present invention will be described in more detail below with reference to embodiments shown in the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment of the logic waveform generation circuit of the present invention. This embodiment is roughly divided into data generation circuit 3.
01, basic waveform generation circuit 302 and waveform synthesis circuit 303
It consists of:

The data generating circuit 301 receives a logical data signal 308 and a control data signal 309 of several bits (indicated by n bits in the figure) at a decoding circuit 304, and the decoding circuit 304 outputs basic waveform data 310, 311, and 312.

Basic waveform data 310, 311, and 312 are connected to D-type flip-flops 305, 306, and 307 (F in the figure), respectively.
, F, ) is input to the data input terminal of
Basic waveform data 334, 335, and 336 are output in synchronization with the basic cycle clock 313 that is input to the clock input terminal of the D-type flip-flops 305, 306, and 307. Specific examples of the basic waveform data 334, 335, and 336 are shown in Table 1 below.

The basic waveform generation circuit 302 in Table 1 includes one D-type flip-flop 314, two D-type flip-flops 315 and 316 with set/reset (indicated as F, F, in the figure), and four AND circuits 317 to 320. and a cent/reset control circuit 321. The D-type flip-flops 314, 315, and 316 sample the basic waveform data output from the data generation circuit 301 using the clock signals 322, 323, and 324 that are input to the clock input terminals. On the other hand, the set/reset control circuit 321
receiving a logic data signal 308 and a control data signal 309;
Control signal 32 for controlling opening/closing of AND circuits 317 to 320
5 to 328 to control conduction of the basic period clock 313. And this AND circuit 317~
The output signals 329 to 332 of the D-type flip-flops 315.320 are inputted to the reset terminal R and set terminal S of the D-type flip-flops 315.316 as shown in the figure.
Set/reset 16. At this time, the logic data 308 and the control signal 3 of the set/reset control circuit 321
An example of the relationship between 25 to 328 and the states of the D-type flip-flops 315 and 316 is shown in Table 2.

Table 2 [In this way, the basic waveforms 337 to 339 are generated from the D-type flip-flops 314 to 316 in the basic waveform generation circuit 302.
is output and input to the waveform synthesis circuit 303.

The waveform synthesis circuit 303 includes the above-described flip-flop 131.
The basic waveforms 337 to 339 obtained from 4 to 316 are synthesized, and in this embodiment, three AND gates 34
0 to 342 and an OR gate 343. This waveform synthesis circuit 303 sets the output 345 to "1" when any two of the basic waveforms 337 to 339 output from the basic waveform generation circuit 302 are "1", and outputs 345 when any two are "0". The configuration is such that the output 345 is "0".

Next, the case where an RZ waveform is generated by the embodiment shown in FIG. 1 will be described using Table 1, Table 2, and FIG. 2 described above. Basic cycle clock 313 and clock signal 3
22 to 324 are signals having the same period as shown in the figure, but having different phases. Logical data input signal 3
08 is "1" and "0" over the basic period as shown in the figure.
It is a signal to repeat. When generating a positive RZ waveform (RZ waveform when the logical data input signal 308 is "1"), as shown in Table 1, the D-type flip-flops 305 and 306 in the data generation circuit 301 .30
The basic waveform data output from 7 is 334 to 336 “
O”.

They become “1” and “0”. In FIG. 2, the basic waveform data 334 to 336 are displayed together for convenience. The basic waveform data 334 to 336 are input to the basic waveform generation circuit 302.

On the other hand, in the set/reset control circuit 321 in the basic waveform generation circuit 302, the controls 325 to 3 are controlled as shown in Table 2.
"1", "0", "0", and "1" are output to 28, respectively, and AND circuits 317 and 320 are opened. Therefore, the basic period clock 313 is outputted as an output signal 329.332 from the AND circuit 317.320, resets the D-type flip-flop 315, and resets the D-type flip-flop 31.
6 cents. Then, the clock signals 322-324
At the timing when becomes “1”, the D-type flip-flop 31
4 to 316 sample the basic data waveforms 334 to 336, respectively, and the basic data waveforms 337 to 339 shown in FIG.
Output. In the waveform synthesis circuit 303, as shown in FIG. 2, the fundamental waveforms 337, 338 are "0" in period a, the fundamental waveforms 338, 339 are "1" in period C, and the fundamental waveforms 337, 338 are "1" in period C. 339 is “O”, the output 345 is “0” in period a and “0” in one period as shown in the figure.
1'', and C between u becomes "0".

In FIG. 2, if the pulse d of the clock signal 324, which defines the falling edge of the pulse of the output 345, is set to the position shown by diagonal lines, the period of the output 345 can be changed by the clock signal 324.
It becomes possible to make the pulse width shorter than ~325.

In FIG. 1, when generating a negative polarity RZ waveform, "0" and "0" are output to outputs 334 to 336 as basic waveform data 334 to 336, as shown in Table 1.

It is sufficient to output "0" and further reset the D-type flip-flops 315 and 316 in synchronization with the basic period clock 313 as shown in Table 2 and FIG. The pulse width (negative polarity) of the output 345 can be made shorter than the pulse widths of the clock signals 322 to 324, as in the case of the positive RZ waveform described above.

〔Effect of the invention〕

According to the present invention, when generating a logic waveform, several types of basic waveforms that do not depend on the pulse width of an input clock are generated,
By synthesizing this basic waveform, it is possible to generate a logic waveform having a pulse width smaller than the pulse width of the input clock.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a circuit diagram showing an example of a conventional logic waveform generation circuit, and FIGS. 4 and 5 are operation of the conventional logic waveform generation circuit shown in FIG. 3. It is a time chart showing. 301...Data generation circuit, 302...Basic waveform generation circuit, 303...Waveform synthesis circuit, 304...Decode circuit, 305-307.314-316...D flip-flop (F in the figure) , F, )321
. . . Set/reset control circuit, 313 . . . Basic period clock, 322 to 324 . . . Clock signal. Agent Patent Attorney Tadashi Akimoto Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] a first means for outputting a plurality of basic waveform data independent of the pulse width of the clock signal based on the input logic data signal and control data signal; and Based on the generated control signal, a plurality of basic waveform data outputted from the first means are sampled at the input timing of the clock signal, and a plurality of basic waveforms independent of the pulse width of the clock signal are output. and a third means for synthesizing a plurality of basic waveforms output from the second means to output a desired logical waveform independent of the pulse width of the clock signal. Logic waveform generation circuit.