JPS6258491B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a display device in a focusing state detection system.

The present invention is a further improvement of the display stabilization circuit previously proposed by the applicant in Japanese Patent Application No. 149079/1982.

In the previous proposal, when detecting the focus adjustment state, if the interval between detecting the focus adjustment state becomes longer,
For example, no countermeasures have been taken for the case where the surroundings are dark and sufficiently high-intensity light does not enter the light receiving element for focus detection, and it takes a long time to obtain a signal from the element. Therefore, if the surroundings are dark as described above, the subject is in focus, the display shows that the subject is in focus, and for some reason the subject becomes in focus and out of focus, the surroundings will also be dark. Therefore, until a signal is obtained from the element and it is detected that the subject is out of focus, the detection result of the previous focus adjustment state, that is, the in-focus state is displayed, and as a result, the subject is in focus. There was a drawback that the focus status was displayed even though it was not.

The present invention has been made in view of these drawbacks, and an object of the present invention is to provide a focus adjustment state display method that erases past data when the acquisition cycle of focus detection data is long when performing focus detection. be.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

In the figure, reference numeral 1 is a focus adjustment state signal from a known focus detection means, and by passing it through ROM 2, four states of in-focus, front focus, back focus, and state indistinguishable are detected.
Convert to bit code signal. This code signal is passed through a data selector consisting of AND gates 3, 4 and an OR gate 5, a D-FF (D flip-flop) 6, a data selector also consisting of AND gates 7, 8 and an OR gate 9, and a D-FF (D-type flip-flop) 6. FF1
A data selector consisting of AND gates 11, 12 and an OR gate 13, a D-FF 14, and a data selector also consisting of AND gates 15, 16 and an OR gate 17. , D-FF18, it is possible to maintain and update data from one generation ago. 19 is a sufficiently fast clock generated from a clock generation circuit (not shown),
Clocking 14 and 18. 21 is an input line 2 for receiving a judgment completion signal from a focus state judgment circuit (not shown).
0, the clock 19 outputs the signal 20 to its terminal, and by passing these through the AND gate 22, the output 23 generates a high pulse for only one clock period when determining the focus state. .

Reference numeral 24 denotes a signal that becomes high when a focus state of a focus detection device (not shown) is detected (for example, when a detection optical system such as a movable mirror is set at a predetermined position), and this signal 24 and the output 23 of the AND gate 22 are combined. AND
When the external conditions are normal, a determination completion pulse of the focusing state determination circuit is generated at the output 29 of the gate 28. This signal is passed through an inverter 30 to generate an inverted signal at its output 31. By this inverted signal, AND gates 3, 7, 1 for circulation
Close 1, 15, D-FF6, 10, 14, 18
This prevents the maintenance of the state.

At this time, if there is an abnormality in the front stage of the focus detection device, such as overrange,
The input line 32 becomes low due to the action of a circuit not shown, and the AND gate 33 cuts off the transmission of the output 29, turns off the AND gates 4 and 8, and outputs D-FF6,
The input of 10 and 10 is set to low to create a code corresponding to state indistinguishability, and in other cases, the output from the ROM 2 is loaded into the D-FFs 6 and 10.

When the data acquisition cycle is long, an unillustrated circuit causes the input line 34 to go low.
AND gate 35 is turned off, AND gate 12,
16 is turned off and D-FF is used to retain past data.
The outputs of 14 and 18 are made low, that is, erased and rendered indistinguishable.

Note that the signal 2 remains unchanged while the data acquisition cycle elapses.
0 is a low level, and since the output of the AND gate 22 is a low level, the signal 29 is also a low level, and the output of the AND gate 1 is passed through the inverter 30.
1 and 15 are on, so D-FF14,
18 holds past data.

The outputs of the above four D-FFs 6, 10, 14, and 18 are divided into three codes by the ROM36.
LED4 through NAND gates 37, 38, 39
0, 41, and 42 are lit according to focus, front focus, and rear focus. 43 is a current limiting resistor.

At this time, the lighting duty is controlled to be higher (brighter) when it is bright by a pulse input line 44 whose duty changes depending on the brightness of the subject or the outside world, and when there is a power supply abnormality from a power supply voltage check circuit (not shown). , for example, the signal on the input line 45 that goes low when the voltage drops is combined with the aforementioned signal 24.
By applying this to the AND gate 46, a signal that becomes high only during normal operation is obtained at its output, and this
By adding this to the NAND gates 37, 38, and 39, display is allowed only during normal times and inhibited during shooting.

Data selector and D-FF in the above embodiment
(D-type flip-flop) is similar to a general register, and logic other than this D-FF can be easily converted into ROM.

Incidentally, in the above-mentioned embodiments, the interface section for the focus detection device and the circuit shown in the drawings can be applied, for example, as disclosed in the above-mentioned Japanese Patent Application No. 149079/1983.

As described above, according to the present invention, when it takes a long time to obtain the next focus detection result after the previous focus was achieved, the latest focus Since it displays the detection results, if the focus detection time takes a long time, the previous predetermined time has elapsed and there is a possibility that the focus detection result will be in a different state from the current focus state. Since this can be ignored, accurate focus detection display can be performed even on a display device that displays the focus state in consideration of the previous focus detection result.

[Brief explanation of the drawing]

The figure is a block circuit diagram showing an embodiment of the present invention, particularly a configuration of a partial circuit according to an improvement of the present invention. 2, 36...ROM, 6, 10, 14, 18,
21...D type flip-flop, 3~5,7~
9, 11-13, 15-17, 22, 28, 3
3, 35, 37 to 39, 46... logic gate, 4
0-42...LED.

Claims (1)

[Scope of Claims] 1. A focus detection circuit that repeatedly detects the focus adjustment state of a photographic lens with respect to a subject, and a detection result obtained by the focus detection circuit is inputted and holds the input detection result, and a first memory circuit that updates the held content by inputting a new detection result from the focus detection circuit; and a first memory circuit that updates the held content by inputting a new detection result from the focus detection circuit; a second memory circuit that holds the contents of the memory circuit until updated;
When the content of the first memory circuit is a detection result indicating in-focus, and the content of the first memory circuit is a detection result indicating out-of-focus, the content of the second memory circuit is selected, and the content of the second memory circuit is selected. is a detection result indicating out-of-focus, and on the other hand, when the content of the first memory circuit is a detection result indicating in-focus, the content of the first memory circuit is selected, and the selected first
Alternatively, in a focus state display device that displays a focus state based on the contents of a second memory circuit, when the time for the focus detection operation by the focus detection circuit becomes longer than a predetermined time, the first memory circuit 1. A focus state display device comprising control means for selecting the contents of the first memory circuit and displaying the focus state based on the contents of the first memory circuit.