JPS6260194A - Dynamic ram - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a dynamic RAM (random access memory). For example, the present invention relates to a dynamic RAM (random access memory). Multi-method dynamic RA
This article relates to techniques that are effective for use in M.

[Background technology]

In a multi-address dynamic RAM, a row (X) address signal and a column (Y) address signal are multiplexed and supplied to a common address terminal. In this case, in addition to making the number of bits of the row address signal equal to the number of focuses of the column address signal, an irregular bit configuration is required, for example, making the row address signal 8 bits and the column address signal 6 bits. It may be said that If the configuration of the address signal differs in this way,
The memory array and address decoder must be configured accordingly (therefore, the design spent on it,
A problem arises in that manufacturing costs increase.

Regarding dynamic RAM, for example, see ``Hitachi IC Memory Data Book J'' published by Hitachi, Ltd. in September 1988.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic RAM that achieves improved mass productivity for different address supply systems.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.9 Namely, a row and column address decoder that forms a selection signal for a memory array in which row and column addresses are configured equally. In the case of a configuration in which the number of bits of the row address signal or the number of bits of the column address signal is 2", 2"
The output signal of the row address buffer corresponding to ``/2 bits is supplied to the column address decoder.

〔Example〕

FIG. 1 shows a block diagram of a dynamic RAM according to the present invention. Which circuit elements make up each circuit block in the same diagram? , is formed on a semiconductor substrate such as, but not limited to, single crystal silicon using known semiconductor integrated circuit manufacturing techniques.

In this embodiment, although not particularly limited, the memory array M
-ARY is configured by a two-intersection method (folded bit line or digit line method).

Column system (data!1) in memory array M-ARY
it) The signal line is composed of a pair of complementary data lines arranged in parallel, and in the figure, the signal lines are arranged in the horizontal direction. Row-related address selection lines (word lines, dummy word lines) are arranged in the vertical direction in the memory array M-ARY. There are 128 complementary data lines and 128 word lines each, and therefore 128 addresses are assigned to each. As a result, one memory array M-ARY has a total storage capacity of about 16 bits. In this embodiment, a total of four similar memory arrays M-ARY are provided in order to write and read information in units of 4 bits, although this is not particularly limited. It has a storage capacity of .

Note that in a dynamic RAM, the memory array includes a sense amplifier for amplifying the complementary data signal and a data signal sent to the memory, a precharge circuit for bringing the complementary data line to a precharge level, and a complementary data line. A column switch circuit and the like for selection based on a column address decode signal are coupled. However, the specific configurations of those circuits are not directly related to IQ of the present invention. In FIG. 1, the memoria L/-i Lf-A RY is understood to include a sense amplifier SA, a column switch circuit for selecting a data line, etc. to avoid complicating the drawing. sea bream. The sense amplifier SA receives a timing signal φp during write/read operations.
a is selectively activated by a word line selection operation, a minute read voltage from a memory cell coupled to one data line of the complementary data lines is transferred to the other data line by a dummy word line selection operation. The reference voltage from the dummy cell coupled to the dummy cell is referenced and amplified. In other words, the sense amplifier SA is connected to Mwo! -Amplify to high level, /low level.

The L ton address buffer R-ADB is formed in synchronization with the row address rope signal RAS.
In this embodiment, the unit circuits XO to x7 are made up of eight unit circuits that are activated by the switching signal φar and receive address signals supplied from eight external terminals AO and -A7, respectively.
It consists of The above unit diagram 1i! 3XO-χ゛l is
The above timing signal φ is output from external terminals AO to A7, respectively.
It holds the address signal supplied in synchronization with ar, and generates an internal AT/S signal with the same sign and opposite phase as the internal address signal. Among the unit circuits xO to X7, the internal address signals formed by the unit circuits X1 to X7 are sent to the row address decoder R-D.
This will be communicated to CR. Furthermore, although the internal address signal formed by the unit circuit XO is a row address signal, the column address decoder C-DC
This will be communicated to R.

The row address decoder R-IJCR decodes the internal address signal supplied from the row address buffer R-ADB and selects one line of the memory array q'M-ARY in synchronization with the word line selection timing signal φX.
1' line and dummy word line are selected, in this case,
The address signal supplied in synchronization with the row address strobe signal RAS consists of 8 bits, of which 1 bit (XO) is sent to the row address decoder R-
Since it is not supplied to OCR, memory array M-ARY
A selection operation of 1/128 corresponding to the number of word lines is performed.

The column address buffer C-ADB is activated by a timing signal φac generated in synchronization with the column address strobe signal CAS.
It is composed of six unit circuits Y1 to Y6 each receiving address signals supplied from six external terminals A1 to A6. The above unit circuits Y1 to Y6 each have an external terminal Al
In response to the address signal supplied from -A6 in synchronization with the timing signal φac, an internal address signal having the same phase as that address signal and an internal address signal having the opposite phase are generated and transmitted to the column decoder C-DCH.

Column decoder C-DCR receives a total of 7 bits supplied from six unit circuits Y1 to Y6 that constitute the column address buffer C-ADB and one unit circuit XO that constitutes the row address buffer R-ADB. The internal address signal is decoded to form one column selection signal to be supplied to the column switch circuit included in the memory array M-AR'/ in synchronization with the data line selection timing signal φy. As mentioned above, the column address signal consists of 6 bits, but when 1 bit (YO) of the row address signal is added, a column selection signal of 1/128 is formed. At this time, before the column address signal is supplied from the unit circuit xO that receives the row address signal, the column address decoder C-D
The column address decoder C-DCR performs its selection operation in response to the data line selection timing signal φy, so even if the above signal (YO) is supplied early, there will be no inconvenience in the column selection operation. Note that the column switch circuit receives the selection signal formed by the column address decoder C-0CR and connects the complementary data line of the memory array M-ARY to the common complementary data line CD.

The common complementary data line CD is coupled to the output terminal of the data input buffer sofa DIB and the input terminal of the data output buffer DOB.

The data output buffer DOB receives the write enable signal W.
In the case of a read operation in which E is set to a high level, the timing signal φr- puts it into an operating state, and in that operating state, the signal on the common complementary data line CD is amplified and sent to the external terminal Dout. In the write operation, the data output buffer DOB is rendered inactive by the timing signal 7rw and brought into an output high impedance state.

As described above, when memory access is performed in units of x4 bits, a total of four data output buffers DOB are provided corresponding to the four memory arrays M-ARY.

When the write enable No. 18 WE is at a low level and the data input cover sofa DIB is in a 7-component operation, the data input cover sofa DIB is put into an operating state by the timing signal φrw, and in that operating state, the blue entry signal supplied from the external terminal Din is sent to the above-mentioned common complementary data. Tell the line.

In the data input cover sofa DIB, in the read operation,
The above-mentioned timing signal ψr- makes it inactive, and the output is brought into a high impedance state, so that the transmission of the read signal g to the common complementary data line is not prevented. As mentioned above, when memory access is performed in units of ×4 bits, four memory arrays M-AR
A total of four data input buffers DTB are also provided corresponding to Y.

The timing control circuit TC receives control signals RAS (row address strobe signal) and CA supplied from external terminals.
It receives the SC column address strobe signal (SC column address strobe signal) and WE (write enable signal), forms and sends out the various timing signals necessary for memory operation according to the operation mode.

FIG. 2 shows a timing diagram for explaining the fluctuation in the operation of the RAM.

When the row address strobe signal RAS is changed from a high level to a low level, for example, the timing signal φar is changed to a high level in response to this, and the row address buffer R-ADB is activated. Each unit circuit X0-X7 constituting the row address buffer T2-ADH receives an address signal supplied from address terminals AO-A7, holds it, and forms an internal address signal.

Among these, the internal address signals corresponding to address terminals A1 to A7 are transmitted to the row address decoder R-DCR, and the internal address signals (
YO) is transmitted to the column address decoder C-DCR.

After this, the word line selection timing signal φX is set to high level, and the row address decoder R-DCR decodes the signals of the above 7 bits (Al to A7).
One word line and its corresponding dummy word line are brought into a selected state.

Next, the sense amplifier operation timing signal φpa is set to high level, and the sense amplifier SA is activated.

The sense amplifier SA performs an operation of amplifying the stored information of the memory cell connected to the selected word line by referring to the reference voltage formed by the dummy cell connected to the dummy word line.

When the column address strobe signal CAS changes from high level to low level, for example, the timing signal φaC
is set to high level, column address buffer C-AD
B is activated. Column address buffer C-A
Each unit circuit Y1 to X6 constituting the DH receives an address signal supplied from the address terminal Al-A6, forms an internal address signal, and outputs the column address decoder R-D.
Tell CR.

After that, the data line selection timing signal φy is set to high level, and the column address decoder C-DCR receives the 6-bit (Al to A6) signal supplied from the column address buffer C-ADB and the row address buffer side. By decoding the signal (YO) from the unit circuit XO, a column selection state is formed in which a pair of complementary data lines are coupled to a common complementary data line.

Next, if it is a read operation in which the write enable signal WE is set to high level, a data output cover sofa (not shown) is activated.
A timing signal φrw is generated to put B into an operating state, and the signal read out to the common complementary data line is amplified and sent to the external terminal Dout.

In the dynamic RAM shown in FIG. 1, when both the row address signal and the column address signal are supplied as the same 7 bits, for example, the address terminal AO is set as an empty terminal and the unit circuit X.

The input of is coupled to address terminal A7. This unit circuit XO has the above-mentioned row system timing (i-no.
By supplying a column system timing signal φac instead of ar, the unit circuits Y1 to Y6 are brought into operation at the same time as the unit circuits Y1 to Y6.

Such a change in connection can be easily realized, for example, by changing the mask for selective processing of rounding forming wiring layers such as Aluminum New J, Rikijo, and so on. and,
The only difference in the operation is that the operation timing of the unit circuit XO is different, and that the row system address LJ and the column system address signal are both introduced to the address terminals A1 to A7.

When a plurality of memory arrays are provided on a semiconductor substrate, a row address decoder and a column address decoder are provided in common to each of the plurality of memory arrays, and an address buffer, timing circuit, data input cover sofa, Peripheral circuits such as data output buffers are provided in the periphery of the main circuit portion consisting of the memory array and address decoder.For example, when there are four memory arrays as in the embodiment, the four memory arrays are arranged on the semiconductor substrate. Two row address decoders and two column address decoders are provided corresponding to the four memory arrays.

One row address decoder is common to the first and second memory arrays, for example, and is disposed in an installation area sandwiched between these memory arrays, and the other row address decoder is common to the third and fourth memory arrays. The memory arrays are shared by the memory arrays and placed in the installation area sandwiched by these memory arrays. One column address decoder is common to the first and third memory arrays and placed in a portion sandwiched between these memory arrays, and the other column address decoder is common to the second and fourth memory arrays. and placed between these memory arrays. The input wiring, control wiring, common data line for data input/output, etc. for the row address decoder and column address decoder arranged between these memory arrays are extended over the area set between the memory arrays, and It is coupled to an address buffer, a timing control circuit, a data input cover sofa, and a data output cover sofa provided around the circuit.

Therefore, according to this embodiment, the wiring connections can be changed substantially in the peripheral circuit portion located around the memory array, which is relatively easy. The circuit operation of the above-mentioned connection change differs only in that the operation timing of the unit circuit XO is different and that row-related address signals and column-related address signals are supplied to address terminals A1 to A7.

〔effect〕

(11 If the internal circuits such as the memory array and address decoder are configured to make the row address and column address equal, and the number of bits of the row address signal and the number of bits of the column address signal are 2" larger than the number of bits of the row address signal and the number of bits of the column address signal, 2"
By supplying the output of the address buffer corresponding to /2 to the column address decoder, the memory array and address decoder can be used both when the row address signal and the column address signal are the same and when they are different. . Therefore, by simply changing some connections, we developed both a dynamic RAM in which the row address signal and column address signal are the same, and a dynamic RAM in which the row address signal and column address signal are different.
The effect is that manufacturing can be carried out.

(2) According to (1) above, by changing a part of the dynamic RAM that has already been developed and in which the row address signal and column address signal have the same number of focuses, the number of bits of the row address signal can be changed to the number of bits of the column address signal. An effect can be obtained that a dynamic RAM having a number of bits larger than the number of bits by 2n can be formed.

1. The invention made by the present inventor has been specifically explained based on Examples, but this invention is not limited to the above Examples, and it should be noted that various changes can be made without departing from the gist of the invention. For example, when performing memory access in units of x4 bits, two memory arrays are configured, and one column selection signal selects two pairs of complementary data lines to access two bits from each. The configuration of the memory array can be modified in various ways, such as one that allows access in units. Further, the write/read operation may be performed in units of one bit instead of in units of multiple bits as described above.

[Application field]

This invention is a dynamic RA using multi-address system.
It can be widely used for M.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram for explaining an example of its operation. M-ARY...Memory array, R-ADB...Row address buffer, C-ADB...Column address decoder, Xo-X7. Yl~Y6・・Unit circuit, R-DCR・
・Row address decoder, C-DCR・・Column address decoder, DIB・・Data person cover sofa, DOB・
・Data output buffer, TC...Timing control circuit Patent attorney Tomio Ogawa-゛', j' Figure 1

Claims (1)

[Claims] 1. A memory array that is selected based on row and column addresses, a row and column address decoder that forms selection signals for the memory array, and a memory array that is selected based on row and column addresses, and a row and column address decoder that forms selection signals for the memory array, and It includes a column address buffer that takes in the supplied row and column address signals, and supplies a predetermined one of the row address signals supplied from the common address terminal to the column address decoder as a column address signal. A dynamic RAM that is characterized by: 2. The dynamic RAM according to claim 1, wherein the connection of the address buffer corresponding to the irregular row and column address supply method is realized by a master slice method.