JPS6261124A - Control system for instruction execution cycle - Google Patents

Abstract

PURPOSE:To make it possible to change the time of one machine cycle on the basis of user selection using an MPU by changing the period of reference clocks by mode setting and forming a mode for executing all instruction format in one cycle mode. CONSTITUTION:The titled system is constituted of a function block, a NOR 18a finding out the NOR conditions of three input signals from AND circuits 14, 17 and a mode setting part 21 and the mode setting part 21 for setting up a machine cycle mode. When a slow I/O interface or the like to be driven only when one machine cycle outputted from the MPU is 1musec is to be controlled, one machine cycle of a reference clock is set up to 1musec and a condition for cancelling the output of a signal for varying the machine cycle time based upon an two cycle instruction and a three cycle instruction developed by a decoder is set up by the mode setting part 21, so that all instructions can be driven in the machine cycle of 1musec.

Description

[Detailed Description of the Invention] [Summary] This is an instruction execution cycle control method that executes instructions according to the instruction format based on a basic clock consisting of a predetermined cycle of the machine clock sent from a microprocessor (hereinafter referred to as MPU). In contrast to the previous method where the number of execution cycles was variable, by changing the period of the basic clock by mode setting and providing a mode in which all instruction forms are executed in one cycle mode, the number of execution cycles can be changed by changing the number of execution cycles depending on the user selection of the MPU.
It is also possible to vary the machine cycle time, making it possible to provide a more efficient MPU.

[Industrial application field]

The present invention relates to an instruction execution cycle control method that allows the number of instruction cycles of an MPU to be varied according to a user's selection and provides an efficient MPU usage pattern.

The ability and performance of MPtl depend on the instruction execution time.

For example, an MPU that controls a high-speed direct access storage device (hereinafter referred to as DASD) is required to have high performance, and the execution time must be shortened accordingly.

For example, if you have a high-performance MPU that can operate in one cycle time of 100 ns, it will take 2 cycles (200 ns) or 3 cycles (300 ns) depending on each instruction.
It is customary to use it as a processor that can operate on.

This is effective when the external device controlled by the processor operates at high speed and the processor operates at its limits in order to respond to that operation (for example, DASD control).

However, for example, there are cases where the operation of an external device does not require such high speed, and the cycle time (2) does not need to be 100 ns. That is, for example, when controlling a low-speed Ilo interface, some users prefer to set it to 1 μSEC because the interface operates at a low speed and if one machine cycle does not take 1 μSEC, the circuits within the external device cannot operate.

In such a case, the MPU's capacity is that all instructions are 1
Although it is possible to operate within μSEC, depending on the instruction format, it may take 1 machine cycle (1μ5EC), 2 machine cycles (2μSEC), or 3 machine cycles (3μSE
C), which is not efficient.

It is expected to realize an MPU that can set efficient machine cycles that can support two high-speed external devices as described above and can also support low-speed external devices.

[Prior art and problems to be solved by the invention] Figure 3 is a block diagram explaining the conventional example, Figure 4 is a diagram explaining the situation of the machine crofter, and Figure 5 is a diagram explaining the instruction form. show.

Normally, the command instruction (instruction format) 11 sent to the MPUI is, for example, an FMT instruction format as shown in FIG.
, ALU indicating the type of operation, IR indicating the XR1 internal register address indicating the 5 POP1 external register address indicating a special operation which is an operation instruction for hardware directly controlled by the MPUI.
It consists of

The execution time of the MPUI executed by the instruction instruction (instruction form) 11 is determined by the type of instruction, with one period of the basic clock (11) being one machine cycle.

For example, the number of machine cycles varies depending on each instruction, such as 1 cycle (4) for internal register operation, 2 cycles (5) for external register operation, and 3 cycles (6) for fetch/store to memory.

That is, command instruction (command form B) 11 F
MT is decoded by the decoder 12 and a 2-cycle instruction (5
) or expand the 3-cycle instruction (6).

When the 2-cycle instruction (5) is expanded, the signal shown in FIG.
3 and AND14, and the predetermined signal is N.

Send to AN[119 via R18 and N0T20.

On the other hand, the other terminal of AND19 is connected to the basic clock (
1) is input, and by the logical product condition of AND19, HP
ol's machine clock (3) is a two-cycle instruction (5
) is created and sent.

In addition, in the case of 3-cycle instruction (6), F, F15. F, F
16 and H AND17 The signal that inhibits the 0 position part is ANDed through N0R18 and N0T20.
19, a 3-cycle instruction (6) which is a machine clock (3) is created and sent out.

These two-cycle instructions (5) and three-cycle instructions (6)
The reason why this is necessary is that the operating time of the internal hardware is a factor in determining the performance of the MPUI.

When a user uses the MPUI described above, depending on the operating conditions of the external circuit (not shown), two-cycle instructions (5
) and 3-cycle instructions (6), it is possible to vary the time of one machine cycle, but it is impossible to vary the instruction execution time (number of instruction execution cycles).

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

This block diagram shows the functional blocks explained in Figure 3 (however,
(excluding N0R18), N0R18a which takes the NOR condition of three input signals from 8ND14.17 and mode setting section 21, and mode setting section 21 which sets the machine cycle mode.

[Effect]

For example, one machine cycle output from MPLI is one
When controlling a low-speed I10 interface that can only operate with μSEC, one machine cycle of the basic clock is 1 μSEC, and in such a low-speed case, the machine cycle time is determined by the 2-cycle and 3-cycle instructions developed by the decoder. By setting a condition in the mode setting unit to cancel the output of a signal that varies the , it becomes possible to provide an efficient MPtl that can operate all instructions in a machine cycle of 1 μSEC.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 2 shows a detailed diagram of the invention.

Note that the same reference numerals indicate the same objects throughout the figures.

The mode setting section 21 shown in FIG. 2 can set two modes, a low speed mode and a normal mode, by setting terminals a to c. When setting the low speed mode by shorting the setting terminals a and b, The output is always at the "1" level, and when the setting terminals a and c are short-circuited to set the normal mode, the output is always at the "0" level.

On the other hand, the N0R18a sends out the "1" level when all three inputs are at the O" level, and if even one has the "1" level, the "0" level is sent out. Therefore, the mode setting section 21 is set to a low speed. When set to the mode, "1" level is always sent to one input terminal of AND19.

As a result, one machine cycle (for example, 1 μSEC) of the basic clock (1) is sent out as the machine clock (3) of the liver U1 for all instructions.

If you want to take advantage of the expansion of 2-cycle instructions (5) and 3-cycle instructions (6), set the normal mode to the 4th
As shown in the figure, the machine clock (3) inhibits ■, ■, and ■ with the output signals (“1” level is output) from the 2-cycle instruction (5) and the 3-cycle instruction (6). Sent out.

〔Effect of the invention〕

According to the present invention as described above, when a low-speed machine clock is required, all instructions can be operated with the low-speed machine clock, so that an efficient FIPU can be provided.

[Brief explanation of drawings]

Fig. 1 is a block diagram explaining the present invention in detail, Fig. 2 is a block diagram explaining the present invention in detail, Fig. 3 is a block diagram explaining the conventional example, and Fig. 4 explains the situation of the machine clock. FIG. 5 is a diagram explaining the instruction form. In the figure, 1 is MPU. 11 is an instruction instruction section, 12 is a decoder, 13.15.16 is F,
F. 14, 17.19 is AND, 18.18
a is NOR. 20 is NOT, 21 is a mode setting section,
are shown respectively. 7 sink Otsu 7f) like jLhi 4L ro month storage 5 drawing 2 4 drawing now now Kata book? Tax diagram Figure 5

Claims (1)

[Scope of Claims] In a microprocessor in which the number of instruction execution cycles differs depending on the instruction format, there is a normal mode in which the number of instruction execution cycles for a device controlled by the microprocessor (1) varies depending on the instruction format, and a normal mode in which the number of instruction execution cycles differs depending on the instruction format; A mode setting means (21) is provided which can set the mode to a low speed mode such as one-cycle instruction, and the microprocessor (1)
1. An instruction execution cycle control method characterized in that the one-cycle instruction time is varied in accordance with the device controlled by the system.