JPS6263340A - address conversion circuit - Google Patents

Abstract

PURPOSE:To make address conversion operation after updating an address unnecessary, by performing the updating operation on the displacing section of the address only and specifying the operation of operand fetch and instruction fetch within the area of a main memory indicated by the bit of the displacing section. CONSTITUTION:The address conversion circuit is provided with a program counter 5, operand address register 6, and operator 7 for the increment and decrement of the program counter. The j, e, f, g, and h of the figure respectively represent an operation mode signal for switching mode, base address input signal of an instruction or operand, displacing address input signal of an instruction or operand, and high-order bit line of an address bus, and low-order bit line of the address bus. Therefore, the extent for making access to a main memory following instruction fetch and operand fetching operations in the address conversion mode is specified with the extent indicated by the bit of a displacing section, with the address indicated by the base section of the operand address register 6 set at the leading edge.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an address conversion circuit, and particularly to an address conversion circuit for performing address emulation between models having different numbers of address bits.

[Background of the invention]

When a new computer is developed and replaced with an old model, an emulation machine is used to inherit the programs developed and used on the old model. There are various emulation methods, from those that fully use hardware such as microprograms to those that use a combination of hardware and software. When performing emulation using hardware, it is necessary to switch between a native mode in which the new machine, ie, the host computer, operates as it should, and an emulation mode, in which the old model machine, ie, the target computer, operates. For example, if an older machine uses 16-bit addresses and a newer machine uses 24-bit addresses, the 16-bit word address must be converted to a 24-bit byte address, and when used for either , the address conversion circuit is switched and used. As shown in Figure 3 (, ), the 24-bit address space exists at addresses 0 to 224, and the 16-bit address space is included as part of the 24-bit address space, so the emulation mode is within the shaded range. Limited.

Emulation mode program counter (PC
When specifying the range of this emulation mode by EM), the number of address bits used is part of a 24-bit address space, so a 24-bit address is required instead of a 16-bit address.

Conventionally, in the Natres conversion method described in JP-A-57-161941, as shown in FIG. 3(b), a plurality of program counters (PCEM, PCNT) are provided,
Addresses are converted by switching using a pointer or mode bit. In other words, two 24-bit program counters are installed, one for emulation (PCEM) and one for native (PCNT), and the output of the flip-flop for mode switching is set to emulation mode (EM).
OD), the contents of the PCEM counter are output to the address bus, and when the output of the flip-flop is in native mode, the contents of the PCNT counter are output to the address bus.

Furthermore, in the address conversion method described in Japanese Patent Application Laid-open No. 57-105043, as shown in FIG. Addresses are translated by concatenating bits. That is,
A 24-bit program counter for native mode is divided into upper 8 bits and lower 16 bits, and the contents of the lower bits are shared during emulation mode.

In the emulation mode, a value is set in an 8-bit register for the extension bits, and this specifies which part of the emulation address space is divided into 16 bits.

4th ri! i is a block diagram showing the address control section of FIG. 3(c) in more detail. In Fig. 4.

1 is the base address register that sets the emulation mode extension bit, 2 is the native mode program address register divided into upper and lower bits, 3 is the operand address register divided into upper and lower bits, and 4 is the next address. 8 is a selection circuit that selects one of the outputs of registers 1, 2 and 3, e, d
are the upper and lower address buses. First, in the native mode, the value of the program address register 2 is incremented by 1 by the adder 4 and the lower bits are output to the lower address bus d, and the upper bits are selected by the selection circuit 8 and output to the upper address bus C. Next, in order to read the operand from the main memory, the operand address register 3i value is set, the lower bits are output to the address bus d, and the upper bits are selected by the selection circuit 8 and output to the address bus C. In addition, in emulation mode, only the lower bit is set in program address register 2, this is incremented by 1 by adder 4, and then output to address bus d, and the extended bit is set to base address register 1. is selected by the selection circuit 8 and output to the address bus C.

For operand addresses, same as before. In this manner, address conversion is performed by switching the base address portion of the calculation result using the selection circuit 8. As described above, all conventional address translation circuits require dedicated hardware registers, which increases costs and increases the size of the device.

[Purpose of the invention]

An object of the present invention is to improve such conventional problems and provide an address translation circuit that can perform address translation to emulation mode without providing a dedicated hardware register for storing address bits for translation. There is a particular thing.

[Summary of the invention]

In order to achieve the above object, the address translation circuit of the present invention includes a program counter that indicates an instruction word address, and an operand address that indicates the address of an operand necessary for executing the instruction word read by the program counter. The main memory address control circuit has a program counter and an operand address register each divided into two fields, a base part and a displacement part, and in emulation mode, the displacement part output of the program counter and the operand address register. The main memory is accessed as an instruction word address, and only the displaced part of the operand address register is updated as an operand address.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to one drawing.

FIG. 2 is a diagram for explaining the operating principle of the present invention. In a program storage type computer, the instructions of the program stored in the storage device are retrieved one by one, decoded, and the operation of each instruction is executed repeatedly.
Proceed with the processing instructed by the program. That is, 1
Regarding each instruction, as shown in Figure 2, after reading the instruction (step 10), it is determined whether this instruction requires an operand or not (step 11). If it is an instruction, read the operand from the storage device (step 12), decode the operation part (part 02) of the instruction, and branch to each instruction (step 13).
), execute the operation of each instruction (steps 14-16).

When the execution of the instruction operation is completed, the process returns to step 10 and moves on to reading the next instruction. Computer processing progresses in this order, but in conventional address translation circuits,
As shown in FIG. 4, an address is divided into a base part and a displacement part, and when converting an address, the contents of the base part are replaced. However, the address when reading the instruction in FIG.

Only the lower bits of the program address register 2 and the value of the base address register 1 in FIG. 4 are set, and the operand address register 3 is not used. In FIG. 2, when it is determined that an operand is necessary, an address value is set in the operand address register 3 for reading the operand. In the present invention, redundant hardware is reduced. Therefore, hardware that is not used when reading instructions is used.

We focused on the fact that the base address register 1 can also be used as the operand address register 3. Furthermore, it has been noted that if the base address register 1 is removed and the instruction read operation and operand read operation are performed at different times, the selection circuit 8 in FIG. 4 becomes unnecessary. That is, in the present invention, the address register itself is
Divide into base part and displacement part and update during address translation mode.

Using the method of performing only the displacement part, the base part is set to the base part of the operand address register.

FIG. 1 is a block diagram of an address translation circuit showing one embodiment of the present invention. In FIG. 1, as is clear from a comparison with FIG. 4, the base address register 1 and selection circuit 8 in FIG. 4 are removed, and the native mode and emulation mode are switched by the output j of the flip-flop. , and connect the output of the arithmetic unit 7 and the output of the operand address register 6 directly to the address bus,
They are different in that they do

In FIG. 1, 5 is a program counter, 6 is an operand address register, 7 is an arithmetic unit for incrementing or decrementing the program counter, j is an operation mode signal for mode switching, e is an instruction or operand base address input signal, f is the instruction or operand displacement address input signal, g is the upper bit line of the address bus, and h is the lower bit line of the address bus.

First, in the native mode, the operation mode signal j is
0'', the setting to the operand address register 6 and the output of the arithmetic unit 7 are not prohibited. Therefore, the base address of the operand is set and the arithmetic unit 7 is not prohibited.
The base address part of is also connected to address bus g and output freely. In this case, in order to read the instruction, the program counter 5 receives the base address input signal e,
and a displacement address input signal f, and is connected to the arithmetic unit 7. All addresses of calculation results are output.

The base part is connected to a base address bus g, and the displacement part is connected to a displacement address bus h, and the signals are sent to the main memory. Next, since the operation mode signal j is re Ou when reading the operand in native mode,
After the base address and displacement address are set in the operand address register 6, the base address bus g
is output to the displacement address bus h and sent to the main memory.

Next, in the address conversion operation mode, that is, in the emulation mode, since the operation mode signal j is 11171, setting of the base address in the operand address register 6 is prohibited, and the output of the base address from the arithmetic unit 7 is prohibited. It is forbidden. That is, in the emulation mode, the base address of both address registers 5 and 6 is fixed, and only the displacement address is updated. Therefore, during emulation mode,
For both the instruction address and the operand address, only the output signal of the displacement address section is connected to the displacement address bus h, and only the base address of the operand address register 6 is connected to the base address bus g. First, when reading an instruction, a value indicating the address space area of the emulation machine to be selected from among multiple areas divided for each displacement address in the native machine's address space, that is, a value that is conventionally set in the base address register The first value obtained is set in the base address section of the operand address register 6 by the base address input signal j. Then, during the emulation mode, storage to that portion is inhibited by the operation mode signal j. Further, only the displacement address f is set in the program counter 5 and connected to the operation @7. As for the calculation result by the calculator 7, only the displacement address is connected to the displacement address bus h, and the output of the base address is prohibited from being output to the bus g by the operation mode signal j. Then, the base address is output from the operand address register 6 to the bus g.

Next, when reading an operand, the displacement address input signal f is set in the displacement address field of the operand address register 6, the beginning of the address space of the emulation machine is set in the base part, and the displacement address and base The address is output to the displacement address bus h and the base address bus g, sent to the main memory, and used as an access address.

In this way, the access range to the brush memory accompanying the instruction fetch operation and operand fetch operation during the address conversion mode starts from the address indicated by the base part of the operand address register 6, and starts from the address indicated by the base part of the operand address register 6.
Specified within the range indicated by -.

In this way, in this embodiment, the base address register 1 and selection circuit 8 that were conventionally required can be omitted, and the same address translation function can be realized.

〔Effect of the invention〕

As described above, according to the present invention, only the displacement part of the address is updated, and the operand fetch and instruction fetch operations are defined within the area of the main memory indicated by the bits of the displacement part of the address. Therefore, there is no need for a conversion operation after an address is updated, and it is possible to reduce the amount of hardware for address conversion and the operation time of the editing circuit after an address is updated, thereby improving the performance of the processing device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an address conversion circuit showing an embodiment of the present invention, FIG. 2 is a flow chart showing the principle of the present invention, FIG. 3 is an explanatory diagram of a conventional address conversion operation, and FIG. FIG. 2 is a block diagram showing an example of an address conversion circuit. 1: Base address register, 2, 5 Niprogram counter, 3, 6: Operand address register, 4, 7:
Arithmetic unit, 8: selection circuit, C, g: base address bus,
d, h: displacement address bus. Patent applicant Hitachi, Ltd. −,,,'−=,°
,, ,,;,l',,

Claims (1)

[Claims] (1) In a main memory address control circuit equipped with a program counter indicating an instruction word address and an operand address register indicating the address of an operand required to execute the instruction word read by the program counter, each It has a program counter and an operand address register that are divided into two fields, a base part and a displacement part.In emulation mode, the displacement part output of the program counter and the base part output of the operand address register are connected and used as the instruction word address. An address conversion circuit characterized in that it accesses main memory and updates only a displaced portion of an operand address register as an operand address.