JPS6266472A - Clock recovery circuit - Google Patents

Abstract

PURPOSE:To obtain a clock recovery circuit increasing the Q of a resonance circuit without hindrance by providing a comparator receiving an output of the resonance circuit and converting it into a digital signal and a PLL circuit receiving an output of the comparator as a reference signal. CONSTITUTION:When an output level of the resonance circuit 5 is negative, a Schotky diode 3 is biased forward and since the Schottky diode 3 is not conducted until the output level of the resonance circuit 5 exceeds a threshold level of the Schottky diode 3, the resistance of the Schottky diode is several MOMEGA. When the negative output level exceeds the threshold level, the load of the resonance circuit 5 is the sum of the conductive resistance of the Schottky diode and an output resistance of an EOR gate 2, then the load is heavier and the level is clipped near the threshold level. Although the output peak of the resonance circuit 5 is clipped near the threshold level, since the load in this case is light as several MOMEGA or below, a high Q is obtained and the clock component is extracted sufficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a magnetic recording and reproducing device for digital signals, and more particularly to a clock extraction device using a resonant circuit and a phase-locked loop.

[Conventional technology]

Conventionally, this type of clock regeneration circuit extracts a signal α converted into a digital signal and delays this signal by 1/2 of the clock cycle using a delay line 1, as shown in FIG. Shivor (hereinafter abbreviated as FOR) Gate 2
, so that the minimum repetition period of the output pulse of FOR gate 2 is the same as the clock, and then resistor 8,
9 to the resonant circuit 5 tuned to the clock frequency, and converts the output pulse of the FOR gate 2 into a continuous sine wave of the clock frequency, which is further input to the comparator 6.
After being converted into a digital signal, this signal is input to a PLL circuit 7 which uses it as a reference.

As a result, a signal synchronized with the input signal α is output from the PLL circuit 7 as a clock.

[Problem that the invention seeks to solve]

In the conventional clock regeneration circuit described above, if the level of the input digital signal remains high or low for a long time, no pulse is output from the FOR gate, the resonant circuit continues damped oscillation, and the output signal of the resonant circuit becomes noise. I'm drowning.

To improve this, it is possible to reduce the load on the resonant circuit and increase the Q, but since the output impedance of the EX)R gate is low, the load on the resonant circuit is determined by the resistance that connects the FOR gate and the resonant circuit.

If the above-mentioned resistance is increased, the input level of the resonant circuit is lowered by the resistance, so there is a drawback that it cannot be increased unnecessarily.

The present invention solves the above problems and provides a clock regeneration circuit that can increase the Q of a resonant circuit without any problem.

[Means for solving problems]

The present invention provides a digital signal reproducing device including a delay line that delays an input signal by 1/2 of a clock period, an exclusive OR gate that receives the output of the delay line and the input signal, and an exclusive OR gate that delays the input signal by 1/2 of a clock period. Clock regeneration characterized by having a resonant circuit that receives the signal via a Schottky diode, a comparator that receives the output of the resonant circuit and converts it into a digital signal, and a PLL circuit that receives the output of the comparator as a reference signal. It is a circuit.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

FIG. 2 (5) to I are timing charts of the embodiment. In FIG. A FOR gate (FOR gate) 2 and a resonant circuit 5 are connected via Schottky diodes 3 and 4.

In the embodiment, the digitized signal α (see FIG. 2) first enters the FOR gate 2 and the delay line l;
The signal entering delay line 1 is 1/1/1 of the clock period.
2 (Fig. 2 (B)) and is supplied to the other input of the EOR gate 2. The output of the FOR gate 2 (Fig. 2 (c5) It enters circuit 5 and is further added to comparator 6.

The output of the comparator 6 enters a PLL circuit 7, and a clock is output from the PLL circuit 7.

The output of the FOR gate 2 sends out a pulse whose minimum cycle of pulse repetition is the same as the clock, as shown in FIG. 2 cod.

Since the output pulse of the FOR gate 2 has an intermittent part as a clock, it is sent to a resonant circuit 5 which is tuned to the frequency of the clock via Schottky diodes 3 and 4.
into a continuous sine wave with the same frequency as the clock, although there are level fluctuations (Figure 2 (G) and (G))
.

When the output of the FOR gate 2 becomes high level, it exceeds the threshold level of the Schottky diode 3 and drives the resonant circuit 5. However, the drive level of the resonant circuit 5 drops by the threshold level of the Schottky diode 3 (approximately 0.2 to 0.5 V). At this time, since the Schottky diode 3 is biased in the forward direction, the resistance of the Schottky diode 3 is approximately several tens of ohms.

E) When the output of the OR gate 2 is at a low level, the resonant circuit 5 performs damped oscillation. When the output level of the resonant circuit 5 is positive, the Schottky diode 3 is biased in the opposite direction, so its resistance becomes several MΩ or more.

When the output level of the resonant circuit 5 is negative, the Schottky diode 3 is forward biased, but the Schottky diode 3 is forward biased until the output level of the resonant circuit 5 exceeds the threshold level of the Schottky diode 3. Since there is no conduction, the resistance of the Schottky diode is several MΩ.
That's all.

When the negative output level of the resonant circuit 5 exceeds the threshold level, the load of the resonant circuit 5 becomes the sum of the conduction resistance of the Schottky diode (several tens of ohms) and the output resistance of the FOR gate 2 (about 100 ohms), so the load increases. becomes heavy and clips around the threshold level.

Although the peak of the output of the resonant circuit 5 is clipped near the threshold level, the load at this time is light, several MΩ or more, so a high Q can be obtained and the clock component can be sufficiently extracted.

The output of the resonant port [5 is converted into a digital signal g by a comparator 6, and then this signal g (using FIG. 2 (0) as a reference and a PLL circuit having a digital phase comparator j!
87. A signal h (FIG. 2 (El)) synchronized with the input signal α is output from the PLL circuit 7 as a clock.

In the conventional method, when a digital signal with a period 32 times that of the clock is input, the output of the resonant circuit shows a large attenuation, and three peaks of the sine wave are counted as shown in Figure 4 (B). Afterwards, I get drowned out by the noise.

According to the present invention, although there is a level drop in the output of the resonant circuit due to the Schottky diode as shown in FIG. 4 (0), the attenuation remains within about 70%.

〔Effect of the invention〕

As explained above, the present invention has the effect of increasing the Qe of the resonant circuit by connecting the output of the FOR gate and the resonant circuit with a Schottky diode.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 (5) to
The figures are time charts showing the operation of the above circuits, respectively.
FIG. 3 is a block diagram of the conventional embodiment, and FIG. 4 (0) is a characteristic diagram showing the output of the resonant circuit of this embodiment and the output of the conventional resonant circuit. 1...Delay line 2. ... Exclusive or gate 3.4 ... Schottky diode 5.
...Resonance circuit 6...Comparator 7...PL
L times M8.9...Resistance

Claims (1)

[Claims] (1) In a digital signal reproducing device, a delay line that delays a digitized input signal by 1/2 of a clock period, an exclusive OR gate that receives the output of the delay line and an input signal, and a It is characterized by having a resonant circuit that receives the output of the agate via a Schottky diode, a comparator that receives the output of the resonant circuit and converts it into a digital signal, and a PLL circuit that receives the output of the comparator as a reference signal. clock regeneration circuit.