JPS6268308A - MOS amplification output circuit - Google Patents

Abstract

PURPOSE:To increase a voltage fed to an output MOSFET by using the 2nd conduction MOSFET whose gate electrode receives an impurity at opposite conduction that to the source and drain and formed as a current mirror form so as to amplify the drain output of the 1st conduction type differential MOSFET. CONSTITUTION:In order to increase an injected voltage fed to output MOSFETs Q1, Q2 the drain output of differential MOSFETs Q5, Q6 is amplified further by the next amplifier circuit. P-channel MOSFETs Q7, Q8 whose gate electrode receives an N<+> impurity being opposite conduction type to that of the source and drain have a large threshold voltage and the constituted as a current mirror form. The source of the MOSFETQ7 is connected to the drain of the differential MOSFETQ5 and the source of the MOSFETQ8 is connected to the drain of the differential MOSFETQ6. The drain of the MOSFETs Q7, Q8 is provided respectively with constant current MOSFETs Q11, Q13.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an amplification output circuit composed of MOSFETs (insulated gate field effect transistors), and relates to a technology that is effective when used in analog amplification output circuits. .

[Background technology]

As an analog amplification output circuit composed of MOS FETs, a circuit as shown in Fig. 3 is used, for example, in the IEE Journal of Solid State Circuits (IEE Journal of Solid State Circuits
olid-3tate C1rcuits) Vo
l 5C17Nl16, (December 1982) page 9
69-982.

The output of the differential amplifier circuit is the P channel output MO as it is.
Drives SFETQ40. The output of the differential amplifier circuit is connected to the MOSFET Qa 8 that constitutes the source follower circuit.
The level is shifted by the above output MOSFETQ4.
It drives an N-channel output MOSFET Q41 which is in a complementary push-pull configuration with 0.

In this circuit, differential amplification MOSFETQ34, C
Since an active load circuit in the form of a current mirror is provided at the drain of 35, both power signals IN(-), (+)
When no signals are equal, both differential MOSFETs Q34. Q3
The drain currents of 5 become equal, pseudo MOSFET
Q37 and output MOSFET Q40 operate in the same way as a current mirror circuit, so they have relatively good accuracy (bias current (
(idling current) can be set.

However, when driving a DC load with a relatively low resistance value, a problem arises in that the output dynamic range is narrowly limited. The reason for this is as follows. The maximum value in the negative direction of the drain output voltage of differential MOSFET Q35 is the condition for differential MOSFET Q35 to perform its amplification action.
Since it can only change within the saturation region of FETQ34°C35, it is limited by the threshold voltage of differential MOSFETQ35, and the maximum value in the positive direction is
It is limited by the threshold voltage of SFETQ37. Therefore, the output dynamic range becomes small due to a lack of transfer voltage (drive voltage) to the output MOSFETs Q40 and C41. That is, when viewed from the output circuit side, the channel conductivities of the output MOSFETs Q40 and C41 are β1 and β2 (βl-β2), respectively, the captured voltage from the differential amplifier is Δ, and the output MOS
FETQ40. The drain current of Q41 is Io, the load resistance RL connected to the output terminal OUT is the load resistance R
The output voltage Vout generated at L is expressed by the following equation 11.

VouL --RL ((0]゛+aτ)×Δ×agoτ) −(1) As is clear from formula t1), in order to increase the amplitude of the output voltage Vout, the resistance RL must be increased. If the resistance value is relatively small, it may be possible to increase the size (β1, β2) of the output MOSFETs Q40 and C41 to allow a large current Io to flow, but in this case, the element size will increase and the current consumption will increase. will increase.

[Purpose of the invention]

The purpose of this invention is to provide an output MOS of relatively small size.
The object of the present invention is to provide a MOS amplification output circuit having a large current drive capability using FETs.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the drain output of a first conductivity type differential MOSFET is amplified by a second conductivity type MOSFET whose gate electrode is doped with an impurity of a conductivity type opposite to that of the source and drain, and which has a current mirror configuration. , output MOSFE
This increases the transfer voltage supplied to T.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the present invention. Each circuit element in the figure is a well-known 0MO5 (complementary MO
S) formed on a single semiconductor substrate, such as single crystal silicon, by integrated circuit manufacturing techniques. In the same figure, the MOSFET with an arrow added to the channel part
is of P-channel type. In addition, MOSFETQ7, which is expressed with a thicker gate electrode. Q8 etc. are MOSs into which impurities of conductivity type opposite to the gate source and drain are introduced.
For example, MOSFETQ? .

Q8 is a P-channel MOSFET in which an N0 type impurity is introduced into the gate electrode.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal N-type silicon. P channel MOS
The FET has a source region, a drain region formed on the surface of the semiconductor substrate, and a gate made of polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region with a thin gate insulating film interposed therebetween. Consists of electrodes. The N-channel MOS FET is formed in a P-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of P-channel MOS FETs formed thereon. The P-type well region constitutes the base gate of the N-channel MOSFET formed thereon.

The gates of the N-channel differential amplification MOSFETs Q5 and Q6 are respectively coupled to input terminals (-) and (+). An N-channel MOSFET QI 2 through which a bias current flows is provided between the common source of the differential amplification MOSFET Q5゜Q6 and the negative voltage terminal -■ (the ground potential of the circuit in a single power supply system consisting of a positive power supply voltage). It will be done. The differential amplification MOSFETQ5. Between the drain of Q6 and the positive voltage terminal +■, there is a P-channel MOSFET Q3. Q4 is provided as a load means.

In this embodiment, in order to increase the output dynamic range, in other words, the output MOSFETs Q1 and Q2
In order to increase the amplitude of the transferred voltage supplied to the transistors, the drain output of the differential MOSFET Q5°Q6 is further amplified by the following amplifier circuit.

The P-channel MOS FETs Q7 and Q8 are made to have large threshold voltages by introducing an N0 type impurity, which is a conductivity type opposite to that of the source and drain, into their gate electrodes. These MOSFETs Q7 and Q
8 are connected in a current mirror configuration. MOSFETQ7
The source of MOSFETQB is coupled to the drain of differential MOSFETQ5, and the source of MOSFETQB is coupled to the drain of differential MOSFETQ6. These MOSFETs Q7 and Q
Constant current MOSFBT QI 1 and Q1 are connected to the drain of 8.
3 are provided respectively.

Although not particularly limited, a bias current of 21o flows through the constant current MOSFETQ12, and a bias current of 21o flows through the constant current MOSFETQ12.
and Q13 are set so that a bias current of Io flows through them, respectively.

Of the output voltage in the differential amplifier section of this embodiment, in other words, the drain output voltage of MOSFETQB,
The maximum positive value is determined by the threshold voltage -Vt8 from the saturation condition of MOSFETQB. MOSFETQ
B has an N0 type impurity introduced into its gate electrode as described above. As a result, the threshold voltage Vt8 of the MOSFET QB is made to have a value larger by about 1.degree. 2 V than the threshold voltage of the P-channel MOSFET into which P-type impurities are introduced. Accordingly,
The maximum voltage to the positive side of the drain output voltage can be increased. Also, its source potential is positive power supply voltage +
The threshold voltage Vt8 slightly increases due to the substrate effect caused by the lower potential than V.

On the other hand, differential MOSFETQ5. By setting the potential of the well region where Q6 is formed to a negative voltage -■, the common-mode input voltage range can be expanded to the positive power supply voltage +■. M
The maximum value on the negative side of the drain output of OSFETQB can be as large as the negative power supply voltage -2, assuming that the source-drain voltage (residual voltage) in MOSFETQ13 is -0. As a result, the output M
This allows the transfer voltage (drive voltage) supplied to the gates of OSFETQI and Q2 to be increased. That is,
This allows the transfer voltage Δ in the equation (1) to be increased.

In addition, the above amplification MOSFET Q? , QB is a differential MOS
FE'l'Q5. By receiving the drain output voltage of Q6 at the source and forming the output voltage from the drain,
It performs a voltage amplification operation similar to that of a gate-grounded amplification MOSFET.

The above current mirror type MOSFET Q7. Of Q8,
The drain voltage of MOSFETQ8, which has an output expansion of 1, is
Since the power supply voltage (+V, -V) is close to the midpoint voltage,
If left as is, a large through current will flow through the output MOS FETs Ql and Q2. Therefore, in order to reduce the through current in MOSFETs QI and Q2, the following level shift circuit is provided. On the one hand, the drain output of MOSFETQ8 is connected to the above MOSFETQ8 and 14t.
A P-channel MOSFET Q9 with a Q structure and a P-channel constant current MOSFET Q provided at its source.
The signal is transmitted to the gate of the P-channel type output MO8FETQI via a source follower circuit consisting of 14 circuits. On the other hand, the drain output of the MOSFET Q8 is N
Channel MOSFETQIO and N-channel constant current MOSFETQ1 provided at its source
The signal is transmitted to the gate of the N-channel type output MOSFET Q2 via a source follower circuit consisting of 5.

Assuming that the output voltage level-shifted by the MOSFET Q9 is Vp, this level-shifted output voltage Vp is obtained by the following equation (2).

Vp-Vl-VLO+, Fi-7Q14/#9
-(2) Here, ■1 is the above MOSFETQ
Vt9 is the drain output voltage of MOSFETQ
9 threshold voltage, I Ql4 is MO5FE'rQ1
4, β9 is the constant current formed by MOS F E
This is the channel conductivity of TQ9.

Assuming that the output voltage level-shifted by the MOS FETQ 10 is Vn, this level-shifted output voltage Vn is obtained by the following equation (3).

Vn-V 1- Vt1O+ 21Q15 /I 1
0-(3) C"t', V tlO is MOSFETQI
The threshold voltage of O, IQ15, is MOSFETQ15
Constant current formed by β10 is MOS F ETQ
10 channels #electricity.

In addition, the N-channel Mo3FETQ21 and the P-channel MoSFETQ22 connected in series with the MOSFETQ9 and QIO, respectively, keep the low level of the control signal i during the power-down operation described later, in other words, when not performing the amplification operation. , PD are both turned off by the high level of PD. This aims to reduce power consumption.

Furthermore, a MOSFET as a phase compensation circuit is connected between the drain of the amplification MOSFET Q8 and the output terminal OUT.
QI 6. Ql 7, capacitor C and MOSFETQ
1 B, Ql 9 are provided. The above MOS FET
Among them, P-channel Mo5FETQ17 and Ql9 are:
By constantly connecting its gate to the negative voltage terminal -■, it acts as a resistance element, and the N-channel MO
SFETQI6 and Ql8 act as resistance elements by having their gates constantly connected to the positive voltage terminal +■.

Further, in order to lower the offset voltage of the output, a constant current is generated by each of the constant current MOSFETs QI 1 to Ql 5 based on a bias current generated by the next bias circuit.

Here, the bias current formed by the bias circuit is Ib, constant current 1o-α1・Ib, constant current I Ql4
−α2・Ib, constant current f Ql5−α3・rb, P channel MOSFET QI and N
The current flowing through channel MOSFET Q2 is expressed as rp and In
Then, these currents 1p and In are expressed as follows.

Ip-β1 (fi7T-< F7 ■ lago + 51 fufu]
)]2・I b =<4)In-β2 ((
+V+Vtt+Vt8-V-VtlO) 10F "db)-
(p-Foucault F7T+ 577-)]2・Ib(51 In order to make the offset voltage zero, the above current Ip and In should be made equal. The conditions for this are expressed by the following equation (6). be done.

(+V + Vt4+ Vt8- V
-Vt1O)
131 If the right (lower) side of equation (6) can be made a constant that does not depend on the power supply voltage and threshold voltage, the condition for zero offset is as follows.
It can be made independent of power supply voltage and threshold voltage. Therefore, the bias circuit is constructed in the form shown on the right side of equation (6).

That is, MOSFETQB1 corresponding to MOSFETQ4 in the differential section, MOSFETQB2 corresponding to MOSFETQ8, MOSFETQB3 corresponding to MOSFETQIO, and N-channel M
By connecting OSFETQB 4 in series, bias current Ib
It forms the The above MOS FETQ
B4 is an N-channel 7-channel constant current MOSFET QI
1-Ql Current mirror connection with 3 and Ql5. Further, the P-channel MOSFET QB1 is connected in a current mirror to a P-channel type constant current MOSFET QI4.

Here, in order to achieve zero offset, the bias current is 1
b is set as shown in the following equation.

-V t (lB4) ÷ [(1/F possible) + (1/(wealth) +
C1/ q> + < 1 / $> ) −(
By setting the bias current rb in this way, the conditions for setting the current 1p""In as described above can be obtained from the following equation (8).

As is clear from equation (8), it is possible to set the offset voltage to zero depending on the size ratio of the MOSFETs.

In this embodiment, although not particularly limited, a power-down switch MOSFET is added in order to reduce current consumption when no amplification operation is performed. An N-channel MOSFETQ20 is inserted in series in the bias circuit, and this MOSFETQ20 is connected to the control signal PD.
It is turned off by the low level of . Also, the output MO
Between the gates and sources of SFETQI and Q2, there are a P-channel MOSFET Q23 that is turned on by the low level of the control signal PD, and an N-channel MOSFET Q24 that is turned on by the high level of the control signal PD.
are provided respectively. Depending on the ON state of these MOSFETs Q23 and Q24, the output MOSFETs QI and Q2
As a result, the source and gate of the output MOS F are shorted.
ETQ 1 and Q2 are both turned off. Above system m
tx PD is set to low level and PD is set to high level during power down mode. As a result, when in power-down mode, differential increase/opening, bias circuit,
The DC current consumed in each of the level shift circuit and output circuit can be reduced to zero.

〔effect〕

fl) A current mirror whose gate is made to have a large threshold voltage by introducing an impurity of conductivity type opposite to that of the source and drain of the drain output of the second conductive type differential MOS FET. Amplification of the second conductivity type of the form &i
03 F E By outputting through "I", the output amplitude can be increased. As a result, it is possible to increase the transfer voltage to the complementary output MOSFET, thereby providing the effect that a large output voltage can be supplied to a DC load having a relatively small resistance value.

(2) In order to increase the signal amplitude, a MOS FET is used that has a gate electrode into which impurities of the opposite conductivity type as the source and drain are introduced, so the gate '11is is of the opposite conductivity type. It can be formed by the same process as the gate electrode of the MOSFET. This allows, for example, a MOS with a high threshold voltage.
In order to form F E 'T', the above signal amplitude can be increased without increasing the number of man-hours compared to the method of introducing impurities by ion implantation into the channel region or utilizing the substrate bias effect. This has the effect of being able to.

(3) By increasing the transfer voltage to the output MOSFET, for example, a speaker, which has a relatively low resistance value,
Can directly drive transformers, etc. This eliminates the need for a buffer amplifier to drive these loads, resulting in the effect that the number of external components can be reduced.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in a differential LIJ width circuit, in order to increase the power supply ripple rejection rate,
Current mirror type MOSFET? , an additional circuit such as a capacitor may be provided between the gate of Q8 and the fourth ground point of the circuit.
The conductivity types of S F E 1' may be reversed in the circuit shown in FIG. 1, depending on the polarity of the power supply voltage used. The bias circuit may be of any type as long as it forms a constant current b1 and supplies a bias current to the differential amplifier circuit or level shift circuit using a laminar flow mirror circuit.

[Application field]

This invention is applicable to a kneader/decoder (GO) used as an MO8 amplification output circuit, for example, in a digital telephone exchange.
MOSJ built into DEC! It can be widely used in J-width output circuits, etc.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of the prior art. It is a 7-width output output circuit diagram. ■＞G

Claims (1)

[Claims] 1. Differential MOSFETs Q5 and Q6 of the first conductivity type, the drain outputs of these differential MOSFETs Q5 and Q6 are supplied to the source, and the gate thereof is the source, and an impurity of the opposite conductivity type to the drain is introduced. MOSFETs Q7 and Q8 of a second conductivity type, each having a gate electrode formed in a current mirror configuration;
The common source of the above MOSFETQ5 and Q6 and the above MOSFET
The constant current source circuits provided at the drains of SFETQ7 and Q8, the level shift circuits that level shift the drain outputs of the output side MOSFETs among the MOSFETs Q7 and Q8, and the output voltages through these level shift circuits. A MOS amplification output circuit comprising driven complementary push-pull output MOSFETs Q1 and Q2. 2. The above level shift circuits each have the above MOSFE
A first source follower circuit consisting of MOSFETs similar to TQ7 and Q8 and a constant current source circuit, and a differential MOSFET
The MO according to claim 1, characterized in that it is constituted by a second sof follower circuit consisting of MOSFETs similar to Q5 and Q6 and a constant current source circuit.
S amplification output circuit. 3. Each of the above constant current circuits includes MOSFETQB3 and MOSFETQ7 similar to the above differential MOSFETQ5 or Q6.
Or MOSFET QB2 similar to Q8, differential MOSFET
A MOSFET QB1 similar to the second conductivity type load MOSFET provided at the drains of TQ5 and Q6 and a MOSFET similar to the first conductivity type MOSFET constituting the constant current source circuit.
3. The MOS amplification output circuit according to claim 1, wherein SFET QB4 forms a constant current according to a bias current formed by a bias circuit connected in series.