JPS627166A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS627166A JPS627166A JP60144743A JP14474385A JPS627166A JP S627166 A JPS627166 A JP S627166A JP 60144743 A JP60144743 A JP 60144743A JP 14474385 A JP14474385 A JP 14474385A JP S627166 A JPS627166 A JP S627166A
- Authority
- JP
- Japan
- Prior art keywords
- electron beam
- insulating film
- semiconductor device
- gate insulating
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electron Beam Exposure (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置の製造方法に係り、特に電子線直接
描画法もしくはX線露光法を用いた半導体装置の製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device using an electron beam direct writing method or an X-ray exposure method.
電子線直接描画法やX線露光法は、1μm以下の微細パ
ターンを形成する上で紫外線露光法に変わる有効な手段
である0例えば電子線直接描法に関しては、ジャーナル
・オブ・バキューム・ソサイテイ(J、 Vac、 S
ci、 Technol、 )上1927(1981年
)における岡崎(S、 Qkazaki)らによるrn
−MOSの電子線直接描画および重ね合せ精度と線幅精
度の解析J (Electron−beam dir
ectwriting of n−MOS devic
es and analysis ofoverlay
and 1inevidth accuracies
)と題する文献において論じられている。該文献内でも
論じられているように、従来、電子線直接描画法を用い
て製造したMOSトランジスタにおいては、紫外線露光
法を用いて製造したMOS)−ランジスタに比べて長期
信頼度が低いという問題があった。Electron beam direct writing method and X-ray exposure method are effective means to replace ultraviolet exposure method in forming fine patterns of 1 μm or less. , Vac, S.
rn by S. Qkazaki et al. in ci, Technol, ) supra 1927 (1981).
-Electron-beam dir writing of MOS and analysis of overlay accuracy and line width accuracy J
ectwriting of n-MOS device
es and analysis of overlay
and 1inevidth accuracies
) is discussed in the paper entitled: As discussed in this document, there is a problem in that MOS transistors manufactured using the electron beam direct writing method have lower long-term reliability than MOS transistors manufactured using the ultraviolet exposure method. was there.
本発明の目的は従来に比べて長期信頼度が向上した。電
子線直接描画法もしくはX線露光法を用いて信頼性の高
い半導体装置を製造できる方法を提供することである。An object of the present invention is to improve long-term reliability compared to the conventional technology. An object of the present invention is to provide a method for manufacturing a highly reliable semiconductor device using an electron beam direct writing method or an X-ray exposure method.
MOSLSIの高性能化、高集積化に伴い、そのゲート
寸法は年々微細化されている。それに伴い、MOSLS
Iの製造においては、紫外線を用いた露光法から、より
微細なパターンが解像できる電子線直接描画法もしくは
X線露光法が使われるようになっている。しかし、電子
線直接描画法もしくはX線露光法を用いたMo8LSI
は紫外線露光法を用いたMo5LSIに比べて長期信頼
度が低いという問題があった。その−例を第2図を用い
て説明する。−同図はlMo5トランジスタに所定のD
Cバイアスを印加しておいたときの伝達、コンダクタン
スg、mの時間変化を表わしている。MOSトランジス
タはチャネル長2μm、チャネル幅15μm、酸化膜厚
20nmである。ドレインに8v、ゲートに4V、ソー
スにOV基板に一3vのDCのバイアスを印加し、一般
的な動作条件よりも高いドレイン電圧により特性劣化を
加速させた時の、gmの劣化率Δg m/ g m、
(g maはDCストレス印加前のgm値)を調べたも
のである。同図直線(a)は電子線直接描画法を用いて
製造したMoSトランジスタの実験結果であり、同図真
線(b)は紫外線露光法を用いて製造したMoSトラン
ジスタの実験結果である。同図より、電子線直接描画法
を用いた場合、特性劣化が3桁も早く、長期信頼度が低
いことがわかる。その原因としては、電子線直接描画法
で照射された高エネルギーの電子線によりゲート酸化膜
に大量の中性トラップが形成され、トランジスタの動作
中に発生したホットキャリアが除々にSin、 / S
i界面近傍のゲート酸化膜中の中性トラップに捕獲さ
れ、しきい値電圧の変動、伝達コンダクタンスの劣化を
引き起こすと考えられる。そこで、酸化膜質を種々に変
化させて実験検討したところ、酸化膜を熱窒化させた酸
窒化膜をゲート絶縁膜とした時にgmの時間変化を低く
抑えられることを新たに発見した。第1図に結果の一例
を示す、同図(a)は従来の酸化膜をゲート絶縁膜にし
たMo8)−ランジスタを電子線直接描画法で形成した
場合の、同図(b)は酸窒化膜をゲート絶縁膜にしたM
OSトランジスタを電子線直接描画法で形成した場合の
同図(b)は酸窒化膜をゲート絶縁膜にしたMOSトラ
ンジスタを電子線直接描画法で形成した場合のDCスト
レス試験結果である。トランジスタの仕様及びDCスト
レス条件は第1図で説明したものと同様である。従来の
酸化膜を用いたものに比べ、酸窒化膜を用いたものはg
mの劣化が少なく、長期信頼度に優れていることがわか
る。オージェ電子分光法により酸窒化膜の深さ方向の元
素プロファイルを調べたところ、SiO,/Si界面に
窒素のパイルアップが観測され、この窒素が界面特性の
安定性に寄与していると考えられる。As MOSLSIs become more sophisticated and highly integrated, their gate dimensions are becoming smaller year by year. Along with this, MOSLS
In the production of I, the exposure method using ultraviolet rays has been replaced by an electron beam direct writing method or an X-ray exposure method that can resolve finer patterns. However, Mo8LSI using electron beam direct writing method or X-ray exposure method
The problem was that long-term reliability was lower than that of Mo5LSI using ultraviolet exposure. An example thereof will be explained using FIG. - The figure shows a given D for the lMo5 transistor.
It shows the time change of transmission and conductance g and m when C bias is applied. The MOS transistor has a channel length of 2 μm, a channel width of 15 μm, and an oxide film thickness of 20 nm. When applying a DC bias of 8 V to the drain, 4 V to the gate, and -3 V to the OV substrate to the source, and accelerating characteristic deterioration with a drain voltage higher than the general operating conditions, the deterioration rate of gm Δg m/ g m,
(gma is the gm value before application of DC stress). The straight line (a) in the figure is the experimental result of a MoS transistor manufactured using the electron beam direct writing method, and the true line (b) in the figure is the experimental result of the MoS transistor manufactured using the ultraviolet exposure method. From the same figure, it can be seen that when the electron beam direct writing method is used, the characteristic deterioration is three orders of magnitude faster and the long-term reliability is low. The reason for this is that a large amount of neutral traps are formed in the gate oxide film by the high-energy electron beam irradiated by the electron beam direct writing method, and hot carriers generated during transistor operation gradually become Sin, /S.
It is thought that this is trapped in a neutral trap in the gate oxide film near the i-interface, causing fluctuations in threshold voltage and deterioration in transfer conductance. Therefore, after conducting experiments with various oxide film qualities, it was newly discovered that when an oxynitride film obtained by thermally nitriding an oxide film is used as a gate insulating film, the time change in gm can be suppressed to a low level. Figure 1 shows an example of the results. Figure 1 (a) shows the case where a Mo8)-transistor with a conventional oxide film as the gate insulating film was formed by the electron beam direct writing method, and Figure 1 (b) shows the case of using oxynitride. M with film as gate insulating film
FIG. 2B shows the results of a DC stress test when an MOS transistor is formed using an oxynitride film as a gate insulating film and is formed using an electron beam direct writing method. The transistor specifications and DC stress conditions are the same as those described in FIG. Compared to those using conventional oxide films, those using oxynitride films have a lower g
It can be seen that the deterioration of m is small and the long-term reliability is excellent. When the elemental profile in the depth direction of the oxynitride film was investigated using Auger electron spectroscopy, nitrogen pile-up was observed at the SiO, /Si interface, and this nitrogen is thought to contribute to the stability of the interface properties. .
以下1、本発明の第1の実施例を第3図を用いて説明す
る。同図は、製造したMoSトランジスタの断面模式図
である。該MOSトランジスタの製造にあたっては、ゲ
ート絶縁膜の形成法を除いて、従来技術を用いている。The first embodiment of the present invention will be described below with reference to FIG. This figure is a schematic cross-sectional view of the manufactured MoS transistor. In manufacturing the MOS transistor, conventional techniques are used except for the method of forming the gate insulating film.
P型Si基板1の表面に素子分離用絶縁膜2を形成した
後、ゲート絶縁膜3を形成した。ゲート絶縁膜3の形成
は次のように行った。シリコンウェハをHF:H,O=
1:10のエッチ液で60秒エッチし、純水でエッチ液
を除去した後、直ちに拡散炉にそう入し、熱酸化を行っ
た。熱酸化は1000℃の温度で、流入ガスはo2:N
、=1:1 の条件で25分間行い、約21nmの熱酸
化膜を形成した。続いてHF : H,O=1 :99
のエッチ液で熱酸化膜を20秒間エッチし。After forming an element isolation insulating film 2 on the surface of a P-type Si substrate 1, a gate insulating film 3 was formed. The gate insulating film 3 was formed as follows. Silicon wafer HF:H,O=
After etching with a 1:10 etchant for 60 seconds and removing the etchant with pure water, it was immediately placed in a diffusion furnace to perform thermal oxidation. Thermal oxidation is at a temperature of 1000°C, and the incoming gas is o2:N
, = 1:1 for 25 minutes to form a thermal oxide film with a thickness of about 21 nm. Then HF:H,O=1:99
Etch the thermal oxide film for 20 seconds with the etchant.
純水でエッチ液を除去した後、直ちに拡散炉にそう人し
て熱窒化を行う、熱窒化は950℃の温度で、流入ガス
はNH3:3 Q /winの条件で10分間行い、2
0nmのシリコン酸窒化膜を形成し、ゲート絶縁膜とし
た。しかる後に、ポリSiゲート4を形成し、イオン打
込みによりソース、ドレイン拡散層5を形成してMOS
トランジスタを作成した。さらに、層間絶縁膜6,8お
よびAfi配線7.9を形成することにより、第3図に
示す構造のMO5型半導体装置を製造した。製造に用い
たリソグラフィー技術は全て電子線直脱描画法で行った
。電子線の加速電圧は30kVであった。本杭で形成し
たMOSトランジスタのgmのDCストレスにより時間
変化が前述の第2図に示した(b)である。MOSトラ
ンジスタはチャネル長2μm、チャネル幅15μmであ
る。ゲート絶縁膜として熱酸化膜を用いた結果である同
図(a)に比べてgmの劣化は小さくなり、長期信頼度
が向上した。After removing the etchant with pure water, it was immediately placed in a diffusion furnace and subjected to thermal nitriding.Thermal nitriding was carried out for 10 minutes at a temperature of 950°C and the inflow gas was NH3:3Q/win.
A 0 nm silicon oxynitride film was formed to serve as a gate insulating film. After that, a poly-Si gate 4 is formed, and source and drain diffusion layers 5 are formed by ion implantation to form a MOS.
Created a transistor. Furthermore, by forming interlayer insulating films 6, 8 and Afi wiring 7.9, an MO5 type semiconductor device having the structure shown in FIG. 3 was manufactured. All lithography techniques used in manufacturing were electron beam direct lithography. The accelerating voltage of the electron beam was 30 kV. The time change of gm due to DC stress of the MOS transistor formed with this pile is shown in FIG. 2 (b) above. The MOS transistor has a channel length of 2 μm and a channel width of 15 μm. Compared to the result of using a thermal oxide film as the gate insulating film, as shown in FIG. 2(a), the deterioration of gm is smaller and the long-term reliability is improved.
次に、第2の実施例を説明する。本実施例においては、
リソグラフィー技術として全てX線露光法を用いた以外
は、第1の実施例と全く同様の製造法により、第3図に
示す構造のMO8O8型半体導体装置造した。X線露光
法に当っては、x、iamとして電子ビーム励起X線源
を用い1Moターゲットに20kVの電子線を照射し1
発生した特性X線を用いて露光した。本法で形成したM
OSトランジスタのDCストレスによるgm劣化の時間
変化を第4図直線(b)に示す、同図直線(a)は従来
のゲート絶縁膜として熱酸化膜を用いているMoSトラ
ンジスタのgm劣化を示している。Next, a second example will be described. In this example,
A MO8O8 type semiconductor device having the structure shown in FIG. 3 was manufactured by the same manufacturing method as in the first example except that the X-ray exposure method was used as the lithography technique. In the X-ray exposure method, an electron beam excitation X-ray source is used as x and iam, and a 1Mo target is irradiated with a 20 kV electron beam.
Exposure was performed using the generated characteristic X-rays. M formed by this method
Line (b) in Figure 4 shows the time change in gm deterioration due to DC stress in an OS transistor. Line (a) in the same figure shows gm deterioration in a MoS transistor that uses a conventional thermal oxide film as the gate insulating film. There is.
本法を用いることによりgmの劣化は小さくなっており
、長期信頼度が向上した。By using this method, the deterioration of GM was reduced and long-term reliability was improved.
なお、実施例においては、チャネル長2μm。In addition, in the example, the channel length is 2 μm.
チャネル幅15μmのNMOS トランジスタを用いて
説明したが1本発明が素子のサイズや基板・配線等の材
料に限定されないのは言うまでもない。Although the description has been made using an NMOS transistor with a channel width of 15 μm, it goes without saying that the present invention is not limited to the size of the element or the materials of the substrate, wiring, etc.
上記のように本発明によれば、電子線直接描画法もしく
はX線露光法を用いて製造されるMO8型半導体装置の
高信頼化を図ることができる。As described above, according to the present invention, it is possible to improve the reliability of an MO8 type semiconductor device manufactured using an electron beam direct writing method or an X-ray exposure method.
第1図は本発明の効果の一例を示す図、第2図は従来の
特性の一例を示す図、第3図および第4図は本発明の一
実施例を示す断面図、および特性図である。
1・・・P型Si基板、3・・・ゲート絶縁膜、4・・
・ポリSiゲート、5・・・拡散層、6,8・・・層間
絶縁膜。
石 1 図
冨2図
スLLスJpla科間(set)
冨3 囲
て4 図FIG. 1 is a diagram showing an example of the effect of the present invention, FIG. 2 is a diagram showing an example of conventional characteristics, and FIGS. 3 and 4 are a cross-sectional view and characteristic diagram showing an example of the present invention. be. 1...P-type Si substrate, 3...gate insulating film, 4...
- Poly-Si gate, 5...diffusion layer, 6, 8... interlayer insulating film. Stone 1 Figure 2 Figures LL Su Jpla Category (set) 3 Enclosed 4 Figures
Claims (1)
程と、電子線描画法もしくはX線露光法を用いてパタン
加工を行う工程とを含むことを特徴とする半導体装置の
製造方法。1. A method for manufacturing a semiconductor device, comprising a step of forming a silicon oxynitride film in contact with a semiconductor substrate, and a step of patterning using an electron beam lithography method or an X-ray exposure method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60144743A JPS627166A (en) | 1985-07-03 | 1985-07-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60144743A JPS627166A (en) | 1985-07-03 | 1985-07-03 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS627166A true JPS627166A (en) | 1987-01-14 |
Family
ID=15369325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60144743A Pending JPS627166A (en) | 1985-07-03 | 1985-07-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS627166A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7468304B2 (en) | 2005-09-06 | 2008-12-23 | Canon Kabushiki Kaisha | Method of fabricating oxide semiconductor device |
-
1985
- 1985-07-03 JP JP60144743A patent/JPS627166A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7468304B2 (en) | 2005-09-06 | 2008-12-23 | Canon Kabushiki Kaisha | Method of fabricating oxide semiconductor device |
| US7691715B2 (en) | 2005-09-06 | 2010-04-06 | Canon Kabushiki Kaisha | Method of fabricating oxide semiconductor device |
| US7883934B2 (en) | 2005-09-06 | 2011-02-08 | Canon Kabushiki Kaisha | Method of fabricating oxide semiconductor device |
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