JPS6274127A - 同期化装置 - Google Patents

同期化装置

Info

Publication number
JPS6274127A
JPS6274127A JP61229490A JP22949086A JPS6274127A JP S6274127 A JPS6274127 A JP S6274127A JP 61229490 A JP61229490 A JP 61229490A JP 22949086 A JP22949086 A JP 22949086A JP S6274127 A JPS6274127 A JP S6274127A
Authority
JP
Japan
Prior art keywords
data
clock
synchronizer
address
port memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61229490A
Other languages
English (en)
Japanese (ja)
Inventor
Norudobii Rasumusu
ラスムス・ノルドビイ
Kurandoru Dagurasu
ダグラス・クランドル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Japan Inc
Original Assignee
Yokogawa Hewlett Packard Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hewlett Packard Ltd filed Critical Yokogawa Hewlett Packard Ltd
Publication of JPS6274127A publication Critical patent/JPS6274127A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
    • G06F2205/102—Avoiding metastability, i.e. preventing hazards, e.g. by using Gray code counters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
JP61229490A 1985-09-27 1986-09-26 同期化装置 Pending JPS6274127A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US78186885A 1985-09-27 1985-09-27
US781868 1985-09-27

Publications (1)

Publication Number Publication Date
JPS6274127A true JPS6274127A (ja) 1987-04-04

Family

ID=25124214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61229490A Pending JPS6274127A (ja) 1985-09-27 1986-09-26 同期化装置

Country Status (4)

Country Link
EP (1) EP0217486B1 (de)
JP (1) JPS6274127A (de)
CA (1) CA1266720A (de)
DE (1) DE3674700D1 (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01291321A (ja) * 1988-05-18 1989-11-22 Mitsubishi Electric Corp 論理回路
JPH04220753A (ja) * 1990-12-20 1992-08-11 Fujitsu Ltd 共用メモリシステム
JP2008217450A (ja) * 2007-03-05 2008-09-18 Nec Access Technica Ltd デュアルポートメモリを用いた同期化回路

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146564A (en) * 1989-02-03 1992-09-08 Digital Equipment Corporation Interface between a system control unit and a service processing unit of a digital computer
US5274647A (en) * 1989-02-13 1993-12-28 Kabushiki Kaisha Toshiba Elastic buffer with error detection using a hamming distance circuit
JPH0630053B2 (ja) * 1989-02-13 1994-04-20 株式会社東芝 遅延バッファ回路
US5267191A (en) * 1989-04-03 1993-11-30 Ncr Corporation FIFO memory system
US5008904A (en) * 1989-07-24 1991-04-16 Hewlett-Packard Co. Synchronizer using clock phase extrapolation
DE3941880C2 (de) * 1989-12-19 1997-05-07 Vdo Schindling Verfahren und Schaltungsanordnung zur Datenübertragung, insbesondere in der Kraftfahrzeugelektronik
US5088061A (en) * 1990-07-24 1992-02-11 Vlsi Technology, Inc. Routing independent circuit components
US5867695A (en) * 1992-10-16 1999-02-02 International Business Machines Corp. Method and system for reduced metastability between devices which communicate and operate at different clock frequencies
GB2289146B (en) * 1994-04-12 1998-09-09 Nokia Mobile Phones Ltd Buffering data
DE4417286A1 (de) * 1994-05-13 1995-11-23 Deutsche Bundespost Telekom Verfahren und Schaltungsanordnung zum Auslesen von Daten aus Pufferspeichern in ATM-Einrichtungen
FR2725825B1 (fr) * 1994-10-12 1997-01-10 Majos Jacques Dispositif de memoire asynchrone a acces sequentiel et procede de stockage et de lecture correspondant
DE10127424B4 (de) * 2001-06-06 2004-09-02 Infineon Technologies Ag Elektronische Schaltung mit asynchroner Taktung von Peripherieeinheiten
EP1396786A1 (de) * 2002-09-03 2004-03-10 STMicroelectronics Limited Brückenschaltung zur Neutaktung in einer integrierten Halbleiterschaltung

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6054042A (ja) * 1983-09-02 1985-03-28 Sony Tektronix Corp デ−タ転送方法及び装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4424543A (en) * 1981-11-16 1984-01-03 Dma Systems Corporation Method and apparatus for recording transducer positioning information

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6054042A (ja) * 1983-09-02 1985-03-28 Sony Tektronix Corp デ−タ転送方法及び装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01291321A (ja) * 1988-05-18 1989-11-22 Mitsubishi Electric Corp 論理回路
JPH04220753A (ja) * 1990-12-20 1992-08-11 Fujitsu Ltd 共用メモリシステム
JP2008217450A (ja) * 2007-03-05 2008-09-18 Nec Access Technica Ltd デュアルポートメモリを用いた同期化回路

Also Published As

Publication number Publication date
EP0217486A3 (en) 1989-03-15
DE3674700D1 (de) 1990-11-08
EP0217486A2 (de) 1987-04-08
CA1266720A (en) 1990-03-13
EP0217486B1 (de) 1990-10-03

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