JPS6275741A - Parity check circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an improved parity check circuit.

(Prior Art) In recent years, various parity generation circuits and check circuits have been proposed in advanced technology. The circuit configuration of a conventional parity check circuit will be described with reference to a circuit diagram of a conventional parity check circuit shown in FIG.

Although FIG. 3 shows an example of a circuit using EX-NOH, [EX-OR can also be used depending on the circuit selection.

In FIG. 3, bit A1 of nine operand bits (hereinafter abbreviated as bit input) A-A
and A2 are connected to the first exclusive OR circuit (hereinafter abbreviated as EX-NOR) 1, and bits A3 and A4 are connected to the second EX-NOR circuit.
NOR2, bit input A, and A6 are the third
OR3, focus input A7 and A, l is the 4th EX-NO
It is input to R4. Bits A1 and A2 are both logical values'
°1" or logical value "°O", the first EX-N
The output of OR1 becomes the logical value '1°'. Bit input A
,,A4 and second EX-NOR2 output, bit human power A
5. A6 and the output of the third EX-NOR3, bit human power A
,, The relationship between A8 and the output of the fourth EX-NOR4 is also similar.

Next, 1st NO EX-NOR1 2nd (7) EX-N
OR2 output to 5th EX-NOR5, 3rd (7)
The output of EX-NOR3 and the fourth EX-NOR4 is
input to εX-NOR6. If the number of bit inputs with logical value “1'' among bit inputs 0 to A4 is an even number, the output of the fifth EX-NOR5 becomes logical value “1”.Bit inputs A, ~A, The relationship between the output of the sixth IEX-NOR6 and the output of the sixth IEX-NOR6 is also similar.
R5 and the 6th (7) EX-NOR6 output to the 7th EX
-Input to NOR7. Out of 〇～A to bit input.

If the number of bit inputs with logical value '°1' is even, the seventh
The output of EX-NOR7 becomes the logical value '1'.

Finally, the output of the 7th EX-NOR7 and the bit human power AS
is input to the eighth EX-NOR8, bit input A
If the number of bit inputs of the logical value "°1°" among the bits input from process to A is an even number, the output Y of the eighth EX-NOR 8 becomes the logical value "1".

(Problems to be Solved by the Invention) According to the circuit configuration of the conventional parity check circuit, 9 bit inputs pass through 4 stages of EX-NOR and output a check result. There is a problem in that the chip area becomes large because it requires two N-channel transistors and two P-channel transistors.

(Means for Solving the Problems) The present invention provides the following methods for determining whether the total number of logical values "1" of the minimum unit of three bits is an even number or an odd number.
The true value or complement value of the first bit input is input to the first or second transfer gate, and the exclusive OR output of the second and third bit inputs is used as a positive phase signal or a negative phase signal. , the logical value of the bit input ゛°
The present invention provides a parity check circuit configured to determine whether the total number of 1'' is an even number or an odd number.

Also, by connecting four of the minimum unit circuits,
2-stage EX-NO consisting of 72 transistors
By simply passing through R and a two-stage transfer gate, 8
Total of bit operand input and parity bit input: 9
The object of the present invention is to provide a parity check circuit that can determine whether the total number of input logical values of bits is an even number or an odd number.

(Function) According to the present invention, for every 3 bits, the logical value of the bit
By using a configuration that determines whether the total number of '1's is an even number or an odd number, the number of 1-transistors constituting the parity check circuit can be reduced to reduce the chip area, and the gate stage through which the output signal passes can be reduced. By having at least two stages, the operation time can be shortened.

(Embodiment) A parity check circuit of the present invention will be explained with reference to FIGS. 1 and 2.

FIG. 1 shows a circuit diagram of a 3-bit parity check circuit according to the first embodiment of the present invention. Among the bit inputs A1 to A, the bit input A is connected to the first transfer gate through an inverter 9. 1o and directly to the transfer gate 11 of the tube 2. Also, bit human power A2 and A are.

The positive phase signal is input to the EX-NOR 12, and the exclusive OR output is applied to the gate of the N channel transistor of the first transfer gate 1o and the gate of the N channel transistor of the second transfer gate 1o.
The reverse phase signal is input to the gate of the P channel transistor of the first transfer gate 10 and the gate of the N channel transistor of the second transfer gate 11. Second transfer gate 10.11
is under control.

In other words, the logical value of one of bits A2 and A3 is "
1 ” If the other logical value is °' o ” , E
The exclusive OR by the X-NOR 12 is output as a logical value of "°1".

Since the first transfer gate 10 is controlled to be in the "O'N" state and the second transfer gate 11 is controlled to be in the "OFF" state, only the complementary value that has passed through the inverter 9 is input to the bit input. First transfer gate 1
If the pinto human power A is the logical value "l", the output Y will be the logical value "°0", and if the bit input A□ is the logical value "o", the human power Y will be output. becomes the logical value ゛°1°゛. On the contrary, the logical values of bits A7 and A3 are both °1゛ or "O".

In the case of , the exclusive OR by the EX-NOR 12 is output as the logical value "P", so the bit power A is outputted only as the true value that has passed through the second transfer gate 11 and sent to the bit input. If 〇 is a logical value °°1′″, output Y
is the logical value “1”, and bit human power A1 is the logical value “o”
”, the output Y becomes a logical value “o”. That is, if the total number of logical values □°1″ among the bit inputs A1 to A3 is an even number, the logical value of the output Y becomes “O”.

If the total number is odd, the logical value of the output Y will be '1°'.

FIG. 2 shows a circuit diagram of an 8-bit parity check circuit according to a second embodiment of the present invention, which is constructed by connecting four 3-bit parity check circuits shown in FIG. Second
In the figure, pin 1 to inputs A1 to A 15 to perform a first parity check, and outputs Y□ to Y3 as a result of the first parity check are input to a fourth parity check circuit 16, and outputs Y4. A second parity check is performed by. If the number of logical values "1" of the bit inputs of all or one of the first to third parity check circuits 13 to 15 is an even number, the output Y of the first parity check, ~Y1
The logic values are all °°O" or only one is 0 and the other two are 1, and the output of the second parity check is Y
The logic value of 4 is °°0゛', and the number of logic values □'1'' of the bit inputs of all or one parity check circuit among the first to third parity check circuits 13 to I5 is an odd number. If so, the outputs Y, ~Y1 of the first parity check will have all logic values "1", or only one logic value "1" and the other two
Then, the logical value of the output Y4 of the second parity check becomes "'1°".

That is, if the total number of logical values °''1'' among the nine bits A1 to A is an even number, the logical value of the output Y4 of the second parity check is °°0'', the logical value ' If the total number of degrees 1'' is an odd number, the logic (direct) of the output Y4 of the second parity check becomes 1 par.

(Effects of the Invention) According to the present invention, the parity check circuit in units of 3 bits can be
By using 8 bits, it is possible to configure a standard 8-bit parity check circuit, reduce the number of gate elements in the circuit configuration, reduce the number of gate stages through which the input signal passes to a minimum of 2, and speed up the operation time. There is a remarkable effect that an excellent parity check circuit can be realized.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a 3-bit parity check circuit which is a first embodiment of the present invention, and FIG. 2 is a circuit diagram of an 8-bit parity check circuit which is a second embodiment of the present invention. FIG. 3 shows a circuit diagram of a conventional parity check circuit. 1~8.12-...Exclusive OR circuit (EX-NOR)
, 9 ・Inverter, IO, II... Transfer game h, 13~1G... 1st. second, third, and fourth parity check circuits; Patent applicant Matsushita Electric Industrial Co., Ltd. Figure 1 Figure 2 Figure 3 Figures 1-8゛・EX-NOR

Claims (1)

[Claims] Among multiple binary operand bit inputs, the logical value “
In a parity check circuit that determines whether the total number of 1'' inputs is even or odd, the true value of the first operand bit input among the minimum unit of three operand bit inputs is sent to the first transfer gate, The first operand
The complementary values of the bit inputs are respectively connected to the second transfer gate, and the positive phase signal of the exclusive OR of the second and third operand bit inputs is connected to the gate of the N-channel transistor of the first transfer gate and are connected to the gates of the P-channel transistors of the second transfer gate, respectively, and the opposite-phase signals of the exclusive OR of the second and third operand bit inputs are connected to the gates of the P-channel transistors of the second transfer gate.
The transistor is connected to the gate of the P-channel transistor of the transistor transfer gate and the gate of the N-channel transistor of the second transfer gate, and further, the outputs of the first and second transfer gates are connected in parallel. parity check circuit.