JPS6276665A - Complementary semiconductor device - Google Patents

Abstract

PURPOSE:To improve transistor driving power, to achieve a high speed and to obtain high reliability, by a constitution, wherein impurity distributions in transistor channel regions, which are formed in the first- and second- conductivity-type element regions on the surface of the first conductivity type semiconductor substrate, are made to be impurity distribution having junctions. CONSTITUTION:In a process, which is close to the initial period for obtaining a CMOS, a polycrystalline silicon film 29 is deposited on the entire surface. After a resist is formed on a well region 22, e.g., phosphorus ions are implanted in the polycrystalline silicon film 29 on a substrate 21 other than the well region 22. Thus, an N-type part is obtained and the resist is removed. After the resist is formed on the substrate 21 other than the well region 22, e.g., boron ions are implanted in the polycrystalline film 29 on the well region 22. A P-type part is obtained and the resist is removed. At a process close to the end, tungsten films 37 are selectively grown on the polycrystalline silicon forming gate electrodes 31 and the like. The gate electrode 31 including the N-type impurities and the gate electrode 31 including the P-type impurities are connected through the tungsten films 37.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a complementary semiconductor device, and more particularly to a high-speed and highly reliable complementary semiconductor device with an improved impurity profile in a channel region.

[Technical background of the invention]

A conventional method for manufacturing a CMO8 semiconductor device will be described with reference to FIGS. 3(a) to 3(C).

First, a P-type well region 2 is selectively formed in a part of the surface of an N-type silicon substrate 1. Next, Well Territory IIi! A field inversion prevention layer 3.4 is formed in a predetermined region of the substrate 1 and well region 2 other than 2, respectively.

Subsequently, a field oxide film 5 is formed by selective oxidation, and then a gate oxide film 6 is formed. Next, MOS
The substrate 1 other than the well region 2 is used to adjust the threshold voltage (V th ) of the transistor, improve the punch-through breakdown voltage, etc.
After a resist (not shown) is formed thereon, a channel ion implantation layer 7 is formed by, for example, boron ion implantation, and the resist is removed. Similarly, after forming a resist (not shown) on the well region 2 in order to adjust the threshold voltage (Vth) and improve the punch-through breakdown voltage, channel ion implantation 117- is formed by ion-implanting boron and phosphorus, for example. Then, the resist is removed. (Illustrated in FIG. 3(a)). Next, after depositing a polycrystalline silicon film over the entire surface, for example, phosphorus is diffused to lower the resistance. Next, pattern the polycrystalline silicon film to create gate 1! Form ff18. Subsequently, a resist (not shown) is formed on the substrate 1 other than the well region 2, and then, for example, arsenic is ion-implanted to form N" type source and drain regions 9 and 10, and the resist is removed.

Subsequently, after forming a resist (not shown) on the well region 2, a P+
Type source and drain regions 11 and 12 are formed, and the resist is removed (as shown in FIG. 3B). Next, after depositing an interlayer insulating film 13 on the entire surface, a portion thereof is selectively etched to form a contact hole. Subsequently, after vapor-depositing A.degree. C. over the entire surface, patterning is performed to form the wiring 14, thereby manufacturing 0MO8 (as shown in FIG. 4(C)).

In the conventional 0MO8 described above, the gate electrodes of both the P-channel MOS transistor (hereinafter referred to as PMO8) and the N-channel MOS transistor (hereinafter referred to as NMO8) are doped with the same impurity (usually an N-type impurity as described above). ) is made of polycrystalline silicon. On the other hand, the impurity distribution in the channel region is determined by taking into account the work function difference between the gate electrode and the channel region, and when the gate electrode contains N-type impurities, the impurity distribution as shown in FIGS. 4(a) and (b) distribution is adopted. In other words, the impurity distribution in the channel region is a buried channel type with a junction as shown in Figure 4(a) in PMO8, and a surface channel type without a junction in NMO8 as shown in Figure 4(b). . In this way, when both the gate electrodes of PMO3 and NMO8 contain the same impurity, the impurity distribution in the channel region of either PMO8 or NMO8 is of the surface channel type.

Furthermore, recently, it has been considered to use polycrystalline silicon containing P-type impurities as the gate electrode of PMO3, and using polycrystalline silicon containing N-type impurities as the gate electrode of NMO8. In this case, the impurity distribution in the channel region of both PMO8 and NMO8 becomes a surface channel type.

[Problems with background technology]

Incidentally, in recent years, the speed of semiconductor integrated circuits has been increasing, and the most effective way to increase the speed is to improve the driving power of transistors. However, when the impurity distribution in the channel region is a surface channel type, carriers are easily scattered at the substrate-gate oxide film interface, resulting in lower carrier mobility than when the impurity distribution is a buried channel type. , resulting in a decrease in transistor driving power. In addition, with the miniaturization of devices, deterioration of reliability due to hot carriers becomes a problem, but in the case of surface channel type, the current path is close to the gate oxide film, and hot carrier injection efficiency into the gate oxide film is high. Therefore, it becomes difficult to ensure reliability.

(Objective of the Invention) The present invention has been made in consideration of the above circumstances, and aims to provide a complementary semiconductor device that improves transistor driving power, achieves high speed, and has high reliability. be.

[Summary of the invention]

In the complementary semiconductor device of the present invention, the impurity distribution in the channel region of the transistor formed in the first and second conductivity type element regions on the surface of the first conductivity type semiconductor substrate forms an impurity distribution having a junction. This is a characteristic feature.

In this way, when the impurity distribution in the channel region is a buried channel type having a junction, the gate electrode material is selected in consideration of the work function difference with the channel region. For example, the first
The first gate electrode is formed on the element region of the conductivity type.
The conductivity type impurity can be formed by using polycrystalline silicon containing the second conductivity type impurity as the gate electrode formed on the second conductivity type element region, or by using a single metal plate or a single metal layer having an appropriate work function. Metal silicide is commonly used for all gate electrodes.

According to such a complementary semiconductor device, N M O3,
Since the impurity distribution in the channel region of both PMO8 is of a buried channel type, the transistor driving force can be improved to achieve high speed, and it is possible to prevent a decrease in reliability due to hot carriers.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIGS. 1(a) to ((Ill)) and FIG. 2.

FIGS. 1(a) to 1(g) are cross-sectional views showing the manufacturing process of giving 1 0MO8 according to the present invention. First, a P-type well region 22 is selectively formed in a part of the surface of an N-type silicon substrate 2). Next, field inversion prevention layers 23 and 24 are formed on the substrate 2) other than the well region 22 and on predetermined f[ of the well region 22, respectively. Subsequently, after forming a field oxide film 25 by selective oxidation method, a gate oxide film 26 is formed.
form. Next, after forming a resist on the well region 22, ions of, for example, phosphorus are implanted to improve the bunch-through breakdown voltage, and further, ions of, for example, boron are implanted to adjust the threshold voltage (V th). A channel ion implantation layer 27 is formed in the element region of the substrate 2) other than 1a22, and the resist is removed. Subsequently, after forming a resist on the substrate 2) other than the well region 22, ions of boron, for example, are implanted to improve the bunch-through breakdown voltage, and further, ions of arsenic, for example, are implanted to adjust the threshold voltage (V th). A channel ion implantation layer 28 is formed in the element region of the well region [22] by implantation, and the resist is removed (as shown in FIG. 1(a)).

Next, a polycrystalline silicon film 29 is deposited over the entire surface. Subsequently, after forming a resist on the well region 22, the polycrystalline silicon film 29 on the substrate 2) other than the well region 22 is made into an N type by ion-implanting, for example, phosphorus, and the resist is removed. Subsequently, after forming a resist on the substrate 2) other than the well region 22, the two polycrystalline silicon films on the well region 22 are made into P-type by ion-implanting boron, for example, and the resist is removed (see FIG. (b) As shown). Next, a silicon nitride film 30 is deposited on the entire surface of the two polycrystalline silicon films (as shown in FIG. 3C).

Next, the silicon nitride film 30 and the polycrystalline silicon film 29 are sequentially patterned using a resist (not shown) as a mask to form a gate electrode 31 and a silicon nitride film pattern 30'' on the gate electrode 31, and the resist is removed (
Figure 1) (Illustrated). Next, after a resist is formed on the well region 22, P+ type source and drain regions 32 and 33 are formed by, for example, boron ion implantation, and the resist 1 is removed. Subsequently, after forming a resist on the substrate 2) other than the well region 22, for example, arsenic is ion-implanted to form the N+ type source and drain regions 34.
．． 35 is formed and the resist is removed. Subsequently, thermal oxidation is performed to grow thermal oxidation 136 on the side walls of the gate electrode 31 (as shown in FIG. 3(e)).

Next, after removing the silicon nitride film pattern 30-, tungsten 11137 is selectively grown on the polycrystalline silicon constituting the gate electrode 31 and the like. As a result, the gate electrode 31 containing an N-type impurity and the gate electrode 31 containing a P-type impurity are connected by the tungsten film 37 (as shown in FIG. 3(f)). Next, an interlayer insulating film 38 is applied to the entire surface.
After depositing a contact hole, a part of it is selectively etched to form a contact hole. Next, after depositing 82 on the entire surface, patterning is performed to form wiring 39, and 0MO8
(Illustrated in the same figure (Q)).

In the CMOS shown in Figure 1 (CJ), N-type polycrystalline silicon is used as the gate electrode of PMO3, P-type subcrystalline silicon is used as the gate electrode of NMOS, and
As shown in Figures (a) and (b), the impurity distribution in the channel region is of a buried channel type with a junction. Therefore, in both PMO8 and NMO8, scattering at the substrate-gate oxide film interface is suppressed, transistor driving power is significantly improved, and high-speed CMO8 integrated circuits can be achieved. In addition, since the impurity distribution in the channel region of both PMO8 and NMO8 is a buried channel type, the current path moves away from the gate oxide film, and the injection efficiency of hot carriers into the gate oxide film decreases.
Reliability can be significantly improved.

In the above example, channel ion implantation to control the threshold voltage (V th ) and improve punch-through breakdown voltage was performed twice each for PMO3 and NMO8, but once for the substrate and well. It goes without saying that if the settings do not require ion implantation for improving the bunch-through breakdown voltage, only ion implantation for threshold voltage control may be sufficient.

In the above embodiments, N-type polycrystalline silicon was used for PMO3 and P-type subcrystalline silicon was used for N1vl○S as gate electrode materials in order to enable a buried channel type impurity distribution. If a buried channel type impurity distribution is possible by selecting a material with an appropriate work function for the gate electrode,
Single metal or metal silicide as PMO8, NMO
It may be used as a gate electrode material common to 8.

Furthermore, in the above embodiment, selective deposition of tungsten was used to connect the P-type child crystalline silicon and the N-type polycrystalline silicon that constitute the gate electrode. In this case, polycrystalline silicon containing different impurities can be well connected by low-temperature heat treatment, so that mutual diffusion of impurities can be avoided. Note that if interdiffusion of impurities due to high-temperature heat treatment is not a problem, a metal with a high melting point or metal silicide may be used instead of tungsten.

Furthermore, in the above embodiment, tungsten was deposited only on the polycrystalline silicon constituting the gate electrode, but the invention is not limited to this, and tungsten, other high-melting point metals, or metal silicides may also be deposited on the source and drain regions. good.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a complementary semiconductor device that improves transistor driving power, achieves high speed, and has high reliability.

[Brief explanation of drawings]

FIGS. 1(a) to (q) are CMOs in embodiments of the present invention.
Figures 2(a) and (b) are characteristic diagrams showing the impurity distribution in the channel region of the same CMOS, and Figures 3(a) to (C) are the conventional 0 of
A cross-sectional view showing the manufacturing process for obtaining MO8, FIG.
) and (b) are characteristic diagrams showing the impurity distribution in the channel region of the same CMOS, respectively. 2)... N-type silicon substrate, 22... P-type layer, 23.24... Field inversion prevention layer, 25...
- Field oxide film, 26... Gate oxide film, 27.
28...Channel ion implantation layer, 29...Polycrystalline silicon film, 30...Silicon nitride film, 31...G]-Shin' branch, N:j-#/, 32.33...・P-type source, drain region, 34.35...N+ type source, drain region, 36...thermal oxide film, 37...tungsten model, 3
8... Interlayer insulating film, 39... Wiring. Applicant's agent Patent attorney Takehiko Suzue Φ ni=R2F+-1

Claims (3)

[Claims] (1) Element regions of first and second conductivity types formed on the surface of a semiconductor substrate of first conductivity type, and gate insulating films and gate electrodes formed on the element regions of first and second conductivity types, respectively. , second conductivity type source and drain regions formed on the surface of the first conductivity type device region on both sides of the gate electrode, and first conductivity type source and drain regions formed on the second conductivity type device region surface on both sides of the gate electrode. A complementary semiconductor device having source and drain regions of conductivity type, characterized in that impurity distributions in channel regions of transistors formed in element regions of first and second conductivity types form an impurity distribution having a junction. Complementary semiconductor device. (2) The gate electrode formed on the element region of the first conductivity type contains impurities of the first conductivity type, and the gate electrode formed on the element region of the second conductivity type contains impurities of the second conductivity type. A complementary semiconductor device according to claim 1, characterized in that it is made of polycrystalline silicon. (3) Complementary item according to claim 2, characterized in that the gate electrode containing impurities of the first conductivity type and the gate electrode containing impurities of the second conductivity type are connected by a high melting point metal or metal silicide. type semiconductor device.