JPS627736B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse counting device that counts pulses input within a certain period of time and always maintains the minimum value of the counted value.

Techniques for digitally measuring quantities to be measured are progressing, and along with this, there is a demand for something that can always hold the minimum value among the counted values at regular intervals.

The object of the invention is to provide a pulse counting device that digitally always maintains a minimum value.

An embodiment of the present invention will be described below with reference to the drawings. Input terminal 1 is a terminal into which pulses are input, and the input pulses are distinguished from noise in input circuit 2, waveform-shaped, amplified, and then passed through first pulse input gate circuit 3 and second pulse input gate circuit 4 to the second pulse input gate circuit 4. 1
It is counted by a counter 5 and a second counter 6. 1st
An RS flip-flop is used as an example of the gate control circuit 7 and the second gate control circuit 8, and the first pulse input gate circuit 3, by the input of the gate open signal, until the input of the next gate close signal.
The second pulse input gate circuit 4 is opened. The main control circuit 9 controls the first gate control circuit 7 and the second gate control circuit 8, and also resets the first counter 5 and the second counter 6 directly and the first counter selection gate circuit 10 or the second counter selection gate. It is controlled via the circuit 11. . The comparator circuit 12 constantly compares the count values of the first counter 5 and the second counter 6, and continues to output a high-level signal P _c1 while the count value of the second counter 6 is smaller than the count value of the first counter 5. While the count value of the second counter 6 exceeds the count value of the first counter 5, the high level signal P _c2 continues to be output. The first delay circuit 13 and the second delay circuit 14 convert the counter reset signal _P4 that has passed through the first counter selection gate circuit 11 and the second counter selection gate 12 into a gate open signal by slightly delaying it. 15, 16, 17, 18 are or gate, 19
2 is a reference time signal generation circuit, and 20 is an external reset input terminal.

External reset signal _P0 is external reset input terminal 2
0 to the main control circuit 9, the main control circuit 9
outputs a gate closing signal _P1 at regular intervals. The first gate control circuit 7 and the second gate control circuit 8 are reset by the first gate closing signal _P1 ,
Therefore, the output from the output terminal Q becomes a low level, and the first pulse input gate circuit 3 and the second pulse input gate circuit 4 are closed. Following the first gate closing signal _P1 , the main control circuit 9 outputs a counter reset signal _P2 , and the OR gates 17,1
8 to the reset input terminals R of the first counter 5 and second counter 6 to reset them. Subsequently, the main control circuit 9 outputs the gate opening signal _P3.
is sent to the set input terminal S of the first gate control circuit 7 and the second gate control circuit 8 via the OR gates 15 and 16 to set these and open the first pulse input gate circuit 3 and the second pulse input gate circuit 4. let With this opening, the first counter 5 and the second counter 6 start counting pulses. After a certain period of time t has elapsed, the main control circuit 9 outputs the second gate closing signal _P1 , and the first gate control circuit 7
Then, the second gate control circuit 8 is reset, and the first pulse input gate circuit 3 and the second pulse input gate circuit 4 are closed. Following the second gate closing signal _P1 , the main control circuit 9 issues a counter reset signal.
_P4 is sent to the first counter selection gate circuit 10 and the second counter selection gate circuit 11. At this time, the first
Since the count values of the counter 5 and the second counter 6 are equal, the comparison circuit 12 outputs the high-level signal P _c2 to the second counter selection gate circuit 1.
1 has been opened. The first counter selection gate circuit 10 is closed because the signal P _c1 is not input thereto. Therefore, the counter reset signal _P4 is the second
It passes only through the counter selection gate circuit 11, passes through the OR gate 18, and resets the second counter 6. As a result, the count value of the first counter 5 remains as the minimum value. The counter reset signal _P4 passed through the second counter selection gate circuit 11 is transferred to the second delay circuit 1.
4 and becomes the gate opening signal _P5 ,
The signal is sent to the second gate control circuit 8, which is set and the second pulse input gate circuit 4 is opened. Therefore, during the second fixed time t, only the second counter 6 counts pulses. The second pulse input gate circuit 4 is closed by the third gate closing signal _P1 , and subsequently the counter reset signal _P4 is applied to the first pulse input gate circuit 4.
The signal is sent to the counter selection gate circuit 10 and the second counter selection gate circuit 11. When the count value of the second counter 6 is greater than or equal to the minimum value of the first counter 5, the comparator circuit 12 opens the second counter selection gate circuit 11 by the high level signal P _c2 , so the counter reset signal _P4 opens the second counter selection gate circuit 11. The second counter 6 is reset again, and only the second counter 6 counts pulses for the third fixed time t. Conversely,
When the count value of the second counter 6 is smaller than the minimum value of the first counter 5, the comparator circuit 12 opens the first counter selection gate circuit 10 with a high-level signal _Pc1 and resets the first counter 5. , the count value of the second counter 6 is left as the new minimum value.

Note that the timing of the signals P ₁ to _{P 4} output by the main control circuit 9 is measured by the reference time signal input from the reference time signal generation circuit 19. The comparison circuit 12 may output a pulse-like signal P _c1 or P _c2 in synchronization with the counter reset signal P ₄ .

In the present invention, one of the first counter and the second counter holds the minimum value, only the other counter counts input pulses, and compares the counted value with the minimum value, whichever is smaller. Since the value of is left as the minimum value, one of the counters can always hold the minimum value.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Figure 2 is the time chart. 1... Input terminal, 3... First pulse input gate circuit, 4... Second pulse input gate circuit, 5...
1st counter, 6...2nd counter, 7...1st counter
Gate control circuit, 8... Second gate control circuit, 9
...Main control circuit, 10...First counter selection gate circuit, 11...Second counter selection gate circuit,
12... Comparison circuit, 13... First delay circuit, 14
...Second delay circuit.

Claims (1)

[Claims] 1 The input terminal where the pulse is input and the first
The first opens and closes the input to the counter and the second counter.
a pulse input gate circuit, a second pulse input gate circuit, a first counter that counts pulses passing through the first pulse input gate circuit, and a second counter that counts pulses that pass through the second pulse input gate circuit;
A first gate control circuit that opens a first pulse input gate circuit when a gate open signal is input until the next gate close signal is input, and a second pulse input gate circuit that opens the first pulse input gate circuit until the next gate close signal is input when the gate open signal is input. A second gate control circuit opens the gate circuit, compares the count values of the first counter and the second counter, and opens the first counter selection gate circuit when the count value of the second counter is smaller than the count value of the first counter. a comparator circuit that opens the second counter selection gate circuit when the count value of the second counter exceeds the count value of the first counter; and a comparison circuit that opens the second counter selection gate circuit when the count value of the second counter exceeds the count value of the first counter; A gate close signal is sent to the second gate control circuit, and following the first gate close signal, a counter reset signal is sent to the first and second counters, and then a counter reset signal is sent to the first and second gate control circuits. Send a gate open signal to the control circuit,
A main control circuit that sends a counter reset signal to the first counter selection gate circuit and a second counter selection gate circuit every time a gate close signal is sent after the gate is issued, and a counter reset signal that is input from the main control circuit. A first counter selection gate circuit that sends a counter reset signal input from the main control circuit to the first counter and the first delay circuit when the circuit is opened, and a second counter selection gate circuit that sends the counter reset signal input from the main control circuit to the second counter and the second delay circuit when the circuit is opened. a counter selection gate circuit, a first delay circuit that delays a counter reset signal inputted from the first counter selection gate circuit, converts it into a gate open signal and sends it to the first gate control circuit, and a second counter selection gate circuit. A second delay circuit that delays an input counter reset signal to convert it into a gate open signal and sends it to a second gate control circuit.