JPS6278855A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a disconnection of the second layer wiring at the contact part by a method wherein an interlayer insulating film is provided in such a way that the upper surface of the contact part is exposed and the second layer wiring is formed on a flat surface which is formed at the upper surfaces of the contact part and the interlayer insulating film. CONSTITUTION:A resist 14 is left on the part, at which a contact part 151 is formed, and the metal film thickness of the part other than the contact part is decreased by etching using the resist 14 as a mask. A patterning of a metal film 13 for forming a first layer wiring is performed and a first layer wiring 15 in the prescribed pattern is formed. An interlayer insulating film 17 is deposited and a flattening is executed. By this flattening, the upper surface of the contact part 151 is brought into an exposed state. A metal film for forming a second layer wiring is formed by vapore deposition and the second layer wiring 18 is formed by performing a patterning. By this way, a disconnection of the wiring 18 at the contact part 151 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor device with a multilayer wiring structure, and more particularly relates to an improvement in the structure of a contact portion between a first layer wiring and a second layer wiring. It is something.

<Prior Art> Semiconductor devices are becoming increasingly integrated, and wiring technology is also shifting to multilayer wiring. Furthermore, wiring technology is becoming increasingly finer, and the dimensions of contact portions are becoming smaller year by year.

A conventional contact portion structure and its formation method are shown in FIG. In the figure, l is the semiconductor substrate, 2 is the 5i02 film, and 3 is the semiconductor substrate.
1 is a first layer wiring, 4 is an interlayer insulating film, 5 is a resist, 6 is a through hole, and 7 is a second layer wiring.

An interlayer insulating film 4 is formed on the first layer wiring 3, and a through hole 6 is formed in the contact portion by lithography technology (FIG. 2(a)). Thereafter, a metal film for forming a second layer wiring is formed by sputtering, vacuum evaporation, etc., and patterning is performed to form a second layer wiring 7 (FIG. 2(b)).

<Problems to be Solved by the Invention> However, in the above structure, as shown in FIG. (bad), and this caused the wire to break. The poor step coverage becomes greater as the through-hole size becomes smaller. In addition, in the conventional structure described above, the surface level difference after forming the second layer wiring is large, and when forming the third layer wiring on the second layer wiring, step coverage becomes more of a problem than when forming the second layer wiring. Become.

The present invention provides a contact portion structure that solves the above-mentioned problems in the conventional structure.

Means for Solving Problems〉 A first layer wiring is provided in which the film thickness of the contact portion is thicker than that of other wiring portions, and at least the top surface of the contact portion is exposed on the first layer wiring. An interlayer insulating film is formed. Then, the above contact ν is placed on the interlayer insulating film.
A second layer wiring is formed in contact with the upper surface of the portion.

<Example> Hereinafter, the present invention will be described in detail based on Examples.

FIG. 1 is a process sectional view showing a contact portion structure and a method for forming the same according to the present invention. In the figure, 11 is a semiconductor substrate, 12 is a 5i02 film, 13 is a metal film for forming first layer wiring, 14 is a resist, 15 is a first layer wiring, 16 is a resist, 17 is an interlayer insulating film, and 18 is a first layer wiring. It is a two-layer wiring.

First, a metal film 13 for forming the first layer wiring with a thickness of about 3 μm is formed by vapor deposition or the like, and a resist (4) is left in the area where the contact area is to be formed, and etching is performed using the resist as a mask to remove the area other than the contact area. The metal film thickness for S is reduced to about 1 μm (FIG. 1(a)).

Next, the metal film for forming the first layer wiring is patterned to form the first layer wiring 15 in a predetermined pattern (first layer wiring 15).
Figure (b)).

As is clear from the above description, in the first layer wiring 15, only the contact portion 151 has a thickness of approximately 3 μm, and the other wiring portion 152 has a thickness of approximately 1 μm.

Next, an interlayer insulating film 17 is deposited (FIG. 1(C)) and planarized (FIG. 1(d)).

Due to this planarization, the upper surface of the contact portion +51 is exposed.

Then, a metal film for forming a second layer wiring is formed by vapor deposition, and patterning is performed to form a second layer wiring 18. The second layer wiring 18 is in contact with the first layer wiring 15 at the upper surface of the contact portion (FIG. 1(e)).

When a third layer wiring is further provided on the second layer wiring, the shape of the second layer wiring may be the same as that of the first layer wiring.

In the conventional method, holes are made in the interlayer insulating film, as shown in FIG. 2(a). This shift in etching dimensions during drilling has been one of the factors limiting miniaturization of the hole tact portion.

The dimensions of the contact part in the above embodiment are shown in Figure 1(a).
Determined by resist patterning and etching shift. The larger the etching shift, the smaller the contact portion dimensions. By controlling the amount of this shift, it becomes possible to form finer contact portions than with conventional methods.

<Effects of the Invention> As described in detail above, according to the present invention, the film thickness of the contact portion of the first layer wiring is made thicker than that of other wiring portions, and at least the upper surface of the contact portion is exposed. Since the interlayer insulating film is provided as shown in FIG. It will be resolved. In addition, the surface level difference after forming the second layer wiring is smaller than before, so
Furthermore, the step coverage when forming the third layer wiring is improved, and the formation of the third layer wiring becomes easier.

[Brief explanation of drawings]

FIGS. 1(a) to 1(e) are process cross-sectional views showing a contact structure and a method of forming the same according to the present invention, and FIG. 2(a) is a cross-sectional view of the process. (b) is a process sectional view showing a conventional contact portion structure and its formation method. Explanation of symbols 11: semiconductor substrate, 12: 5i02 film, 13: first
Metal film for layer wiring formation, 14 resist, 15: first layer wiring, 16: resist, +7: N insulating film, 18: second layer wiring, 151: contact portion, 152: other wiring portions. Agent Patent attorney Aihiko Fukushi (and 2 others) (en No. 15iF (Q) (b) Tomi 2-rII

Claims (1)

[Claims] 1. In a semiconductor device having a multilayer wiring structure, a first layer wiring whose contact portion is thicker than other wiring portions, and at least the upper surface of the contact portion is exposed. A semiconductor device comprising: an interlayer insulating film; and a second layer wiring provided on the interlayer insulating film and in contact with the upper surface of the contact portion.