JPS6281246U - - Google Patents

Info

Publication number
JPS6281246U
JPS6281246U JP17143585U JP17143585U JPS6281246U JP S6281246 U JPS6281246 U JP S6281246U JP 17143585 U JP17143585 U JP 17143585U JP 17143585 U JP17143585 U JP 17143585U JP S6281246 U JPS6281246 U JP S6281246U
Authority
JP
Japan
Prior art keywords
program
transfer instruction
speed
rom
stores
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17143585U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17143585U priority Critical patent/JPS6281246U/ja
Publication of JPS6281246U publication Critical patent/JPS6281246U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路図、第2
図は同実施例のメモリマツプ例を示す模式図、第
3図は同実施例の動作例を示すフローチヤートで
ある。 1……CPU、2……ROM、3……RAM、
5……転送命令、6……プログラム、7……ジヤ
ンプ命令。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a schematic diagram showing an example of the memory map of the same embodiment, and FIG. 3 is a flowchart showing an example of the operation of the same embodiment. 1...CPU, 2...ROM, 3...RAM,
5...Transfer instruction, 6...Program, 7...Jump instruction.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] メモリに記憶されたプログラムに基づいてCP
Uを高速で動作させるプログラムの高速処理装置
において、前記プログラムとともに転送命令を記
憶するROMと、前記転送命令によつて指定され
るアドレスに配置されるRAMと、前記プログラ
ムを実行する前に前記転送命令に基づいて前記プ
ログラムを前記RAMに転送させ、この後前記R
AMに転送されたプログラムを処理するCPUと
を備えたことを特徴とするプログラムの高速処理
装置。
CP based on the program stored in memory
A high-speed processing device for a program that operates U at high speed includes a ROM that stores a transfer instruction together with the program, a RAM that is located at an address specified by the transfer instruction, and a ROM that stores a transfer instruction before executing the program. The program is transferred to the RAM based on the instruction, and then the R
A high-speed program processing device comprising: a CPU that processes a program transferred to an AM.
JP17143585U 1985-11-07 1985-11-07 Pending JPS6281246U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17143585U JPS6281246U (en) 1985-11-07 1985-11-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17143585U JPS6281246U (en) 1985-11-07 1985-11-07

Publications (1)

Publication Number Publication Date
JPS6281246U true JPS6281246U (en) 1987-05-23

Family

ID=31107058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17143585U Pending JPS6281246U (en) 1985-11-07 1985-11-07

Country Status (1)

Country Link
JP (1) JPS6281246U (en)

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