JPS6281923A - Overcurrent detector circuit - Google Patents

Overcurrent detector circuit

Info

Publication number
JPS6281923A
JPS6281923A JP60221420A JP22142085A JPS6281923A JP S6281923 A JPS6281923 A JP S6281923A JP 60221420 A JP60221420 A JP 60221420A JP 22142085 A JP22142085 A JP 22142085A JP S6281923 A JPS6281923 A JP S6281923A
Authority
JP
Japan
Prior art keywords
load
transistor
overcurrent
voltage
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60221420A
Other languages
Japanese (ja)
Inventor
圭 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP60221420A priority Critical patent/JPS6281923A/en
Publication of JPS6281923A publication Critical patent/JPS6281923A/en
Pending legal-status Critical Current

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  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (発明の分野) この発明は、1〜ランジスタで負荷を駆動する場合に好
適な過電流@λ[1回路に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to an overcurrent @λ[1 circuit suitable for driving a load with one to transistors.

(発明の概要) この発明では、負荷IWりJlt]トランジスタの主端
子間飽和電圧を基準電圧と比較J°ることにより、過電
流を検出覆るように構成し、出力の残電圧及び発熱量を
最小にする効果をもたらすものでおる。
(Summary of the Invention) In this invention, an overcurrent is detected and overridden by comparing the saturation voltage between the main terminals of the load IW and the transistor with a reference voltage, and the output residual voltage and heat generation amount are reduced. This will have the effect of minimizing

(従来技術とその問題点) 従来、トランジスタで負荷を駆動する場合において、負
荷の過電流を検出するには、第4図に示されるように、
負荷駆動用トランジスタコと直列に電流検出用抵抗2を
接続し、抵抗2の端子間電圧をコンパレータ3でレベル
弁別するのが通例である。
(Prior art and its problems) Conventionally, when driving a load with a transistor, in order to detect an overcurrent in the load, as shown in FIG.
It is customary to connect a current detection resistor 2 in series with the load driving transistor, and to discriminate the level of the voltage across the terminals of the resistor 2 using a comparator 3.

なお、4,5はそれぞれ制御回路と主回路とを絶縁分離
するだめのフォトカプラである。
Note that 4 and 5 are photocouplers for insulating and separating the control circuit and the main circuit, respectively.

しかしながら、このような過電流検出回路におっては、
電流検出用抵抗2による電圧降下が生じるため、出力側
から児た残電圧が高くなる他、抵抗2による発熱か大き
く、熱設計、実装設計上も制約を受Cプるなどの問題点
がおった。
However, in such an overcurrent detection circuit,
Since a voltage drop occurs due to the current detection resistor 2, the residual voltage from the output side becomes high, and the heat generated by the resistor 2 is large, resulting in many problems such as restrictions on thermal design and mounting design. Ta.

(発明の目的) この発明の目的は、出力側から児だ残電圧が低く、しか
も発熱も少ない過電流検知回路を提供することにおる。
(Objective of the Invention) An object of the invention is to provide an overcurrent detection circuit which has a low residual voltage from the output side and generates little heat.

(発明の構成とすJ果) この発明は上記の目的を達成するために、負荷駆動用ト
ランジスタの主端子間飽和電圧を基準電圧と比較するこ
とにより、過電流を検知することを特徴とする。
(Structures and Effects of the Invention) In order to achieve the above object, the present invention is characterized in that overcurrent is detected by comparing the saturation voltage between the main terminals of the load driving transistor with a reference voltage. .

このような構成によれば、飽和残電圧を高くすることが
なく、また発熱量も最小限に押えることができ、熱設計
、実装設計上の制約を軽減させることができる。
According to such a configuration, the saturation residual voltage does not become high, the amount of heat generated can be suppressed to a minimum, and restrictions on thermal design and packaging design can be reduced.

ざらに、トランジスタがオフの時、出力端の電圧を監視
することになるため、負荷の断線検出も可能となる。
Furthermore, since the voltage at the output terminal is monitored when the transistor is off, it is also possible to detect load disconnection.

(実施例の説明) 第1図は本発明に係わる過電流検出回路の一例を示す回
路図である。
(Description of Embodiments) FIG. 1 is a circuit diagram showing an example of an overcurrent detection circuit according to the present invention.

同図に示す如く、この回路では、負荷駆動用トランジス
タ1のエミッタ・コレクタ間(主端子間)電圧をコンパ
レータ6でレベル弁別することにより、負荷回路の過電
流を検出するようにしている。
As shown in the figure, in this circuit, an overcurrent in the load circuit is detected by level-discriminating the voltage between the emitter and collector (between the main terminals) of the load driving transistor 1 using a comparator 6.

なお、7.8はそれぞれ主回路と制御回路を絶縁分離す
るためのフォトカプラである。
Note that 7 and 8 are photocouplers for insulating and separating the main circuit and the control circuit, respectively.

次に、負荷のオンオフ動作は次のように行なわれる。出
力0N10FF信号が“ビ′であれば、フォトカプラ7
がオンし、負荷駆動トランジスタ1がオンする。他方、
出力ON/オフ信号が“ト1′′であれば、フォトカプ
ラ7がオフし、トランジスタ1がオフとなる。
Next, the load on/off operation is performed as follows. If the output 0N10FF signal is “BI”, photocoupler 7
is turned on, and load drive transistor 1 is turned on. On the other hand,
If the output ON/OFF signal is "T1", the photocoupler 7 is turned off and the transistor 1 is turned off.

次に過電流検出動作は次のように行なわれる。Next, the overcurrent detection operation is performed as follows.

トランジスタ1のコレクタに流れる電流ICと、コレク
タ・エミッタ間飽和電圧vcε(sat)との関係は、
第2図に示す如く、Icの増加に伴ってVcg(Sar
)の増加率が大きくなる特性をもっている。
The relationship between the current IC flowing through the collector of transistor 1 and the collector-emitter saturation voltage vcε(sat) is as follows:
As shown in Figure 2, as Ic increases, Vcg (Sar
) has the characteristic of increasing the rate of increase.

このV e r= (sat)をコンパレータ6によっ
て、予め設定された塁準電圧■refと比較すると、ト
ランジスタ1に過電流が流れたとき、コンパレータ6の
出力が“′ビとなり、検知信号が゛′ビ′となる。
When this V e r = (sat) is compared with the preset reference voltage ref by the comparator 6, when an overcurrent flows through the transistor 1, the output of the comparator 6 becomes "'", and the detection signal becomes " It becomes 'bi'.

次に、負荷の断線検出動作は次のように行なわれる。ト
ランジスタ]がオフのとき、負荷と負荷用電源が正常に
接続されていれば、トランジスタのコレクタには一定レ
ベル以上の電圧がかかっている。従って、コンパレータ
6の出力及び、検出信号はともに″じ′となる。もし、
負荷が断線したり負荷用電源が落ちた場合、トランジス
タ1のコレクタは無電圧となり、コンパレータ6が及び
′“H″、検出信号がともにH″となる。
Next, the load disconnection detection operation is performed as follows. When the transistor is off and the load and load power supply are connected properly, a voltage above a certain level is applied to the collector of the transistor. Therefore, the output of the comparator 6 and the detection signal are both "the same".If
When the load is disconnected or the load power supply is turned off, the collector of the transistor 1 becomes non-voltage, the comparator 6 becomes ``H'', and both detection signals become ``H''.

以上の動作により、第3図のフローチャートに示される
方法によって、過電流の検出と負荷の断線の検出を同時
に行なうことができる。
With the above-described operation, overcurrent detection and load disconnection detection can be performed simultaneously by the method shown in the flowchart of FIG.

なお、以上の実施例ではバイポーラトランジスタで説明
したが、パワーMOSトランジスタ等でも同様に説明で
きることは勿論である。
Note that although the above embodiments have been explained using bipolar transistors, it goes without saying that the same explanation can be made with power MOS transistors and the like.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係わる過電流検出回路の一例を示す回
路図、第2図はトランジスタのIC−VcE(sat)
特性曲線を示すグラフ、第3図は本発明装置の動作を説
明するフローチャート、第4図は従来例を示す回路図で
ある。 1・・・負荷駆動用トランジスタ 6・・・コンパレータ 1m
Fig. 1 is a circuit diagram showing an example of an overcurrent detection circuit according to the present invention, and Fig. 2 shows IC-VcE (sat) of a transistor.
FIG. 3 is a graph showing a characteristic curve, FIG. 3 is a flowchart explaining the operation of the device of the present invention, and FIG. 4 is a circuit diagram showing a conventional example. 1...Load driving transistor 6...Comparator 1m

Claims (1)

【特許請求の範囲】[Claims] (1)負荷駆動用トランジスタの主端子間飽和電圧を基
準電圧と比較することにより、過電流を検知することを
特徴とする過電流検知回路。
(1) An overcurrent detection circuit that detects overcurrent by comparing the saturation voltage between the main terminals of a load driving transistor with a reference voltage.
JP60221420A 1985-10-04 1985-10-04 Overcurrent detector circuit Pending JPS6281923A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60221420A JPS6281923A (en) 1985-10-04 1985-10-04 Overcurrent detector circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60221420A JPS6281923A (en) 1985-10-04 1985-10-04 Overcurrent detector circuit

Publications (1)

Publication Number Publication Date
JPS6281923A true JPS6281923A (en) 1987-04-15

Family

ID=16766458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60221420A Pending JPS6281923A (en) 1985-10-04 1985-10-04 Overcurrent detector circuit

Country Status (1)

Country Link
JP (1) JPS6281923A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007333666A (en) * 2006-06-19 2007-12-27 Tamagawa Seiki Co Ltd Disconnection detection method and apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007333666A (en) * 2006-06-19 2007-12-27 Tamagawa Seiki Co Ltd Disconnection detection method and apparatus

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