JPS6283672U - - Google Patents

Info

Publication number
JPS6283672U
JPS6283672U JP1985174067U JP17406785U JPS6283672U JP S6283672 U JPS6283672 U JP S6283672U JP 1985174067 U JP1985174067 U JP 1985174067U JP 17406785 U JP17406785 U JP 17406785U JP S6283672 U JPS6283672 U JP S6283672U
Authority
JP
Japan
Prior art keywords
card
semiconductor device
arrangement
cards
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985174067U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985174067U priority Critical patent/JPS6283672U/ja
Publication of JPS6283672U publication Critical patent/JPS6283672U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view

Landscapes

  • Credit Cards Or The Like (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図乃至第４図は、本考案を示すものであり
第１図は、ＩＣカード用半導体素子を埋設してな
るＩＣカードの概略平面図、第２図は回路基板の
概略平面図、第３図はパツドの配置を示すＩＣカ
ード用半導体素子の平面図、第４図は他の実施形
態を示すＩＣカード用半導体素子の平面図、第５
図乃至第７図は、従来例を示すものであり、第５
図はＩＣカード用半導体素子を埋設してなるＩＣ
カードの概略平面図、第６図は回路基板の概略平
面図、第７図はパツドの配置を示すＩＣカード用
半導体素子の平面図、第８図は本考案の更に他の
実施形態を示すＩＣカード用半導体素子の平面図
である。 １，２……ＩＣカード、１０……マイクロコン
ピユータ半導体素子、１１……データ記憶素子、
１２，２２……回路基板、１３……ピンコンタク
ト、２０……シングルチツプマイクロコンピユー
タ半導体素子。 1 to 4 show the present invention. FIG. 1 is a schematic plan view of an IC card in which a semiconductor element for an IC card is embedded, FIG. 2 is a schematic plan view of a circuit board, and FIG. 3 is a plan view of a semiconductor device for an IC card showing the arrangement of pads, FIG. 4 is a plan view of a semiconductor device for an IC card showing another embodiment, and FIG.
Figures 7 to 7 show conventional examples.
The figure shows an IC with embedded semiconductor elements for IC cards.
6 is a schematic plan view of the circuit board, FIG. 7 is a plan view of a semiconductor element for an IC card showing the arrangement of pads, and FIG. 8 is an IC card showing still another embodiment of the present invention. FIG. 2 is a plan view of a semiconductor element for a card. 1, 2...IC card, 10...microcomputer semiconductor element, 11...data storage element,
12, 22...Circuit board, 13...Pin contact, 20...Single chip microcomputer semiconductor element.

Claims (1)

【実用新案登録請求の範囲】 (1) データ記憶素子として、データの消去及び
再書込みが可能なＥＰＲＯＭ又はＥＥＰＲＯＭを
内蔵するシングルチツプマイクロコンピユータ半
導体素子で特にＩＣカードに適した所謂矩形状の
ＩＣカード用半導体素子において、ＩＣカードの
外表面に露出したピンコンタクトと接続される前
記ＩＣカード用半導体素子のパツドが、該ＩＣカ
ード用半導体素子の天と地の両辺縁部又は左と右
の両辺縁部に、前記ピンコンタクトの配列に適合
した形で優先的に配置されていることを特徴とす
るＩＣカード用半導体素子。 (2) 前記ピンコンタクトの配列がＩＣカードの
ＩＳＯ規格に適合していることを特徴とする実用
新案登録請求の範囲第１項記載のＩＣカード用半
導体素子。[Claims for Utility Model Registration] (1) A so-called rectangular IC card, which is a single-chip microcomputer semiconductor device that has a built-in EPROM or EEPROM that can erase and rewrite data as a data storage element, and is particularly suitable for IC cards. In the semiconductor device for IC card, the pad of the semiconductor device for IC card connected to the pin contact exposed on the outer surface of the IC card is located at both the top and bottom edges or both the left and right edges of the semiconductor device for IC card. 1. A semiconductor element for an IC card, wherein the semiconductor element is preferentially arranged in a manner that matches the arrangement of the pin contacts. (2) The semiconductor device for an IC card according to claim 1, wherein the arrangement of the pin contacts conforms to the ISO standard for IC cards.
JP1985174067U 1985-11-12 1985-11-12 Pending JPS6283672U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985174067U JPS6283672U (en) 1985-11-12 1985-11-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985174067U JPS6283672U (en) 1985-11-12 1985-11-12

Publications (1)

Publication Number Publication Date
JPS6283672U true JPS6283672U (en) 1987-05-28

Family

ID=31112118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985174067U Pending JPS6283672U (en) 1985-11-12 1985-11-12

Country Status (1)

Country Link
JP (1) JPS6283672U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5710258A (en) * 1980-05-20 1982-01-19 Gao Ges Automation Org Integrated circuit chip carrier element for identification card
JPS57122559A (en) * 1980-12-08 1982-07-30 Gao Ges Automation Org Integrated circuit module support

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5710258A (en) * 1980-05-20 1982-01-19 Gao Ges Automation Org Integrated circuit chip carrier element for identification card
JPS57122559A (en) * 1980-12-08 1982-07-30 Gao Ges Automation Org Integrated circuit module support

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