JPS628369A - Data read system - Google Patents

Abstract

PURPOSE:To read a record accurately even when a synchronizing signal representing the recording position of a data is not read/detected by arranging a re-synchronizing signal periodically in the data so as to use it for the correction of out of synchronism due to an error on the way of data read. CONSTITUTION:The re-synchronizing signal 23 is arranged at the head at a prescribed interval, that is, in the unit of S-byte. The re-synchronizing signal 23 is expressed as the same pattern as that of a synchronizing signal 21 such as (5AA5)16. In arranging the re-synchronizing signal 23 in the unit of prescribed bytes, re-synchronization is applied by using the signal 23 and out of synchronism in reading the succeeding data is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data reading method, and particularly to a data reading method in an information recording device such as a magnetic disk device, an optical disk device, or a magnetic tape device.

[Background of the invention]

Original disk drives are attracting attention as information recording devices that can record data at high density. The data reliability of the recording medium itself of this original disk is, for example, 1
The occurrence rate is about 0 to 10 times/bit,
Kouhei's magnetic disk 1 disk outfit! It is said that it is considerably worse than tic.

Therefore, for example, the data recorded on the optical disk medium may be KE
GG (Error Correcting Code
), efforts are being made to read data accurately and improve the error rate.

However, redundancy is insufficiently applied to synchronization information for reading data, and the synchronization information affects reliability when reading data.

[Purpose of the invention]

The object of the present invention is to provide 1. even when the synchronization signal indicating the data recording position of the data recording record cannot be read/detected. The object of the present invention is to provide a data reading method that allows the records to be read normally.

[Summary of the invention]

The present invention is considerably more powerful than the conventional method and can correct continuous errors of up to 806%, for example, several tens of bytes of data. A resynchronization signal is placed periodically in the data and is used to correct synchronization deviations due to errors during data reading. That is, when the initial synchronization signal cannot be detected, the resynchronization signals are used singly or collectively to compensate for the lack of synchronization signals.

[Embodiments of the invention]

This embodiment will be described on the assumption that an apparatus performs recording and reproduction using a frequency modulation method.

FIG. 1 is a block diagram of a general synchronization detection circuit to which this embodiment is applied.

In this figure, a read signal 1 read from a recording medium by a read head (not shown) is input to a read amplifier 2. It should be noted that the read head is configured as a magnetic transducer in a magnetic recording device;
In an optical disc device, it is configured as an optical recording/reproducing head.

A read signal 1 is amplified by a read amplifier 2, and its output is input to a variable harmonic oscillator (VFO) 3. A clock signal 12 is output from l"03, and a synchronization detector 4, which will be described later,
, a demodulator 5 and a reading circuit 6, and a read signal 10 synchronized with this clock signal 12 is sent to a synchronization detector 4.

A delayed modulation signal 11 is output from the synchronization detector 4 and input to the demodulator 5 . A demodulator 5 demodulates the modulated signal 11 into binary data and outputs this data to a reading circuit 6. The reading circuit 6 stores the demodulated data and also performs data error detection and correction.

Figure @2 shows the record format according to one example.

At the beginning of the record format is the VFO pull-in signal 2.
0 is recorded as a predetermined byte. This pull-in signal 20, for example, is entirely composed of a pattern of @1'. In this example, the next synchronization signal 21 is a synchronization pattern represented by (5AA5), for example. According to this synchronization signal 21, the reading timing of the subsequent data 22 is controlled.

In the data field 22, a data signal before demodulation is recorded.

According to the embodiment of the present invention, a resynchronization signal 25 is placed at the beginning of a predetermined interval, that is, in units of S bytes. In this example, this resynchronization signal 23 has the same pattern as the synchronization signal 21, namely (5AA5).

It is expressed as In the conventional technology that does not use the resynchronization signal 23 according to this embodiment, there is only one synchronization signal as shown by the signal 21, so if this synchronization signal 21 is not detected for some reason, subsequent Reading of data 22 will never be able to begin and all subsequent blocks of data will be lost. For example, synchronization signal 2
Even if 1 is detected, there is a risk that during data reading (if an excessive error occurs), a synchronization shift may occur, and data may continue to be read in accordance with this shifted synchronization signal.

On the other hand, if the resynchronization signal 23 is arranged in a predetermined byte unit as in this embodiment, resynchronization is performed by this signal 23, and when reading subsequent data,
Prevents synchronization.

FIG. 5 is a circuit block diagram showing details of the synchronization detector 4. In this figure, the read signal 10 is transmitted to the shift register 4.
1 is input. In addition, the synchronization turn (5AA5) constituting the synchronization signal 21.23 is stored in the register 43.The contents of both registers 41.43 are input to the comparator 42 and compared there. A clock signal 12 is applied to a shift register 41 and a comparator 42.The read signal 10 is read at a timing according to the clock signal 12, and is compared by the comparator 42 in synchronization with this clock signal 12. shift register 41
A delayed signal 11 of the read signal 10 is output. When the synchronization patterns match as a result of comparison in the comparator 42, a signal 13 indicating that the synchronization signal 21 or 23 has been detected is output.

8g4 shows peripheral circuit blocks of the synchronization detector 4. That is, the memory 8 is prepared according to this embodiment. Raw information including clock signals before demodulation is stored in this memory 8 (referred to as bit memory).In other words, when the synchronization pattern 21 detection operation is started, the shift register 41 in the synchronization detector 4 The parallelized raw information 44 is stored in the bit memory 8 at a predetermined period.

That is, the raw information 44 will be stored in the bit memory 8 regardless of the comparison result of the comparator 42.

The state of this operation is shown in FIG.

As shown in FIG. 5, the pull-in signal 20 represented by (FF) sent from the shift register 41 of the synchronization detector 4 is stored in addresses -n to 11 of the bit memory 8. (5AA5) Synchronization signal 2 represented by □6
1 is stored at addresses 0-1. Further, data 22 is stored from address 2 to address 28-1. Furthermore, resynchronization signal 2
3 is subsequently stored at addresses 28 and 2S+1.

Thereafter, data 22 in units of S bytes and resynchronization signal 23 are stored in consecutive addresses in the same manner.

In particular, we will explain how the resynchronization signal 23 (same as the synchronization signal 21) is stored. As shown in Figure 5 (bl), clock pits C and data pits D are
Stored in bytes.

Ru. Here, the synchronization pattern 21 or the resynchronization pattern 26
appears at a period corresponding to the S byte in FIG. 2 unless there is an error. In this example, since there is a clock every other time, 1 byte of data occupies 2 bytes of memory area.

If there is an error in the synchronization signal 21 or the resynchronization signal 23, or if a synchronization error occurs in the VFOs during the process, the synchronization signal indicated by (5AA5) may be replaced by the error pattern or another It will be stored at a shifted address.

FIG. 6 is a 70-chart for detecting the position of the pattern of the resynchronization signal 23 stored in the bit memory 8 shown in FIGS. 4 to 5.

After starting the process, first, the addressee and i are initialized (step 61). Here, A is bit memory 8
, and i indicates the address of the memory 8M (not shown). This memo IJSM is the frequency of occurrence of a resynchronization signal R1j), which will be described later.

This is a memory that temporarily stores the information described below during the process of obtaining the information, and is prepared, for example, in the reading circuit 6 described above.

Next, two bytes of information are read from the address (A-A+15) of the bit memory 8 (step 62).

Then, it is determined whether the information is a synchronization (resynchronization) pattern (step 63). As a result, if it is determined that the pattern is a synchronization pattern, the addressee is stored at address i in the memory SM and updated to l''1+1 (step 64). Thereafter, and if the result of the above determination is that it is not a synchronous pattern, the address A of the bit memory 8 is updated to A+1 (step 65).

Next, this address A is a predetermined address, that is, 2·K-8
It is determined whether or not the value exceeds (step 66). Here, S indicates the interval S bytes between resynchronization signals, and K indicates the number of resynchronization signals.

This determines whether all desired addresses in the bit memory 8 have been searched. If the result of the determination is negative, the above operation is repeated, and if they match, this operation ends (step 67).

The contents of pit memory 8 like this? : Comparator 42 in Fig. 3
, and the position of the resynchronization signal 25 [il
can be detected in units of clocks (-1/2 bits).

FIG. 7 shows the resynchronization signal obtained in FIG. 6 in the 20th S byte (i2 position (-Rtjl) position according to Modnlos from the beginning of the C pit memory 8) and the number ( =Qljl) is the flow factor to separate the resynchronization signal.Here, MOD is an operator that calculates the remainder, and I
NT is a function that calculates the luxury part. The resulting R
An example of the frequency of occurrence of each value of tjl is shown in FIG. If all synchronization signals, including resynchronization signals, are detected correctly.

In this case, the frequency of all synchronization signals is 8 at position P in Figure 8.
0 will appear. If the synchronization signal is out of sync,
As shown at 81, it is detected at a position that is slightly shifted from the original position P. Furthermore, if the data pattern is erroneously detected as a synchronization signal, it will be present at a distance from the position of P as shown at 82.

-fi In order to determine the position of this same xJJ signal in a state where the first synchronization signal 21 is not detected, for example, use the position P indicating the frequency of the pitch height in Fig. 8 or the central value of the concentrated part of the frequency. good.

Q with ga diagram! An example of reading data in the pit memory 8 using the determined position P of the synchronizing signal is shown in FIG. In the ninth cause, the position in pit memory B [P (5AA
5) Memorize the synchronization signal. This is done in order to correct the synchronization signal at a position where the synchronization signal is not detected or is detected at a deviated position. That is, since the position of the same signal where the error has occurred can be referred to from the contents of the memory SM shown in FIG. 6, the correct synchronizing signal is stored at that position. .

Therefore, at the stage when this storage operation is completed, all the synchronization signals are aligned to correspond to the position fftp. The contents of this memory 8 are read out from time to time according to the clock of the clock generator 7, and the signals 10' and 12' of FIG.
By inputting , it is possible to read a block of data.

In this operation, as shown in FIG. 8, even if there is an error in the resynchronization signal during the process, for example, a synchronization error error 81,
As long as this is within the range that can be recovered by a resynchronization signal, it is a matter of course that normal reading is possible with the operation shown in FIG. 9 as is. If an error outside the allowable margin is detected, its location can be identified using Q in FIG. This allows a normal read operation to occur by properly embedding the resynchronization signal in the bit memory 8 in advance.

Such advanced processing can be incorporated depending on the reliability required by the system.

In the above embodiments, a method has been described that collectively utilizes resynchronization signals periodically arranged in a data block. In this case, it is assumed that all raw data for one block before demodulation is stored in the memory.

However, depending on the reliability of the recording medium, for example, it may be possible to use a limited resynchronization signal at the beginning of a block. In this case, for example, if the first synchronization signal 21 in FIG. 2 is not detected, at least the first S bytes of data will be
For this part, which is not input to the reading circuit 6 shown in the figure, for example, S bytes of data of all degrees 0'' are forcibly input.

When the next resynchronization signal 23 is detected, the subsequent data is first input to the demodulation circuit 5 and the reading circuit 6 shown in FIG. The S bytes of will be corrected by the BCC. In other words, in line with the correction ability of 1!2cc,
It is fully possible to set the value of S in this way.

In addition, when using the first resynchronization signal preferentially for bank-up of the synchronization signal in this way, the synchronization signal and the backup resynchronization signal are omitted, and the first resynchronization signal is used instead of the normal resynchronization signal.
It is possible to configure it with high reliability (by providing redundancy in the number of synchronization holes).

〔Effect of the invention〕

According to the present invention, even if a synchronization signal for starting record reading 0 cannot be detected, many synchronization signals exist in subsequent data.

The resynchronization signal allows normal reading of the record. Furthermore, even if a large synchronization error occurs in a record, the record can be read normally by appropriately reproducing the resynchronization signal depending on the state of the resynchronization signal in the data.

[Brief explanation of drawings]

FIG. 1 is a block diagram of synchronization signal detection to which this embodiment is applied, FIG. 2 is a diagram showing an example of a record format according to an embodiment of the present invention, and FIG. 3 is a synchronization detector 4 shown in FIG. 1.
4 is a functional block diagram according to an embodiment of the present invention, FIG. 5 is a diagram illustrating the contents of the memory 8 shown in FIG. 4,
6 is a flowchart for detecting the resynchronization signal in the memory 8 of FIG. 4; FIG. 7 is a processing flowchart for statistically processing the position of the resynchronization signal from the results of FIG. FIG. 8 is a diagram showing the results of the statistical processing shown in FIG. 7, and FIG. 9 is a block diagram for reading data in the memory 8 using a synchronization signal. 1... Read signal 2... Read amplifier 3... Variable harmonic oscillator 4... Synchronization signal detector 5... Demodulator 6... Read circuit

Claims (4)

[Claims] (1) In a data block reading method that includes data and a synchronization signal to indicate the start point of this data, a resynchronization signal is placed in the data in order to resynchronize after data reading starts, and a synchronization signal is A data reading method characterized by reading data using this resynchronization signal if the data cannot be detected normally. (2) The data reading method according to item 1, wherein the resynchronization signal is placed at the beginning of a predetermined byte unit of data. (3) The first or second method has the step of determining the detection frequency and position of a synchronization signal including a resynchronization signal, and reads data in synchronization with a synchronization signal corresponding to a position where the frequency is highest. Data reading method described in Section 2. (4) It has a storage means for storing all information including the synchronization signal read from the recording medium, reads out a pattern indicating the synchronization signal from the storage means, and synchronizes the synchronization signal corresponding to the position where the synchronization signal is detected with the highest frequency. 4. The data reading method according to claim 3, characterized in that the signal is calculated.