JPS6284765U - - Google Patents
Info
- Publication number
- JPS6284765U JPS6284765U JP17722085U JP17722085U JPS6284765U JP S6284765 U JPS6284765 U JP S6284765U JP 17722085 U JP17722085 U JP 17722085U JP 17722085 U JP17722085 U JP 17722085U JP S6284765 U JPS6284765 U JP S6284765U
- Authority
- JP
- Japan
- Prior art keywords
- phase
- comparator
- type flip
- terminal
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000000819 phase cycle Methods 0.000 claims description 3
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000000605 extraction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Emergency Protection Circuit Devices (AREA)
Description
第１図は本考案の実施例の相順検出装置の回路
図、第２図は本考案の相順検出装置の原理説明図
、第３図は第１図の各部の波形図である。
１，２：コンパレータ、３：Ｄ形フリツプフロ
ツプ素子、４：ストロープ信号発生器、５：アン
ド素子。
FIG. 1 is a circuit diagram of a phase sequence detection device according to an embodiment of the present invention, FIG. 2 is a diagram explaining the principle of the phase sequence detection device of the present invention, and FIG. 3 is a waveform diagram of each part of FIG. 1. 1, 2: comparator, 3: D-type flip-flop element, 4: strobe signal generator, 5: AND element.
Claims (1)
する一相とそれより１２０°進んだ相とを第一の
コンパレータの入力端に、前記基準相より１２０
°遅れた相と基準相とを第二のコンパレータの入
力端に接続し、第一のコンパレータの出力端をＤ
形フリツプフロツプ素子のクロツクパルス入力端
子Ｃに、第二のコンパレータの出力端をＤ入力端
子に接続し、このＤ形フリツプフロツプ素子のＱ
出力端子を検相用信号引出端子としたことを特徴
とする相順検出装置。 A reference phase of three-phase alternating current whose voltage has been lowered through a transformer and a phase 120 degrees ahead of it are connected to the input terminals of the first comparator.
° Connect the delayed phase and the reference phase to the input terminal of the second comparator, and connect the output terminal of the first comparator to D
The output terminal of the second comparator is connected to the clock pulse input terminal C of the D-type flip-flop element, and the Q of this D-type flip-flop element is connected to the clock pulse input terminal C of the D-type flip-flop element.
A phase sequence detection device characterized in that the output terminal is a signal extraction terminal for phase detection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17722085U JPS6284765U (en) | 1985-11-18 | 1985-11-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17722085U JPS6284765U (en) | 1985-11-18 | 1985-11-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6284765U true JPS6284765U (en) | 1987-05-29 |
Family
ID=31118215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17722085U Pending JPS6284765U (en) | 1985-11-18 | 1985-11-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6284765U (en) |
-
1985
- 1985-11-18 JP JP17722085U patent/JPS6284765U/ja active Pending
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