JPS6284841U - - Google Patents
Info
- Publication number
- JPS6284841U JPS6284841U JP17717885U JP17717885U JPS6284841U JP S6284841 U JPS6284841 U JP S6284841U JP 17717885 U JP17717885 U JP 17717885U JP 17717885 U JP17717885 U JP 17717885U JP S6284841 U JPS6284841 U JP S6284841U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- program counter
- program
- input
- operation panel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005259 measurement Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図はこの考案の一実施例を示す計算機負荷
率計測装置のブロツク図、第２図は従来の計算機
負荷率計測のフローチヤートを示す図である。
図において、１は電子計算機、２はプログラム
カウンタ、３はプログラム、４はプログラムカウ
ンタ入力回路、５は操作パネル、６はプログラム
カウンタ比較回路、７は実行時間演算回路、８は
タイマ、９は負荷率演算回路、１０はＤ／Ａ変換
器、１１はアナログデータ出力機器である。
FIG. 1 is a block diagram of a computer load factor measuring device showing an embodiment of this invention, and FIG. 2 is a flow chart of conventional computer load factor measurement. In the figure, 1 is an electronic computer, 2 is a program counter, 3 is a program, 4 is a program counter input circuit, 5 is an operation panel, 6 is a program counter comparison circuit, 7 is an execution time calculation circuit, 8 is a timer, and 9 is a load 10 is a D/A converter, and 11 is an analog data output device.
Claims (1)
ログラムカウンタ入力回路と、プログラム実行時
間計測開始アドレスと終了アドレスおよびプログ
ラムのサイクルタイムを入力する操作パネルと、
上記プログラムカウンタ入力回路から入力された
アドレスと上記操作パネルから入力されたアドレ
スとを比較するプログラムカウンタ比較回路と、
タイマと、上記プログラムカウンタ比較回路から
の出力信号と、上記タイマの出力信号からプログ
ラム実行時間を計算する実行時間演算回路と、上
記操作パネルから入力したサイクルタイムから計
算機負筒率を計算する負荷率演算回路と、上記負
荷率演算回路の演算結果をアナログ出力するため
のＤ／Ａ変換器とを備えたことを特徴とする計算
機負荷率計測装置。 a program counter input circuit for reading the program counter of the electronic computer; an operation panel for inputting the program execution time measurement start and end addresses and program cycle time;
a program counter comparison circuit that compares the address input from the program counter input circuit and the address input from the operation panel;
a timer, an output signal from the program counter comparison circuit, an execution time calculation circuit that calculates the program execution time from the output signal of the timer, and a load factor that calculates the computer cylinder ratio from the cycle time input from the operation panel. A computer load factor measuring device comprising: an arithmetic circuit; and a D/A converter for analog outputting the arithmetic result of the load factor arithmetic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17717885U JPS6284841U (en) | 1985-11-18 | 1985-11-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17717885U JPS6284841U (en) | 1985-11-18 | 1985-11-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6284841U true JPS6284841U (en) | 1987-05-30 |
Family
ID=31118136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17717885U Pending JPS6284841U (en) | 1985-11-18 | 1985-11-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6284841U (en) |
-
1985
- 1985-11-18 JP JP17717885U patent/JPS6284841U/ja active Pending
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