JPS628512B2 - - Google Patents

Info

Publication number
JPS628512B2
JPS628512B2 JP12531879A JP12531879A JPS628512B2 JP S628512 B2 JPS628512 B2 JP S628512B2 JP 12531879 A JP12531879 A JP 12531879A JP 12531879 A JP12531879 A JP 12531879A JP S628512 B2 JPS628512 B2 JP S628512B2
Authority
JP
Japan
Prior art keywords
film
gas
plasma
heat treatment
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP12531879A
Other languages
Japanese (ja)
Other versions
JPS5651580A (en
Inventor
Yukio Tanuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP12531879A priority Critical patent/JPS5651580A/en
Publication of JPS5651580A publication Critical patent/JPS5651580A/en
Publication of JPS628512B2 publication Critical patent/JPS628512B2/ja
Granted legal-status Critical Current

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  • ing And Chemical Polishing (AREA)
  • Drying Of Semiconductors (AREA)

Description

【発明の詳細な説明】 本発明は改良されたプラズマエツチング方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved plasma etching method.

近年、平行平板電極に高周波(RF)電力を印
加し、導入したCF4やC2F6などのフロロカーボン
系の反応性ガスを放電させてガスプラズマを前記
電極間に形成せしめ、このガスプラズマ中の正イ
オンにより減圧下で前記電極上に置かれた半導体
ウエーハ(基体)表面の被膜をエツチングするこ
とが行なわれている。
In recent years, radio frequency (RF) power has been applied to parallel plate electrodes to discharge introduced fluorocarbon-based reactive gases such as CF 4 and C 2 F 6 to form gas plasma between the electrodes. Etching of a film on the surface of a semiconductor wafer (substrate) placed on the electrode is performed under reduced pressure using positive ions.

しかしプラズマエツチングに際しては、エツチ
ング終了の余裕度をみてオーバーエツチングを行
なうために半導体基体表面は相当に反応性のエツ
チング雰囲気にさらされることになる。このため
シリコン表面に欠陥層が形成され、又C、F等の
有機物や装置に起因するFe、Ni、Cr等の重金属
で汚染され、PN接合リークやフイールド電流の
不良、ソース、ドレインと金属配線とのコンタク
ト抵抗の増大を招いたりする。
However, during plasma etching, the surface of the semiconductor substrate is exposed to a considerably reactive etching atmosphere because over-etching is performed depending on the margin of completion of etching. As a result, a defective layer is formed on the silicon surface, and it is also contaminated with organic substances such as C and F, as well as heavy metals such as Fe, Ni, and Cr originating from the device, resulting in PN junction leakage, poor field current, source, drain, and metal wiring. This may lead to an increase in contact resistance with the

特にプラズマエツチング後の表面の熱酸化によ
りスタツキングフオールト(OSF:Oxidation
induced Stacking Fault)と呼ばれる膨大な結晶
欠陥を誘発する。
In particular, stacking faults (OSF) occur due to thermal oxidation of the surface after plasma etching.
This induces a huge number of crystal defects called induced stacking faults.

殊にボロンをプラズマエツチング箇所にイオン
注入したり、プラズマエツチング箇所にフイール
ド酸化膜など厚い熱酸化膜を形成すると著しい結
晶欠陥を生じる。
In particular, when boron ions are implanted into a plasma etched area or a thick thermal oxide film such as a field oxide film is formed at a plasma etched area, significant crystal defects occur.

本発明は上記事情に鑑みて為されたもので、減
圧下で炭素及びフツ素を含むガス、又は塩素を含
むガス等反応性ガスを放電せしめてガスプラズマ
を形成し、半導体装置製造の一工程として半導体
基体表面の被膜をプラズマエツチングしたのち、
前記エツチング箇所に対して不活性ガスを含む雰
囲気中で650℃以上の高温熱処理を行なうことを
特徴とするプラズマエツチング方法を提供するも
のであり、電気特性の改善を図ることが出来る。
The present invention has been made in view of the above circumstances, and involves discharging a reactive gas such as a gas containing carbon and fluorine or a gas containing chlorine under reduced pressure to form a gas plasma, which is a step in the manufacturing of semiconductor devices. After plasma etching the film on the surface of the semiconductor substrate as
The present invention provides a plasma etching method characterized in that the etched area is subjected to high-temperature heat treatment at 650° C. or higher in an atmosphere containing an inert gas, and electrical characteristics can be improved.

以下本発明の実施例を図面を参照して詳述す
る。
Embodiments of the present invention will be described in detail below with reference to the drawings.

先ずシリコン基板1にバツフアオキサイドとし
て700Å厚のシリコン酸化膜2を熱酸化形成し、
さらに選択酸化用の2000Å厚のシリコン窒化膜3
及びレジストマスク4を形成する(第1図a)。
次に先述平行平板型プラズマエツチング装置で
CF4+H2ガスを10-3Torr、180Wのもとで放電さ
せてプラズマエツチングを行ないフイールド部の
シリコン窒化膜3及びシリコン酸化膜2をエツチ
ングする(第1図b)。このとき基板1のエツチ
ング速度は数十Å/分と極めて遅いがプラズマ雰
囲気にさらされ、イオン衝撃を受けて欠陥層が形
成され、同時に先述有機物や重金属で汚染され
る。こののちフイールドボロンイオン注入を行な
いフイールドをウエツト酸化すると激しい密度
(約107コ/cm2)のOSFが発生する。
First, a silicon oxide film 2 with a thickness of 700 Å is formed as a buffer oxide on a silicon substrate 1 by thermal oxidation.
Furthermore, a 2000 Å thick silicon nitride film 3 for selective oxidation
and a resist mask 4 is formed (FIG. 1a).
Next, use the parallel plate plasma etching apparatus mentioned above.
Plasma etching is performed by discharging CF 4 +H 2 gas at 10 -3 Torr and 180 W to etch the silicon nitride film 3 and silicon oxide film 2 in the field portion (FIG. 1b). At this time, although the etching rate of the substrate 1 is extremely slow at several tens of angstroms per minute, it is exposed to a plasma atmosphere, receives ion bombardment, forms a defective layer, and at the same time becomes contaminated with the aforementioned organic substances and heavy metals. After this, when field boron ions are implanted and the field is wet oxidized, an OSF with a high density (approximately 10 7 ions/cm 2 ) is generated.

プラズマエツチング後に予め不活性ガス例えば
N2雰囲気中で1050℃で60分間高温熱処理を行な
うとOSFは〜103コ/cm2迄減少させることが出来
た。
After plasma etching, inert gas e.g.
When high temperature heat treatment was performed at 1050°C for 60 minutes in a N 2 atmosphere, the OSF could be reduced to ~10 3 /cm 2 .

第2図はN2熱処理を行なわなかつたもの(A)、
1050℃30分N2熱処理(B)、1050℃60分N2熱処理(C)
のOSF密度を示す。
Figure 2 shows one without N2 heat treatment (A);
1050℃ 30 minutes N2 heat treatment (B), 1050℃ 60 minutes N2 heat treatment (C)
shows the OSF density of

N2の他Ar、Heガスでも良い。 In addition to N2 , Ar or He gas may also be used.

熱処理温度は650℃以上特に1000℃より高温で
良いOSF低下が観られた。
Good OSF reduction was observed when the heat treatment temperature was higher than 650℃, especially higher than 1000℃.

又、この不活性ガス処理は前記ボロンイオン注
入の前やその前後両方において行なうとさらに有
効である。
Further, it is more effective if this inert gas treatment is performed before or both before and after the boron ion implantation.

不活性ガス処理の後CVDSiO2膜5を0.5μ堆積
してPOcl3ガス中で高温熱処理を行ない(第1図
c)、SiO2膜5を除去し、1×1013cm−のフイ
ールドボロンイオン注入層6を形成する(第1図
d)。
After inert gas treatment, a CVDSiO 2 film 5 of 0.5 μm was deposited and subjected to high-temperature heat treatment in POCl 3 gas (Fig. 1c), the SiO 2 film 5 was removed, and a field boron film of 1×10 13 cm− 2 was deposited. An ion implantation layer 6 is formed (FIG. 1d).

第1図cに示したCVDSiO2膜5堆積及びPocl3
処理は必ずしも必要でない。
CVDSiO 2 film 5 deposition and Pocl 3 shown in Figure 1c
Processing is not necessarily required.

こののち、ウエツト酸化で1μ厚のフイールド
酸化膜7を熱酸化形成し(第1図e)、膜2,3
を除去し(第1図f)、ゲート酸化膜8、多結晶
シリコン9、レジストマスク10を形成して(第
1図g)、レジストマスク10をエツチングマス
クとして先述したと同様に多結晶シリコン膜9、
ゲート酸化膜8をプラズマエツチングし、n+
オン注入層11,11′を形成する(第1図h)。
ここでのプラズマエツチング条件はCF4+H2、2
×10-2Torr、rf出力150Wであつた。このプラズ
マエツチングによりやはり損傷、汚染が先述した
ように生じる。
After this, a field oxide film 7 with a thickness of 1 μm is formed by thermal oxidation by wet oxidation (Fig. 1e), and films 2 and 3 are formed by thermal oxidation.
(FIG. 1f), a gate oxide film 8, polycrystalline silicon 9, and a resist mask 10 are formed (FIG. 1g), and the polycrystalline silicon film is etched using the resist mask 10 as an etching mask in the same manner as described above. 9,
Gate oxide film 8 is plasma etched to form n + ion implantation layers 11, 11' (FIG. 1h).
The plasma etching conditions here are CF 4 +H 2 , 2
×10 -2 Torr, RF output 150W. This plasma etching also causes damage and contamination as described above.

そこでN2+H2雰囲気中で高温熱処理を行な
う。
Therefore, high-temperature heat treatment is performed in an N 2 + H 2 atmosphere.

第3図はN2中にH2を10%含むガス中で30分
(B)、60分(C)夫々700℃で熱処理した場合と、この
処理を行なわれない場合のn+イオン注入層1
1,11′とこの層上に形成したAl電極とのコン
タクト抵抗を示す。コンタクト孔は3μ口であ
る。
Figure 3 shows 30 minutes in a gas containing 10% H2 in N2 .
(B), 60 minutes (C) N + ion implanted layer 1 with and without heat treatment at 700°C, respectively.
The contact resistance between layers 1 and 11' and the Al electrode formed on this layer is shown. The contact hole is 3μ.

本処理によりコンタクト抵抗は著しく減少し、
ドライ処理でない又等方性エツチングである弗化
アンモニウム溶液でコンタクト孔をエツチング形
成したもの(実線)と、匹敵する値が得られた。
熱処理は650〜1000℃、30分以上が好ましかつ
た。
This treatment significantly reduces contact resistance,
A value comparable to that obtained by etching contact holes with an ammonium fluoride solution (solid line), which is not a dry process or isotropic etching, was obtained.
The heat treatment was preferably performed at 650 to 1000°C for 30 minutes or more.

次にCVDSiO2膜12を堆積し(第1図i)、
BPSG膜13堆積(第1図j)、レジスト14に
よるコンタクト孔開口(第1図k)を行ないAl
電極15を形成して(第1図l)11,11′を
夫々ソース、ドレインとするMISトランジスタを
形成する。
Next, a CVDSiO 2 film 12 is deposited (Fig. 1i),
The BPSG film 13 is deposited (Fig. 1j) and the contact hole is opened using the resist 14 (Fig. 1k).
An electrode 15 is formed (FIG. 1l) to form a MIS transistor with 11 and 11' serving as a source and a drain, respectively.

尚、プラズマエツチングする半導体基体表面の
被膜としては酸化シリコン膜の他窒化シリコン
膜、多結晶シリコン膜、さらには金属シリコン合
金膜が使用出来、Alを含む場合にはCCl4でプラ
ズマエツチングすれば良い。
In addition to silicon oxide films, silicon nitride films, polycrystalline silicon films, and even metal silicon alloy films can be used as the film on the surface of the semiconductor substrate to be plasma etched.If Al is included, plasma etching may be performed with CCl 4 . .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a〜lは本発明の実施例を各工程に従い
示す断面図、第2図は本発明効果を示す特性図、
第3図は本発明効果を示す特性図である。
Figures 1a to 1 are cross-sectional views showing the embodiment of the present invention according to each step; Figure 2 is a characteristic diagram showing the effects of the present invention;
FIG. 3 is a characteristic diagram showing the effects of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 1 減圧下で炭素及びフツ素を含むガス、又は塩
素を含むガスを放電せしめてガスプラズマを形成
し、半導体装置製造の一工程として半導体基体表
面の被膜をエツチングしたのち、前記エツチング
箇所に対して不活性ガスを含む雰囲気中で650℃
以上の高温熱処理を行なうことを特徴とするプラ
ズマエツチング方法。
1. A gas containing carbon and fluorine, or a gas containing chlorine is discharged under reduced pressure to form a gas plasma, and a film on the surface of a semiconductor substrate is etched as a step of manufacturing a semiconductor device, and then the etched portion is etched. 650℃ in an atmosphere containing inert gas
A plasma etching method characterized by performing the above-mentioned high-temperature heat treatment.
JP12531879A 1979-10-01 1979-10-01 Plasma etching method Granted JPS5651580A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12531879A JPS5651580A (en) 1979-10-01 1979-10-01 Plasma etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12531879A JPS5651580A (en) 1979-10-01 1979-10-01 Plasma etching method

Publications (2)

Publication Number Publication Date
JPS5651580A JPS5651580A (en) 1981-05-09
JPS628512B2 true JPS628512B2 (en) 1987-02-23

Family

ID=14907132

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12531879A Granted JPS5651580A (en) 1979-10-01 1979-10-01 Plasma etching method

Country Status (1)

Country Link
JP (1) JPS5651580A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63243615A (en) * 1987-03-31 1988-10-11 Matsushita Electric Ind Co Ltd liquid fuel combustion equipment

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59110119A (en) * 1982-12-15 1984-06-26 Nec Corp Surface processing for semiconductor layer
JPH0656846B2 (en) * 1983-04-29 1994-07-27 ソニー株式会社 Method for treating semiconductor substrate
JPH0624190B2 (en) * 1984-12-21 1994-03-30 株式会社東芝 Wiring formation method
JPS6466544A (en) * 1987-09-08 1989-03-13 Fuji Photo Film Co Ltd Chemical analyzer
JPH01206620A (en) * 1988-02-15 1989-08-18 Toshiba Corp Manufacture of semiconductor device
JP6597296B2 (en) * 2015-12-25 2019-10-30 東京エレクトロン株式会社 Substrate processing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63243615A (en) * 1987-03-31 1988-10-11 Matsushita Electric Ind Co Ltd liquid fuel combustion equipment

Also Published As

Publication number Publication date
JPS5651580A (en) 1981-05-09

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