JPS628558A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make it possible to write data after data-line forming processes and to shorten process completing time, by extending the data lines, which are connected to memory cell rows, to the outside of the upper parts of the channel forming region of an MISFET, in a logitudinal mask ROM. CONSTITUTION:Conductor layers 10A and 10B are electrically connected to specified semiconductor regions 7 and 8 through a connecting hole 9A. The upper part of an insulating film 9 is extended to the direction of rows. Data lines are extended to the outside of the upper parts of the channel forming regions of memory cells Q1-Q8. After the forming processes of the memory cells Q1-Q8 and the data lines DLs, n-type impurity ions are introduced in the channel forming region 2 through gate electrode 6A by ion implantation technology. Thus the first threshold voltage is converted into the second threshold voltage. After the forming processes of the data lines DLs, the data is written.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device having a nonvolatile memory function.

[Background Art] As a semiconductor integrated circuit device having a non-volatile memory function,
Mask ROM with low cost and excellent safety against information destruction
(Read Only Memory) is used. Vertical (serial) mask ROMs can be more highly integrated than horizontal (parallel) mask ROMs.

It has the feature of increasing the capacity of information. For this reason, the vertical mask R□'M is in high demand as a storage device for speech analysis and character information.

The memory cells of the vertical mask ROM are composed of MISFETs, and there are 8, 16, .
. . . are connected in series to form a unit memory cell row with a bit configuration. The memory cells are connected in series by sharing the source region or drain region of MISFETs adjacent in the row direction.

Vertical mask ROM 11 Q 11 , It l I
Writing of I information is generally performed by replacing a predetermined enhancement type MISFET ("O" information) with a depletion type MISFET ('"1" information. After formation, phosphorus is introduced into the channel formation region of a predetermined MISFET using ion implantation technology, and the threshold voltage is changed.According to this writing means, information can be written after the MISFET is formed. The time required to complete the process (product completion) (hereinafter referred to as process completion time) can be shortened.

However, the inventor of the present invention found a problem that the process completion time could not be sufficiently shortened because there is a step of forming data lines connected to the memory cell row, a passivation film, etc. after writing information.

This problem arises because the gate electrode and data line (for example, aluminum wiring) extend above the channel formation region of the MI S FET, and impurities cannot be introduced into the channel formation region.

Therefore, it may be possible to shorten the process completion time by introducing impurities into the channel forming regions of MIS and FETs through the data lines and gate electrodes after the data line forming process.

However, with the currently used ion implantation equipment with a low energy of several tens to hundreds of KeVT, impurities cannot be introduced into the channel forming region through the data line, so information cannot be written.

The mask ROM is described in, for example, Science Forum 1 Co., Ltd., "Very LSI Device Handbook," published November 28, 1980, pages 313 to 315.

[Object of the Invention] An object of the present invention is to provide a technique that can shorten the process completion time in a vertical mask ROM.

Another object of the present invention is to provide a technique in which information can be written in a vertical mask ROM after a data line forming process.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Overview of R-ming] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

That is, in a vertical mask ROM using MISFETs as memory cells, data lines connected to memory cell rows are extended beyond the upper part of the channel formation region of the MISFETs.

Thereby, information can be written after the data line forming process, so the process completion time can be shortened. In addition, impurities can be introduced into the channel forming region through the MISFET's goo 1 to electrode without passing through the data line.
Information can be written using a low-energy ion implanter.

Below, regarding the configuration of the present invention, the n-channel MISFET
The present invention will be described along with an embodiment in which the present invention is applied to a vertical mask ROM having a memory cell.

In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiment] A vertical mask ROM which is an embodiment of the present invention is shown in the equivalent circuit diagram of FIG.

In FIG. 1, Qs to Q8 are memory cells II
It is composed of an enhancement type (first threshold voltage) M r S FET that provides Q11 information.

Memory cells Q1 to Q8 are connected to a word line WL connected to an X decoder Xdec.
The structure is such that conduction and non-conduction are controlled. Memory cell Q I-Q a has 8 (or 16, 32, etc.) MISFETs connected in series, sharing the source region or drain region, and forms a unit memory cell row of 8 bits. are doing.

A unit memory cell row is configured in a pair of symmetrical shapes in the row direction via column switches Qs controlled by a first Y decoder Ydect. This pair of unit memory cell rows is
Multiple rows and columns are arranged in a repeating pattern,
It constitutes a memory cell array MA.

In the figure, the memory cell Q2 surrounded by a dotted line is LL 11+
Information is written therein, and it is composed of a depletion type (second threshold voltage) MI S FET.

This memory cell Q2 is an enhancement type MISF
The threshold voltage is changed by introducing a mouth-type impurity such as phosphorus (or arsenic) into the channel formation region of the ET, and the source region and drain region are configured in a conductive state.

The unit memory cell row has one end connected to a reference voltage VsS (for example, circuit ground potential 0 [V]), and the other end connected to a second Y decoder Ydec2 via a column switch Qs, data, and IXDL. ing. The second Y decoder Ydec2 includes a select decoder composed of MISFETQc controlled by select signals A1 to A6 that select the data line DL, and a precharge select signal P.
MISFET Qp controlled by ce.

Vcc is the power supply voltage (for example, the circuit operating voltage 5 [■)]
, 0ul=I Q II of a predetermined memory cell Q,
II I 11 information to sense amplifier (not shown)
This is an output terminal that outputs to.

Next, a specific configuration of this embodiment will be explained.

A memory cell array of a vertical mask ROM, which is an embodiment of the present invention, is shown in a plan view of main parts in FIG. 2, and a cross section taken along the line 2--2 in FIG. 2 is shown in FIG. Note that in FIG. 2, insulating films other than the field insulating film provided between each conductive layer are not shown in order to make the configuration of this embodiment easier to understand.

In FIGS. 2 and 3, 1 is an n-type semiconductor substrate made of single crystal silicon, and 2 is a P-type well region. Field insulating film 3 (insulating film for isolation between elements) and P
A type channel stopper region 4 is provided and is configured to electrically isolate semiconductor elements.

The M I S FETs serving as memory cells Q1 to Q8 are composed of a well region 2 (channel formation region), a gate insulating film 5, a gate electrode 6A, and an A-shaped semiconductor region 7 used as a source region or a drain region. There is.

Column switch Qs is connected to well region 2. Gate insulating film 5
, a gate electrode 6B, and a diamond-shaped semiconductor region 7 used as a source region or a drain region.

The gate electrode 6A or 6B is formed integrally with an adjacent one in the column direction, and constitutes a word line (WL) 6G or 6D.

the gate electrodes 6A, 6B and the word line (WL) 6G,
(3D means, for example, polycrystalline silicon film, high melting point metal (M
o, Ti, Ta, W) films, high melting point metal silicide (M
oSi2. TiSi2. TaSi2. WSi2) film or polycide (MoSi2.TiSi2.Ta5i2jW
It is composed of a Si2/poly Si) film.

Reference numeral 8 denotes a P'''' type semiconductor region provided on the main surface of the well region 2, such as between rows of unit memory cells, and is connected to a reference voltage Vss.
are connected to each other so as to maintain the potential of the well region 2 stably.

9 is an insulating film covering semiconductor elements such as MISFETQ and Qs, 9A is a connection hole 610A formed by removing insulation 1119 on the top of predetermined semiconductor regions 7 and 8, IOB is a conductive layer, and connection hole 9A is through a predetermined semiconductor region 7,
8 and extending in the row direction above the insulating film 9.

The conductive layer 10A constitutes a data line (DL) connected to a predetermined memory cell row, and serves as the memory cells QI to Q8.
It is configured to extend beyond the upper part of the channel forming region of the I S FET. That is, the conductive layer 10A is provided extending in the same direction as the extending direction of the upper part of the field insulating film 3 that surrounds the unit memory cell row and defines its shape.

In this way, by extending the data line beyond the upper part of the channel formation region of the memory cells QI-Qa, after the process of forming the memory cells Q1 to Q8 and the data line DL,
The first threshold voltage can be changed to the second threshold voltage by introducing an n-type impurity, such as phosphorus (or arsenic), into the channel forming region (well region 2) through the gate electrode 6A using ion implantation technology. Therefore, information can be written after the data line DL forming process. As a result, the time required to complete the vertical mask ROM process can be shortened.

The n-type impurity introduced for writing information, such as phosphorus (or arsenic), is surrounded by a dashed line in FIG.
It is designed to be introduced within the area marked with .

Further, since impurities can be introduced into the channel forming region through the gate electrode 6A of the MISFET without passing through the data line DL, information can be written using an ion implantation device with a low energy of several tens to several hundreds [KeV].

Furthermore, by extending the data line I)L above the field insulating film 3 between unit memory cell rows, it is possible to form a barrier for impurities introduced to write information on the top of the field insulating film 3. It is possible to prevent the threshold voltage of the parasitic MO3 from decreasing due to the impurity being captured in the field insulating film 3 portion. Furthermore, the data line DL is
It is possible to suppress the field insulating film 3 from being contaminated by sodium ions and the like, and to prevent the threshold voltage of the parasitic MOS- from decreasing. This makes it possible to reliably electrically isolate the memory cells 01 to 08 arranged in one column direction.

Further, it is preferable that the conductive layer (DL) IOA has a smaller dimension than the width dimension of the field insulating film 3 between the unit memory cell rows. The width of the field insulating film 3 may be larger than the width of the field insulating film 3, as long as the parasitic resistance value of the field insulating film 3 is within an allowable range.

A reference voltage Vss is applied to the conductive layer 10B, and the conductive layer 10B is connected to the well region 2 through one end of the unit memory cell row and the semiconductor region 8.

The conductive layers 10A and IOB are made of, for example, an aluminum film or an aluminum film containing a predetermined additive.

Note that in this embodiment, the conductive layer (DL) IO
Although A is bent above the column switch Qs, the present invention is not limited thereto. For example, a conductive layer (DL) IOA may be extended straight beyond the upper part of the channel formation region of the memory cells Q1 to Q8.

Semiconductor region 7 serving as a drain region of column switch Qs
is configured in an L-shape to form the conductive J! It may be electrically connected to the IOA.

Further, the present invention provides a method for connecting a predetermined MISFET (for example, column switch Qs) to LDD (Lightly D
It may also be configured with a double drain structure in which a semiconductor region with a low impurity concentration is provided along a semiconductor region with a high impurity concentration.

[Effects] As explained above, according to the novel technology disclosed in this application, the following effects can be obtained.

(1) Vertical mask RO using MISFET as a memory cell
In M, the data line connected to the memory cell row is connected to M.
By extending beyond the upper part of the channel formation region of the ISFET, information can be written after the data line formation process, so the process completion time can be shortened.

(2) According to (1) above, MISF is connected without passing the data line.
Since impurities can be introduced into the channel forming region through the gate electrode of the ET, information can be written using a low energy ion implantation device.

(3) According to (1) and (2) above, vertical mask ROM
In this method, it is possible to shorten the process completion time and write information using low-energy ion implantation technology.

The invention made by the present inventor has been specifically explained above based on the above embodiments, but the present invention is as follows.

It goes without saying that the embodiments are not limited to the embodiments described above, and that various modifications can be made without departing from the spirit of the embodiments.

For example, the present invention may be applied to a vertical mask ROM using a p-channel MISFET as a memory cell.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram of a vertical mask ROM which is an embodiment of the present invention. FIG. 2 is a plan view of a main part of a memory cell array of a vertical mask ROM which is an embodiment of the present invention. FIG. 3 is a sectional view taken along the line ■-■ in FIG. 2. In the figure, Q: memory cell, X dec: X decoder, Ydec: Y decoder, MA: memory cell array. WL, t3c, 6D...word line, DL...data line. Vss...Reference voltage, Vcc...Power supply voltage, 1...
- Semiconductor substrate, 2... Well region, 3... Field insulating film, 5... Gate insulating film, 6A, 6B... Gate electrode, 7... Semiconductor region, IOA, 10B...
It is a conductive layer. Figure 1

Claims (1)

[Claims] 1. A plurality of memory cells each consisting of MISFETs having a first threshold voltage are connected in series to form a memory cell row, and a channel forming region of the MISFET having a predetermined first threshold voltage; A semiconductor integrated circuit device having a nonvolatile memory function that constitutes a memory cell composed of MISFETs having a second threshold voltage by introducing impurities into the memory cell row, the data line connected to the memory cell row is The MISFET
1. A semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is configured to extend beyond the upper part of a channel forming region. 2. The semiconductor integrated circuit device according to claim 1, wherein the impurity is introduced into the channel forming region through the gate electrode by ion implantation technology. 3. The semiconductor integrated circuit device according to claim 1, wherein the data line extends above an isolation insulating film between adjacent memory cell rows in the column direction. 4. The semiconductor integrated circuit device according to claim 1, wherein the memory cell is configured as a vertical mask ROM.