JPS6286739U - - Google Patents
Info
- Publication number
- JPS6286739U JPS6286739U JP17745585U JP17745585U JPS6286739U JP S6286739 U JPS6286739 U JP S6286739U JP 17745585 U JP17745585 U JP 17745585U JP 17745585 U JP17745585 U JP 17745585U JP S6286739 U JPS6286739 U JP S6286739U
- Authority
- JP
- Japan
- Prior art keywords
- digital signal
- analog switches
- voltage
- control circuit
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Description
第１図は本考案によるレベル変換回路の一実施
例を示す基本的な系統ブロツク図、第２図は従来
例によるバツフア回路の等価回路図である。
１……アナログスイツチＳＷ、２……アナログ
スイツチ、３……制御回路、４……コントロール
入力端子、５……アナログスイツチ１の入力端子
、６……アナログスイツチ２の入力端子、７……
出力端子。
FIG. 1 is a basic system block diagram showing one embodiment of a level conversion circuit according to the present invention, and FIG. 2 is an equivalent circuit diagram of a conventional buffer circuit. 1...Analog switch SW, 2...Analog switch, 3...Control circuit, 4...Control input terminal, 5...Input terminal of analog switch 1, 6...Input terminal of analog switch 2, 7...
Output terminal.
Claims (1)
スイツチをコントロールする制御回路を備え、前
記２つのアナグロスイツチの各一端をそれぞれ入
力端子とし、かつそれらの他端を共通接続して出
力端子として取り出し、前記各アナログスイツチ
の入力端子にそれぞれ異なる第１及び第２の電圧
を加えるとともに、前記制御回路にデジタル信号
を加えることにより、該デジタル信号を前記第１
及び第２の電圧で決まるデジタル信号に変換する
ようにしたことを特徴とするレベル変換回路。 It is equipped with two analog switches and a control circuit for controlling the two analog switches, one end of each of the two analog switches is used as an input terminal, and the other ends are commonly connected and taken out as an output terminal. By applying different first and second voltages to the input terminals of the analog switch, and applying a digital signal to the control circuit, the digital signal is converted to the first voltage.
and a level conversion circuit that converts into a digital signal determined by a second voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17745585U JPS6286739U (en) | 1985-11-20 | 1985-11-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17745585U JPS6286739U (en) | 1985-11-20 | 1985-11-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6286739U true JPS6286739U (en) | 1987-06-03 |
Family
ID=31118669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17745585U Pending JPS6286739U (en) | 1985-11-20 | 1985-11-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6286739U (en) |
-
1985
- 1985-11-20 JP JP17745585U patent/JPS6286739U/ja active Pending