JPS628731U - - Google Patents
Info
- Publication number
- JPS628731U JPS628731U JP10016685U JP10016685U JPS628731U JP S628731 U JPS628731 U JP S628731U JP 10016685 U JP10016685 U JP 10016685U JP 10016685 U JP10016685 U JP 10016685U JP S628731 U JPS628731 U JP S628731U
- Authority
- JP
- Japan
- Prior art keywords
- functional
- time
- function value
- analog
- converter according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012887 quadratic function Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の１実施例を示した要部回路図
、第２図はその動作例タイムチヤート、第３図は
本考案による関数発生回路例図、第４図は他の関
数発生回路例図、第５図は従来例の概略図、第６
図はその変換特性図である。
３はカウンタ、４はセツトリセツトフリツプフ
ロツプ、５は信号源ないし関数発生器、６はサン
プルホールド回路である。
Fig. 1 is a main circuit diagram showing one embodiment of the present invention, Fig. 2 is a time chart of an example of its operation, Fig. 3 is an example of a function generating circuit according to the present invention, and Fig. 4 is another function generating circuit. Example diagram, Figure 5 is a schematic diagram of the conventional example, Figure 6 is a schematic diagram of the conventional example.
The figure shows the conversion characteristics. 3 is a counter, 4 is a set/reset flip-flop, 5 is a signal source or function generator, and 6 is a sample and hold circuit.
Claims (1)
カウンタと、計時時間のセツト時に動作しそのリ
セツト時に動作が停止するようにした時間関数ア
ナログ演算器と、停止したときの関数値を読みと
る保持回路とを具有していることを特徴とする、
関数型Ｄ／Ａ変換器。 (2) アナログ演算器が２段の積分器からなり、
２次関数値が得られることを特徴とする、実用新
案登録請求の範囲第１項に記載の関数型Ｄ／Ａ変
換器。 (3) アナログ演算器がＣＲ回路からなり、指数
関数値が得られることを特徴とする、実用新案登
録請求の範囲第１項に記載の関数型Ｄ／Ａ変換器
。[Scope of Claim for Utility Model Registration] (1) A counter that measures time corresponding to a digital input value, a time function analog calculator that operates when the clock time is set and stops operating when the time is reset, and and a holding circuit that reads the function value when
Functional D/A converter. (2) The analog computing unit consists of a two-stage integrator,
A functional D/A converter according to claim 1, characterized in that a quadratic function value is obtained. (3) The functional D/A converter according to claim 1, wherein the analog arithmetic unit is composed of a CR circuit and is capable of obtaining an exponential function value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10016685U JPS628731U (en) | 1985-06-29 | 1985-06-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10016685U JPS628731U (en) | 1985-06-29 | 1985-06-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS628731U true JPS628731U (en) | 1987-01-20 |
Family
ID=30969727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10016685U Pending JPS628731U (en) | 1985-06-29 | 1985-06-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS628731U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60100901A (en) * | 1983-10-11 | 1985-06-04 | アイテイダブリユ‐アテコ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Apparatus for producing belt or similar tensioning article |
-
1985
- 1985-06-29 JP JP10016685U patent/JPS628731U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60100901A (en) * | 1983-10-11 | 1985-06-04 | アイテイダブリユ‐アテコ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Apparatus for producing belt or similar tensioning article |
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