JPS6299976A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce a through current flowing through the memory cell of a nonselected data line side so as to reduce power consumption, by providing a data line load element at each data line and turning on the elements in accordance with the selected level of a data line selecting signal. CONSTITUTION:Pairs of input-output terminals of static memory cells 1a, 1b and 1c, 1d are connected with corresponding pairs of data lines D1 and the inverse of D1 and Dn and the inverse of Dn and the drain of a data line load MOSFET Q9 is coupled with the data lines and the source is coupled with a power supply terminal VCC through a level shift MOSFET Q11. When a data line selecting signal it at its non-selecting level and the data line connected with the signal is not selected, the MOSFET Q9 is turned on and gives a bias voltage or reference potential to the data line. Therefore, the through current flowing from transfer MOSFETs Q3 and Q4 of the memory cells having no relation with data readout through differential MOSFETs Q1 and Q2 is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor memory device, such as a MOSFE device.
The present invention relates to a technique that is effective when applied to a static RAM (Rung 15 access memory) configured with T (insulated gate field effect transistor).

[Background technology]

In a MOS static RAM, a plurality of memory cells are usually arranged in a 71-plex shape. Place +i on the same line? The selection terminals of the multiple memory cells arranged in the row are commonly connected to one word line corresponding to that row, and the data input/output terminals of the multiple memory cells arranged in the same column are commonly connected to the data line corresponding to that column. The six connected data lines are connected to a common data line via a column switch circuit.

The input terminal of the sense amplifier and the output terminal of the write circuit are coupled to the common data line.

Therefore, data in one memory cell selected by the word line and column switch circuit is supplied to the sense amplifier.

By the way, a data line load MO8FET which is always on is provided between the data line and the power supply terminal.
This data line load MO8FET allows the potential of the data line to be brought to a desired level before starting data reading.

When such a data line load MO8FET is provided, when a predetermined word line is selected, the selection terminals of all memory cells connected to that word line are turned on.
Through-current flows through the static flip-flop circuit in the memory cell connected to these selection terminals via the data line selection element. This through current occurs in all memory cells connected to one selected word line, so even if only one memory cell is selected, a wasteful current flows in many memory cells. Power consumption will increase.

In particular, in order to achieve high-speed data readout, it is effective to reduce the potential difference applied between the data lines by increasing the mutual conductance of the data line load MO8FET. It will increase further.

An example of a document describing a MOS static RAM equipped with a data line load MO8FET is Japanese Patent Laid-Open No. 57-127989.

[Object 1 of the Invention] An object of the present invention is to provide a semiconductor memory device that can reduce through current flowing from a data line load element through a memory cell, thereby achieving reduction in power consumption. There is a particular thing.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in the present application is as follows. A MO3FET and a low-resistance second data line load MO8FET are provided on each data line, and the second data line load MO8 is set depending on the selection level of the data line selection signal.
By turning on the FET and turning on the first data line negative MO8FET by its unselected level, the through current flowing from the first data line load MO3FET through the memory cell is reduced, thereby reducing power consumption. .

〔Example〕

FIG. 1 is a circuit diagram showing a static RAM which is one embodiment of the present invention.

The static RAM shown in the figure is formed on one semiconductor substrate using known semiconductor integrated circuit technology. Terminal AX
I to AXk, AYI-AYk, Dout, Din and Vec are its external terminals. This static RA
M is operated by being supplied with a power supply voltage from an external power supply device (not shown) provided between the power supply terminal cc and the ground terminal.

Are you talented at drawings? 1 is a memory array, representatively shown are static memory cells Ia to 1d, word lines WL to Wn, and data lines Di, I')1, Dn.

It is composed of Dn.

The static memory cells 1a to 1d have the same configuration, and although not particularly limited, as shown in detail with 1a as a representative, differential MO8FETQI,
A static type flip-flop circuit composed of Q2 and load resistances R1 and R2, and an input/output terminal of this static type flip-flop circuit and a pair of data lines Di and Di.
N-channel type transfer MO3FETQ3. It consists of Q4.

The static memory cell has the load resistances R1, R
Data is held by supplying the power supply voltage applied to the power supply terminal Vcc to the connection point No. 2.

The static memory cells 1a''ld are arranged in a matrix as shown in the figure.Among the static memory cells 1a to 1d arranged in a matrix, the static memory cells lap are arranged in the same row.
Transfer MO8FETQ3. constitutes selection terminals of lc, lb, and ld. The gate of Q4 is connected to the corresponding word line Wl.

On the other hand, a pair of input/output terminals of static memory cells la, lh and lee ld arranged in the same column are connected to a pair of data lines Di and D corresponding to each other.
i, Dn, and Dn.

The data lines Di, D1 and Dn, Dn corresponding to each column are connected to N-channel type data line selection MO3FETQ5. It is connected to common data 1icD and CD via Q6 and Q7°Q8.

The word lines W1 to Wn are connected to the X address decoder circuit 2.
is connected to the output terminal of this X address decoder circuit 2.
The selected word line is selected by the word line selection signal output from the word line selection signal.

In this embodiment, the high level of the word line selection signal is the word line selection level. Note that this X address decoder circuit 2 is supplied with a chip select signal C8 as an external signal. When the chip select signal O8 is set to the chip non-select level, the X address decoder circuit 2 puts all the word lines Wi and Wn into a non-selected state.

A pair of data line selection MOSFETs Q5 provided corresponding to each column of the memory matrix. Q6 and Q7. The gates of Q8 are connected to the output terminals of the Y address decoder circuit 3, and are selected by data line selection No. 43 output from the Y address decoder circuit 3. In this embodiment, the high level of the data line selection signal is the data line selection level.

Address signals supplied to address input terminals AXI to AXk are input to the X address decoder circuit 2 via address buffer circuits BXI to BX,k.

Similarly, address signals supplied to address input terminals AYI to AYk are input to the Y address decoder circuit 3 via address buffer circuits BYI to BYk.

The pair of common data lines CD, CD are connected to the input terminal of the sense amplifier 4 on one side and the output terminal of the write circuit 5 on the other side.

The output signal of the sense amplifier 4 is supplied to the data output terminal Dout via the output sofa circuit 6.

A signal input from the data input terminal 1) in is supplied to the write circuit 5 via the input buffer circuit 7.

Each of the data lines Di, Di, Dn, and Dn has
In order to set the potential of the data line to a reference potential before starting data reading, the P-channel type
Data line load MO9FETQ9 and N exhibiting low on-resistance
A channel type second data line load MO8FETQIO is provided.

The first data line load MO3FETQ9 has its drain coupled to the data line, and its source.

The power supply terminal V c is connected via an N-channel level shift MO5FET QII whose gate and drain are coupled.
connected to c. Refuse M OS F' E 'I'Q
Reference numeral 9 is turned on when the data line selection signal is set to a non-selection level (low level), that is, when the data line connected to it is not selected, and a bias voltage or a bias voltage is applied to the unselected data line. Base 1!
! Give a potential. This bias voltage is applied to a data line connected to a memory cell from which data is not read, and simply maintains the level of the data line at a predetermined level in preparation for the next data read. It is sufficient if it is possible. Therefore, the first data line load MOSFE TQ 9 has a relatively small mutual conductance, that is, a high resistance, and is also small in size.

Therefore, among the memory cells connected to the word line selected based on the word line selection signal, those connected to the data line not selected based on the data line selection signal, that is, those that are unrelated to data reading. Regarding memory cells, please refer to the memo'J
Mo S F E TQ 3 (O4) to differential MO8F
The through current flowing through E''l'Q1 (O2) is reduced.

Note that when all the data lines are unselected (chip non-selection), all the first data line loads MOS F E
TQ 9 is turned on and the bias voltage is supplied to each data line. At this time, all word lines are also set to a non-selected state by the chip select signal C8 at a non-select level, and all transfer lines are turned on. MO5FETQ
3. Q4 is turned off. Therefore, even if the chip non-selection period extends for a long time, there is no risk that the information stored in the memory cells will be destroyed by the bias voltages supplied to each data line.

Here, since the level shift MO8FET QII has its gate and drain coupled together, a voltage drop approximately equal to its threshold voltage occurs between its source and drain. Therefore, the first data line load M
The bias voltage applied to the data line via the O5FETQ9 is a voltage whose level is lowered by the level shift MO3FETQII with respect to the power supply voltage supplied to the power supply terminal Vcc. Therefore, data line selection (
When a predetermined data line is selected based on No. 4, the data line selection MO8FETQ5. Q
6 (O7, O8) is guaranteed, and high-speed data reading is achieved.

The second data line load MO8FETQIO has its source coupled to the data line, and its drain coupled to the power supply terminal Vcc. Such MO8FETQ10, when the data line selection signal is set to selection level (high level), that is, when the data line connected to it is selected,
It is turned on and applies a bias voltage to the selected data line.

Here, the second data line load MO8FETQ10 is
The mutual conductance is the first data line load MO5.
It is set to be larger than FETQ9, that is, to have a low resistance. This mutual conductance is almost the same as a data line load MO8FET that is conventionally placed between each data line and a power supply terminal in a always-on state, and the potential of the data line that should be at a low level when reading data is kept at a relatively high level. It is set to a value that causes the level to change. Therefore, when a bias voltage is applied to a predetermined data line by such a load MO8FETQIO, the level change speed of that data line is increased, and data can be read out at high speed.

In particular, such load MO5FETQIO is connected to MO5FETQ5. It is turned on almost in synchronization with the on operation of O6 (O7, O8). therefore,
As mentioned above, the level of the data line to which the bias voltage is applied is relatively low.

The transition time until the complementary level of read data is determined can be shortened.

In the figure, O12 is a P-channel equalizer MO3FE whose switch is controlled by a data line selection signal.
T, whose drain and source are connected to a pair of data lines Di
, Di and Dn, and is turned on when the data line selection signal is at the non-selection level (low level). When MO5FETQ12 is turned on, the levels between the pair of data lines, which have been set to complementary levels by data reading, are balanced. For example, when memory cells that store different data and are connected to the same data line are sequentially read by switching addresses, the potential difference between the data lines that occurs when reading the first memory cell is used to read the next memory cell. need to be reversed. That is, the high level data line is lowered to the low level by the memory cell, and the low level data line is changed to the first. Pull data line load M to high level with O3FETQ9. ”−
The equalizer MO8FETQ12 reduces the time delay required for inversion of the data lines by forcibly equalizing the levels between the pair of data lines that are set to complementary levels. Particularly in the case of this embodiment, the bias voltage is supplied to the unselected data line by the first data line loads MO3F and ETQ9 as described above,
Since TQ9 is set to have a high resistance in order to reduce power consumption, it is significant to provide the equalizer MO8FETQ12 in the sense of compensating for the time delay required for inversion of the data line.

According to this embodiment, the second data line load MO5F with low resistance
Only the ETQIO connected to the data line in one selected memory cell is turned on, and the other data lines are connected to the high resistance first data line load MO8.
FETQ9 is turned on. As a result, the bias voltage necessary for high-speed data reading is quickly supplied only to the data line involved in reading data, and the bias voltage is supplied to the other data lines more slowly than the data line. Therefore, among the memory cells connected to one selected word line, those connected to data lines that are not selected based on the data line selection signal, that is, the majority of memory cells that are unrelated to data reading, Transfer MO3FETQ3 (Q
From 4), the through current flowing through the differential MO8FET QI (Q2) can be reduced.

In this manner, in the majority of memory cells in the same row other than one memory cell selected when reading data, wasteful through current flowing therein is alleviated, and power consumption can be significantly reduced. Moreover, since the degree of reduction in power consumption is extremely large, the memory cells can be freely laid out without having to adopt a divided configuration of the memory cell array that is used for the same purpose.

〔Effect of the invention〕

As is clear from the following explanation, the invention disclosed in this application provides the following effects: 1! ).

(1) A data line load element that is turned on at the selection level of the data line selection signal is provided on each data line, and by turning on the data line load element according to the selection level of the data line selection signal, the unselected data line Through current flowing through the side memory cells can be reduced, and power consumption can be significantly reduced.

(2) Due to the above effects, low consumption! & Memory cells can be freely laid out without being restricted to the divided configuration of memory cell arrays that is done for power generation.

(3) In particular, if the data line load element is composed of a high resistance first data line load element and a low resistance second data line load element which are switch-controlled in a complementary manner based on the data line selection signal, the above effects can be achieved. In addition, high-speed reading of data can also be achieved.

Although the invention made by the present inventor has been specifically explained based on examples, various changes can be made without departing from the gist thereof.

In the above embodiment, a case has been described in which the data line load element is composed of a first data line load element with high resistance and a second data line load element with low resistance, which are switch-controlled in a complementary manner based on a data line selection signal. However, if the bias voltage during non-selection is replaced by a discharge voltage from a memory cell, the first data line load element can be omitted. The high resistance first data line load element is a MOSFET.
For example, an element made of high-resistance polysilicon formed on a semiconductor substrate via an insulating film, or an element made of a polysilicon high-resistance element and polysilicon connected in series, rather than an element capable of switch operation such as an ET. PN of direction movement
It may also be constructed from a series circuit with a junction element.

Further, the equalizer MOSFET described in the above embodiment may be switch-controlled by an internal control signal generated by detecting a change in the address signal, or may be omitted.

[Application field]

In the above explanation, the invention made by the present inventor was mainly explained in terms of its application to MOS static RAM, which is the technical field behind the invention, but it is not limited to this, and can be applied to various semiconductor storage devices. Can be widely used.

[Brief explanation of drawings]

FIG. 1 shows a static RA which is a first embodiment of the present invention.
It is a circuit diagram showing M. W1 to Wn...word line, Di, Di...data line. Dn, Dn...data line, CD, CD...common data line, Q5-Q8...data line selection element, Q9...
Data line load element (high resistance first data line load MO8FE
T), QIO... data line load element (low resistance second data line load MO3FET), Ql 1... level shift element (level shift MOS FET), Ql 2...
・Equalizer MO8FET, 1...Memory array, 1
a to 1d: static memory cells.

Claims (1)

[Claims] 1. In a semiconductor memory device in which memory cells coupled to a word line and a data line are selected based on a word line selection signal and a data line selection signal, a relatively low resistance 1. A semiconductor memory device comprising a data line load element provided on each data line. 2. The data line load element includes a first data line load element of relatively low resistance that is operated when the data line is selected and a second data line load element of relatively high resistance that is operated when the data line is not selected. A semiconductor memory device according to claim 1, characterized in that: 3. The semiconductor memory device according to claim 2, wherein the first data line load element and the second data line load element are composed of MOSFETs of different conductivity types. 4. The semiconductor memory device according to claim 3, wherein the first and second data line load elements are switch-controlled by a data line selection signal. 5. The semiconductor memory according to any one of claims 2 to 4, wherein the second data line load element is connected to the power supply terminal via a level shift element. Device.