JPS63102473A - Image signal processing device - Google Patents
Image signal processing deviceInfo
- Publication number
- JPS63102473A JPS63102473A JP61247755A JP24775586A JPS63102473A JP S63102473 A JPS63102473 A JP S63102473A JP 61247755 A JP61247755 A JP 61247755A JP 24775586 A JP24775586 A JP 24775586A JP S63102473 A JPS63102473 A JP S63102473A
- Authority
- JP
- Japan
- Prior art keywords
- error
- pixel
- distribution
- interest
- binarization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2059—Display of intermediate tones using error diffusion
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- Character Input (AREA)
- Image Processing (AREA)
- Facsimile Image Signal Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、階調画像を含む画像情報を2値再生する機能
を備えた画像信号処理装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal processing device having a function of performing binary reproduction of image information including gradation images.
従来の技術
近年事務処理の機械化や画像通信の急速な普及に伴って
、従来の白黒2値原稿の他に、階調画像や印刷画像の高
品質での画像再現に対する要望が高まって来ている。特
に、階調画像の2値画像による擬似階調再現は、表示装
置や記録装置との適合性が良く、多くの提案がなされて
いる。Conventional technology In recent years, with the mechanization of office processing and the rapid spread of image communications, there has been an increasing demand for high-quality image reproduction of gradation images and printed images, in addition to conventional black-and-white binary originals. . In particular, pseudo gradation reproduction using a binary image of a gradation image is highly compatible with display devices and recording devices, and many proposals have been made.
これらの擬似階調再現の1つの手段として、ディザ法が
最もよく知られている。この方法は、予め定められた一
定面積において、その面積内に再現するドツトの数によ
って階調を再現しようとするもので、ディザマトリクス
に用意した閾値と入力価情報を1画素毎に比較しなから
2値化処理を行っている。この方法は階調特性と分解能
特性がディザマトリクスの大きさに直接依存し、互いに
両立できない関係にある。また印刷画像などに用いた場
合、再現画像におけるモアレ模様の発生は避けがたい。The dither method is the most well-known method for reproducing these pseudo gradations. This method attempts to reproduce gradations in a predetermined area by the number of dots reproduced within that area, and the threshold value prepared in the dither matrix and input value information are compared for each pixel. Binarization processing is performed from In this method, the gradation characteristics and resolution characteristics directly depend on the size of the dither matrix, and are incompatible with each other. Furthermore, when used for printed images, it is difficult to avoid the occurrence of moiré patterns in the reproduced image.
上記階調特性と高分解能が両立し、かつモアレ模様の発
生抑制効果の大きい方法として、誤差拡75DIGES
T、 pp36−37)が提案されている。As a method that achieves both the above gradation characteristics and high resolution, and has a large effect of suppressing the occurrence of moiré patterns, the error expansion 75 DIGES
T, pp36-37) has been proposed.
第3図は上記誤差拡散法を実現するための装置の要部ブ
ロック図である。原画像における注目画素の座標を(x
、 y)とするとき、1は誤差記憶手段、2は誤差配
分係数マトリクスの示す注目画素の周辺の未処理画素領
域、3は座標(x、 y)における集積誤差Sxyの
記憶位置、4は座標(x。FIG. 3 is a block diagram of essential parts of an apparatus for realizing the above error diffusion method. The coordinates of the pixel of interest in the original image are (x
, y), 1 is the error storage means, 2 is the unprocessed pixel area around the pixel of interest indicated by the error distribution coefficient matrix, 3 is the storage position of the integrated error Sxy at the coordinates (x, y), and 4 is the coordinates (x.
y)における入力レベルIxyの入力端子、5はI’x
y (= I xy + 5xy)の入力補正手段、6
は出力レベルOまたはRの2値信号Pxyの出力端子、
7は一定閾値R/2を印加する信号端子、8は入力信号
I’xy > R/ 2の時Pxy=Rを、その他の場
合はPxy=Oを出力する2値化手段、9はExy(=
I’xy −Pxy )の注目画素に対する2値化誤差
を求める差分演算手段である。y), the input terminal of the input level Ixy, 5 is I'x
y (= I xy + 5xy) input correction means, 6
is the output terminal of the binary signal Pxy of output level O or R,
7 is a signal terminal that applies a constant threshold value R/2, 8 is a binarization means that outputs Pxy=R when input signal I'xy > R/2, and Pxy=O in other cases; 9 is Exy ( =
This is a difference calculation means for calculating the binarization error for the pixel of interest (I'xy - Pxy).
さて、注目画素に対する集積誤差Sxyは第(1)、(
2)式で表わされる。Now, the integration error Sxy for the pixel of interest is the (1)th, (
2) It is expressed by the formula.
8xy=ΣコKij ・Ex−j+2. y−i+
1 −− (1)(但し、’+ Jは誤差配
分係数マトリクス内の座標を示す。)
この誤差配分係数K i jは誤差Exyの注目画素の
周辺画素への配分の重み付けをするもので前記文献では
(但し、*は注目画素の位置)
を例示している。8xy=ΣKij・Ex−j+2. y-i+
1 -- (1) (However, '+J indicates the coordinate in the error distribution coefficient matrix.) This error distribution coefficient K i j weights the distribution of the error Exy to the surrounding pixels of the pixel of interest, and is as described above. In the literature, (where * is the position of the pixel of interest) is given as an example.
第3図の構成では、上記の演算は注目画素に対する2値
化誤差Exyに、未処理の周辺画素領域2内の各画素A
−Dに対応する配分係数を乗算し、誤差記憶手段1内の
値に加算し再び該当位置へ記憶させる誤差配分演算手段
10によって実現している。ただし、誤差記憶手段1の
画素位置Bの集積誤差は予め0にクリアされている。In the configuration shown in FIG. 3, the above calculation adds the binarization error Exy to the pixel of interest to each pixel A in the unprocessed surrounding pixel area 2.
This is realized by the error distribution calculation means 10 which multiplies -D by the corresponding distribution coefficient, adds it to the value in the error storage means 1, and stores it again at the corresponding position. However, the integrated error at pixel position B in the error storage means 1 is cleared to 0 in advance.
発明が解決しようとしている問題点
さて上記の誤差拡散法は、ディザ法に比して階調特性や
分解能の点ですぐれた性能を持ち、印刷画像の再現時に
おいてもモアレ模様の出現は極めて少ない。しかし、濃
度変化の少ない画像や計算機で生成された均一な濃度の
画像などでは方式特有の模様(テクスチャ)を作るため
、はとんど普及していない。このテクスチャの発生の主
たる原因は、注目画素の周辺画素に対する2値化誤差の
配分の割合が注目画素と常に一定の相対的位置関係に保
持されているためである。Problems to be Solved by the Invention The error diffusion method described above has superior performance in terms of gradation characteristics and resolution compared to the dither method, and the appearance of moiré patterns is extremely rare even when reproducing printed images. . However, this method is not widely used because it creates a pattern (texture) that is unique to the method in images with little density change or images with uniform density generated by a computer. The main reason for the occurrence of this texture is that the ratio of binarization error distribution to surrounding pixels of the pixel of interest is always maintained in a constant relative positional relationship with the pixel of interest.
本発明は上記の誤差拡散法におけるテクスチャの発生を
抑制し、階調特性・分解能にすぐれ、かつ印刷画像の再
生時にもモアレ模様の発生の極めて少ない画像信号処理
装置を提供するものである。The present invention provides an image signal processing device that suppresses the occurrence of texture in the error diffusion method described above, has excellent gradation characteristics and resolution, and has extremely low occurrence of moiré patterns even when reproducing printed images.
問題点を解決するための手段
本発明は、画素単位でサンプリングした多階調の濃度レ
ベルを2値化する際に、注目画素の2値化誤差をその周
辺の画素位置に対応させて記憶する誤差記憶手段と、注
目画素の入力レベルと前記誤差記憶手段内の注目画素位
置に対応した集積誤差を加算し補正レベルを出力する入
力補正手段と、前記補正レベルを予め定められた閾値と
比較し注目画素の2値化レベルを決定する2値化手段と
、前記補正レベルと2値化レベルの差分(2値化誤差)
を求める差分演算手段と、前記2値化誤差を注目画素の
周辺の未処理画素に配分する配分係数を、予め定められ
た変更周期で、1組の配分係数セットの対応する画素位
置を無作意に変更しながら発生させる配分係数発生手段
と、前記差分演算手段からの差分と前記配分係数発生手
段からの複数の配分係数から注目画素周辺の未処理画素
に対応する誤差配分値を算出し、前記誤差配分値を前記
誤差記憶手段内の対応する画素位置の集積誤差とを加算
し新たな集積誤差として再び記憶させる誤差配分・更新
手段とを設けることにより、上記目的を達成しようとす
るものである。Means for Solving the Problems The present invention stores the binarization error of a pixel of interest in correspondence with its surrounding pixel positions when binarizing multi-gradation density levels sampled in pixel units. error storage means; input correction means for adding the input level of the pixel of interest and the accumulated error corresponding to the position of the pixel of interest in the error storage means and outputting a correction level; and comparing the correction level with a predetermined threshold. A binarization means that determines the binarization level of the pixel of interest, and a difference between the correction level and the binarization level (binarization error).
and a distribution coefficient for distributing the binarization error to unprocessed pixels surrounding the pixel of interest, at a predetermined change period, randomly changing the corresponding pixel position of one set of distribution coefficients. calculating an error allocation value corresponding to an unprocessed pixel around the pixel of interest from a distribution coefficient generation means that generates the distribution coefficient while changing it at will, a difference from the difference calculation means and a plurality of distribution coefficients from the distribution coefficient generation means; The above object is achieved by providing error distribution/updating means for adding the error distribution value to the accumulated error at the corresponding pixel position in the error storage means and storing the result again as a new accumulated error. be.
作用
本発明は上記構成により、注目画素の周辺画素に対する
2値化誤差の配分割合を、1組の配分係数セントの注目
画素との相対的画素位置を画素の処理とともに無作意に
変更する前記配分係数発生手段によって、2値化誤差の
配分量が注目画素と一定の相対的位置関係に偏らないよ
うにし、処理された出力画像にテクスチャ模様が発生し
ないようにしだものである。According to the above configuration, the present invention randomly changes the distribution ratio of the binarization error to the surrounding pixels of the pixel of interest by randomly changing the pixel position relative to the pixel of interest of a set of distribution coefficient cents along with pixel processing. The distribution coefficient generating means prevents the distribution amount of the binarization error from being biased toward a fixed relative positional relationship with the pixel of interest, and prevents texture patterns from occurring in the processed output image.
実施例
第1図は本発明の一実施例における画像信号処理装置の
ブロック結線図である。Embodiment FIG. 1 is a block diagram of an image signal processing apparatus in an embodiment of the present invention.
第1図において、1〜9の各ブロックの構成と作用は第
3図の従来のものと同様である。第3図の構成と異なる
点は、第3図で示した誤差配分演算手段10のかわりに
、誤差配分・更新手段11と配分係数発生手段12を設
けた点で、以下この点について詳細に述べる。In FIG. 1, the structure and operation of each block 1 to 9 are the same as the conventional one shown in FIG. The difference from the configuration in FIG. 3 is that error distribution/updating means 11 and distribution coefficient generation means 12 are provided in place of the error distribution calculation means 10 shown in FIG. 3, and this point will be described in detail below. .
まず配分係数発生手段12は、注目画素周辺の未処理画
素に対する1組の配分係数セントを予め用意し、同期信
号入力端子13よりX方向ないしY方向の画素処理周期
に同期した同期信号14を得て周辺画素領域2内の画素
位置A、Dに対する2値化誤差Exyの配分係数に^〜
KDを前記1組の配分係数セットより無作意に選択し誤
差配分・更新手段11へ出力する。誤差配分・更新手段
11は同期信号14に同期しながら、前記配分係数KA
−Koと共に、差分演算手段9からの注目画素に対す
る2値化誤差Exyおよび誤差記憶手段1の周辺画素領
域位置A、0.Dに対応する記憶装置に記憶されている
それ以前の画素処理課程における集積誤差S’A、S6
、S6を読み出し、新たな集積誤差5A−8Dを下記筒
(3)式により求める。First, the distribution coefficient generating means 12 prepares in advance a set of distribution coefficients for unprocessed pixels around the pixel of interest, and obtains a synchronization signal 14 synchronized with the pixel processing cycle in the X direction or Y direction from the synchronization signal input terminal 13. The distribution coefficient of the binarization error Exy for pixel positions A and D in the peripheral pixel area 2 is
KD is randomly selected from the one set of distribution coefficients and outputted to the error distribution/updating means 11. The error distribution/updating means 11 updates the distribution coefficient KA in synchronization with the synchronization signal 14.
-Ko, the binarization error Exy for the pixel of interest from the difference calculation means 9 and the surrounding pixel area position A of the error storage means 1, 0. Integration error S'A, S6 in the previous pixel processing process stored in the storage device corresponding to D
, S6 are read out, and a new integration error 5A-8D is determined using the following equation (3).
さらに誤差配分・更新手段11は新たな集積誤差5A−
8Dを誤差記憶手段1内の画素位置A−Dに対応する記
憶装置に書き込む更新処理を行なう。Furthermore, the error distribution/updating means 11 generates a new accumulated error 5A-
An update process is performed to write 8D into the storage device corresponding to the pixel position A-D in the error storage means 1.
以下、誤差配分・更新手段11と配分係数発生手段12
のさらに具体的構成を第2図に示す。第2図において、
配分係数発生手段12は1組の配分係数セットに1〜に
4を予め格納するために記憶装置15を設け、前記係数
セットを画素処理の開始に先だって収納する。またラン
ダム信号発生器16は同期信号入力端子13から与えら
れるX方向ないしはY方向の画素処理周期に対応した同
期信号14の入力により、セレクト信号17を出力する
。このランダム信号発生器16はマキシマムレングス・
カウンタ回路等の複数のビット信号を用いれば容易に構
成でき、広規則性の高いセレクト信号が得られる。セレ
クタ18は4人力4出力構成でセレクト信号17をセレ
クト信号として用い、前記記憶装置15内に格納されて
いる配分係数に、〜に4をKA −KDに無作意に選択
し接続する。すなわち配分係数に1〜に4と誤差記憶手
段1の周辺画素領域2内の画素位置A〜Dに対応した配
分係数に八〜Koの接続の仕方は16通り存在し、これ
らを選択するためにセレクト信号17は4ビツト構成を
採用している。誤差配分・更新手段11は同期信号14
に同期しながら、配分係数発生手段12から入力された
配分係数に^〜に+>と差分演算手段9から入力された
2値化誤差Exyを乗算し誤差配分値19〜22を生成
する。誤差配分値19と誤差記憶手段1より読込んだ画
素位置Aに対応する集積誤差S’Aを加算し次の画素処
理における集積誤差Sxyとして使用するため、内部レ
ジスタ23 (RA)に一時記憶する。画素位置Bに対
する集積誤差は注目画素3の処理において初めて生ずる
ため、誤差配分値20をそのまま画素位置Bに対応する
集積誤差(SB)として内部レジスタ24(RB)に一
時記憶する。誤差配分値20と前画素処理において一時
記憶している内部レジスタ24(RB)のデータを加算
し画素位置Cの集積誤差(Sc)として内部レジスタ2
5(R・)のデータと加算し画素位置りの集積誤差(S
o)として誤差記憶手段1の画素位置りに対応する記憶
装置に記憶させる。このような誤差配分・更新手段11
により、誤差記憶手段1内の記憶装置へのアクセスは、
画素位置Aに対応する読込みアクセスと画素位置りに対
応する書込みアクセスのみとなり容易に実現可能な構成
となる。Below, error allocation/update means 11 and allocation coefficient generation means 12
A more specific configuration is shown in FIG. In Figure 2,
The distribution coefficient generating means 12 is provided with a storage device 15 for previously storing 1 to 4 in one distribution coefficient set, and stores the coefficient set before starting pixel processing. Furthermore, the random signal generator 16 outputs a select signal 17 in response to input of a synchronization signal 14 corresponding to the pixel processing period in the X direction or Y direction, which is applied from the synchronization signal input terminal 13 . This random signal generator 16 has a maximum length
It can be easily constructed by using a plurality of bit signals such as a counter circuit, and a select signal with high generality can be obtained. The selector 18 has a four-manpower, four-output configuration, uses the select signal 17 as a select signal, and randomly selects and connects 4 to KA-KD from the distribution coefficients stored in the storage device 15. That is, there are 16 ways of connecting the distribution coefficients 1 to 4 and the distribution coefficients 8 to Ko corresponding to the pixel positions A to D in the peripheral pixel area 2 of the error storage means 1, and in order to select one of them, The select signal 17 has a 4-bit configuration. The error distribution/updating means 11 uses the synchronization signal 14
In synchronization with , the distribution coefficient inputted from the distribution coefficient generation means 12 is multiplied by +> and the binarization error Exy inputted from the difference calculation means 9 to generate error distribution values 19 to 22. The error distribution value 19 is added to the accumulated error S'A corresponding to the pixel position A read from the error storage means 1, and is temporarily stored in the internal register 23 (RA) for use as the accumulated error Sxy in the next pixel processing. . Since the accumulated error for pixel position B occurs for the first time in the processing of the pixel of interest 3, the error distribution value 20 is temporarily stored as it is in the internal register 24 (RB) as the accumulated error (SB) corresponding to pixel position B. The error distribution value 20 and the data in the internal register 24 (RB) temporarily stored in the previous pixel processing are added and the integrated error (Sc) at the pixel position C is stored in the internal register 2.
5 (R・) and the integration error (S
o) is stored in the storage device corresponding to the pixel position of the error storage means 1. Such error allocation/updating means 11
Accordingly, access to the storage device in the error storage means 1 is as follows.
There is only a read access corresponding to the pixel position A and a write access corresponding to the pixel position, resulting in an easily realized configuration.
発明の効果
以上のように本発明では、注目画素の周辺画素に対する
2値化誤差の配分比率を一定とせず、画素処理とともに
1組の配分係数セットから周辺画素位置に対応した複数
の配分係数を無作意に選択して利用することにより、従
来の誤差拡散法に見られた偽画像(テクスチャ)を大幅
に抑制することが可能となった。Effects of the Invention As described above, in the present invention, the allocation ratio of binarization error to surrounding pixels of a pixel of interest is not fixed, but multiple allocation coefficients corresponding to surrounding pixel positions are calculated from a set of allocation coefficients during pixel processing. By selecting and using them at random, it has become possible to significantly suppress the false images (textures) seen in conventional error diffusion methods.
第1図は本発明の一実施例における画像信号処理装置の
ブロック結線図、第2図は同装置の要部ブロック結線図
、第3図は従来の誤差拡散法を行なう画像信号処理装置
のブロック結線図である。
1・・・誤差記憶手段、11・・・誤差配分・更新手段
、15・・・記憶装置、16・・・ランダム信号発生器
、18・・・セレクタ、23〜25・・・内部レジスタ
。
代理人の氏名 弁理士 中 尾 敏 男ほか1名書 1
図
M 2 図
第 3 図Fig. 1 is a block diagram of an image signal processing device according to an embodiment of the present invention, Fig. 2 is a block diagram of main parts of the same device, and Fig. 3 is a block diagram of an image signal processing device that performs a conventional error diffusion method. It is a wiring diagram. DESCRIPTION OF SYMBOLS 1... Error storage means, 11... Error allocation/updating means, 15... Storage device, 16... Random signal generator, 18... Selector, 23-25... Internal register. Name of agent: Patent attorney Satoshi Nakao and 1 other person 1
Figure M2 Figure 3
Claims (1)
化する際に、注目画素の2値化誤差をその周辺の画素位
置に対応させて記憶するための誤差記憶手段と、注目画
素の入力レベルと前記誤差記憶手段内の注目画素位置に
対応した集積誤差を加算し補正レベルを出力する入力補
正手段と、前記補正レベルを予め定められた閾値と比較
し注目画素の2値化レベルを決定する2値化手段と、前
記補正レベルと2値化レベルの差分により2値化誤差を
求める差分演算手段と、前記2値化誤差を注目画素の周
辺の未処理画素に配分する配分係数を、予め定められた
変更周期で、1組の配分係数セットの対応する画素位置
を無作意に変更しながら発生させる配分係数発生手段と
、前記差分演算手段からの2値化誤差と前記配分係数発
生手段からの複数の配分係数から注目画素周辺の未処理
画素に対応する誤差配分値を算出し、前記誤差配分値を
前記誤差記憶手段内の対応する画素位置の集積誤差とを
加算し再び記憶させる誤差配分・更新手段とを具備する
画像信号処理装置。An error storage means for storing the binarization error of a pixel of interest in correspondence with the surrounding pixel positions when binarizing multi-gradation density levels sampled in pixel units, and an input level of the pixel of interest. input correction means for adding the accumulated error corresponding to the pixel position of interest in the error storage means and outputting a correction level; and comparing the correction level with a predetermined threshold to determine the binarization level of the pixel of interest. A binarization means, a difference calculation means for calculating a binarization error from the difference between the correction level and the binarization level, and a distribution coefficient for distributing the binarization error to unprocessed pixels surrounding the pixel of interest in advance. Distribution coefficient generation means that randomly changes corresponding pixel positions of one distribution coefficient set at a predetermined change period, and a binarization error from the difference calculation means and the distribution coefficient generation means. An error distribution value corresponding to unprocessed pixels around the pixel of interest is calculated from a plurality of distribution coefficients from the plurality of distribution coefficients, and the error distribution value is added to the accumulated error of the corresponding pixel position in the error storage means and stored again. An image signal processing device comprising distribution/updating means.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61247755A JPH0666873B2 (en) | 1986-10-17 | 1986-10-17 | Image signal processor |
| US07/110,082 US4890167A (en) | 1986-10-17 | 1987-10-16 | Apparatus for processing image signal |
| EP87309231A EP0264302B1 (en) | 1986-10-17 | 1987-10-19 | Apparatus for processing image signal |
| DE8787309231T DE3785290T2 (en) | 1986-10-17 | 1987-10-19 | IMAGE SIGNAL PROCESSING DEVICE. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61247755A JPH0666873B2 (en) | 1986-10-17 | 1986-10-17 | Image signal processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63102473A true JPS63102473A (en) | 1988-05-07 |
| JPH0666873B2 JPH0666873B2 (en) | 1994-08-24 |
Family
ID=17168179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61247755A Expired - Fee Related JPH0666873B2 (en) | 1986-10-17 | 1986-10-17 | Image signal processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0666873B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0257365A (en) * | 1988-08-24 | 1990-02-27 | Canon Inc | Image processing device |
| JPH03109871A (en) * | 1989-09-25 | 1991-05-09 | Canon Inc | Image processing device |
| JPH03112269A (en) * | 1989-09-27 | 1991-05-13 | Canon Inc | Image processing device |
| JPH03136467A (en) * | 1989-10-23 | 1991-06-11 | Canon Inc | Picture processor |
| WO2007036999A1 (en) * | 2005-09-28 | 2007-04-05 | Matsushita Electric Industrial Co., Ltd. | Circuit board connection structure, circuit board connection method, and press tool for circuit board connection |
-
1986
- 1986-10-17 JP JP61247755A patent/JPH0666873B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0257365A (en) * | 1988-08-24 | 1990-02-27 | Canon Inc | Image processing device |
| JPH03109871A (en) * | 1989-09-25 | 1991-05-09 | Canon Inc | Image processing device |
| JPH03112269A (en) * | 1989-09-27 | 1991-05-13 | Canon Inc | Image processing device |
| JPH03136467A (en) * | 1989-10-23 | 1991-06-11 | Canon Inc | Picture processor |
| WO2007036999A1 (en) * | 2005-09-28 | 2007-04-05 | Matsushita Electric Industrial Co., Ltd. | Circuit board connection structure, circuit board connection method, and press tool for circuit board connection |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0666873B2 (en) | 1994-08-24 |
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