JPS63113997A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the layout pitch of a word wire and to decrease the propagation time of a signal by constituting the word wire of a main word wire and a sub-word wire and connecting both word wires through an MIS transistor Tr. CONSTITUTION:For MISRAM, a word wire is constituted of a main word wire Woi and a sub-word wire Wi and Wi+1 and both word wires are connected through a MISTr at the near-end and far-end of the main word wire. In the constitution, when a metal wiring is used as the main word wire and a polycrystal Si wiring is used as the sub-word wire, the sub-word wire directly connected to the switch gate of a memory cell 1 can be also used as the gate electrode wiring. For the connection with the cell 1, the contact hole for the section of different wirings is unnecessary and the layout pitch of the sub-word wire can be made narrower. Further, concerning the main word wire, it is sufficient when one wiring is present at every two sub-word wires, and therefore, the wiring width wider than the sub-word wire is used. On the other hand, the signal delaying time of the word wire is speeded up compared with the case to use the word wire of the polycrystal Si wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory device, and particularly to a large capacity semiconductor integrated memory.

(Prior art and its problems) Among conventional semiconductor memory devices, an example of a random access memory (hereinafter referred to as RAM) using MIS transistors is shown in FIG.
Magazine, volume 130, June 1983, pages 127-135, “
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1a'), In the conventional MISRAM as shown in FIG. 3, when the voltage of the decoder output Xi selected by the , the voltage of the word line Wl rises from a low level to a high level. In general, the address signal applied to the RAM causes only one decoder output to go high and only one word line to be selected. At this time, the information of the memory cell 1 connected to the selected word line is read out to the digit line Bl connected to each memory cell. Further, on the other digit line Bi of the pair, an intermediate level of the potential that occurs when the high and low binary storage information of the memory cell is respectively read out to the digit line is generated by the reference potential generation circuit. As a result,
A slight potential difference determined by the capacitance division between the memory cell capacitance and the digit line capacitance is generated between the pair of digit lines Bi and BiO, and the signal is amplified by activating the sense amplifier 2. After that, the digit line signal is output through the input/output circuit selected by the Y decoder.
Reading of memory information ends. In writing, information is written to the selected digit line pair and memory cell through the input/output circuit.

In such a MISRAM, there are two cases in which a polycrystalline silicon gate electrode is used as the word line,
2 Cases in which a metal wiring is used as a word line and connected to a metal word line through a contact hole in the polycrystalline silicon gate electrode of a memory cell switch (MIS) transistor.
There are two ways.

The advantages and disadvantages of both methods are that when polycrystalline silicon wiring is used as the word line, the layout pitch of the word line can be narrowed, but on the other hand, the resistance per unit length of the word line is large, making it difficult to increase the memory capacity. Accordingly, when the wiring length of the word line becomes longer, the signal propagation time from the near end to the far end of the word line becomes longer, and high-speed read/write operations cannot be performed. On the other hand, when metal wiring is used as a word line, the wiring resistance is extremely low compared to polycrystalline silicon wiring, so high-speed operation is possible, but the contact between the metal wiring and the polycrystalline silicon gate electrode This has the disadvantage that the layout margin of the hole is too narrow) and the layout pitch of the word line can be narrowed. In addition, as a compromise between these two methods, a method is also used in which the word line is constructed by stacking two wires, a metal wire and a polycrystalline silicon wire, one above the other, and the two wires are connected through contact holes at a certain interval (
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This method reduces the delay time at the far end of the word line, but as memory becomes more highly integrated and has a larger capacity, memory cells, MIS transistors, wiring, etc. reach the limit of miniaturization. As a result, the layout margin for the contact hole connecting the metal wiring and the polycrystalline silicon wiring is large, and the word line layout pitch cannot be reduced.

As is clear from the above explanation, conventional word line drive circuits and wiring configurations have advantages and disadvantages between the word line layout pitch and signal propagation time. There is a strong need for a semiconductor memory device having the following characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that solves the above-mentioned problems in a highly integrated, large-capacity semiconductor memory, reduces the layout pitch of word lines, and has a high operating speed.

(Means for Solving the Problems) Means provided by the present invention to solve the above-mentioned problems includes memory cells arranged in a matrix, and a plurality of memory cells arranged in a matrix, and a plurality of switch gates of the memory cells connected in the column direction. a sub-word line, a main word line arranged parallel to the sub-word line for each of the plurality of sub-word lines, a plurality of digit line pairs connecting digit terminals of memory cells in the row direction, and a plurality of digit lines; A semiconductor memory device comprising at least a plurality of sense amplifiers each connected to a pair of lines, the main word line being connected to the plurality of corresponding sub-word lines at a plurality of locations via MIS transistors, respectively. It is.

(Function) The semiconductor memory device according to the present invention has, as word lines, a main word line consisting only of wiring and a sub-word line directly connected to the switch gate of the memory cell. The line and a plurality of sub-word lines are connected to each other at a plurality of the same locations via MIS transistors. Therefore, in order to read information from one memory cell, K first selects one main word line, and then selects one of a plurality of corresponding sub-word lines via a transistor (fMIs), and then Read memory cells in a column. As a result, the information of each memory cell is read out to the digit line connected to the cell, the read signal is amplified by the corresponding sense amplifier, and only one of these signals is selected and transmitted to the outside. .

In the semiconductor memory device of the present invention, for example, a memory wiring is used as a main word line, a polycrystalline silicon wiring is used as a sub-word line, and the polycrystalline silicon wiring of the sub-word line is also used as a gate electrode of a switch gate transistor of a memory cell. In particular, the layout pitch of the sub-word lines can be narrowed. On the other hand, regarding the signal delay time between the near end and the far end of the word line, one sub-word line is connected to the main word line of the metal wiring at multiple locations via M I S transistors. In addition, the signal delay time at both ends of the sub-word bladder can be made approximately equal to that in the case of metal wiring. Moreover, since the main word line is arranged as one wiring for each of the multiple sub-word lines, even if the wiring width of the main word line is widened, the layout pitch of the word lines does not increase, and only the sub-word lines It is possible to maintain a narrow layout pitch determined by As a result, the present invention can achieve both a reduction in word line layout pitch and a reduction in signal propagation time, which were problems in conventional semiconductor memories, and is suitable for large-capacity semiconductor integrated memories using long word lines. Very useful.

(Examples) Hereinafter, in order to facilitate understanding of the present invention, examples will be given and explained.

(Embodiment 1) FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In the MISRAM of this embodiment, the word line is composed of a main word line and a sub-word line, and the third word line is connected to the near end of the main word line and the far end thereof via an MIS transistor. It is almost the same as the conventional MISRAM shown in the figure, and the same circuit elements are given the same symbols and names.

In the MISRAM of this embodiment, when the voltage of the decoder output Xi selected by the goes from low level to high level.

At the same time, Xo and X are selected in advance by one bit of the X address. When one of the signals on the sub-word lines Wi and Wi+ is held at a high level voltage,
The voltage on one word line of t rises from a low level to a high level. For example, if the signal of It is read out to the connected digit line B1. In addition, the other digit line Bi of the pair has a height of 2
An intermediate level of the value read signal is generated by a reference potential generation circuit. As a result, a slight potential difference is generated between the digit line pair Bi and B1, and the signal is amplified by activating the sense amplifier 2. Thereafter, data is transferred to and from the outside using the Y decoder and input/output circuit, which are similar to the conventional example shown in FIG.

In this example, if a metal wiring is used as the main word line and a polycrystalline silicon wiring is used as the sub-word line, the sub-word line that connects directly to the switch gate of the memory cell can also be used as the gate electrode wiring, and This eliminates the need for contact holes between different wiring lines, allowing the layout pitch of sub-word lines to be narrowed. Further, as for the main word line, since one wiring is required for every two sub-word lines, a wide wiring width can be used for the sub-word lines as well. This is very convenient in practice, since metal wiring generally has poorer processing precision than polycrystalline silicon wiring and always has a wider wiring width.

Regarding the MIS transistors for connecting the main word line and sub-word line, one M
IS) transistors are required, but this is the same in the conventional example shown in FIG. It will be possible to make it narrower.

On the other hand, regarding the signal delay time of one word line, since both ends of the aU word line are connected to the main word line of metal wiring via MIS transistors, there is almost no difference in the signal delay time between both ends of the sub word line. . In this case,
Although the signal propagation time in the center of the sub-word line slows down as time passes, it is reduced to approximately % of the word line delay time when polycrystalline silicon wiring is used in the conventional example shown in Figure 3, making it practical. Moreover, word line signal propagation speed can be significantly increased.

In other words, in this embodiment, it is possible to reduce both the word line layout pitch and the signal propagation time.

(Embodiment 2) FIG. 2 is a circuit diagram showing a second embodiment of the present invention. In the MISRAM of this embodiment, the memory cell array is divided into two, and the connection between the main word line and the sub-word line via the MIS transistor is at the near end, center, and far end of the word line.
The configuration is the same as that of the first embodiment shown in FIG. 1, and the same circuit elements are given the same symbols and names. When a polycrystalline silicon wiring is used for the sub-word line, the metal wiring and the polycrystalline silicon wiring are connected to the signal X0 or X at three locations on the word line. Since the sub-word lines are connected by K, the signal propagation time is further shortened in all cases of the sub-word lines, as in the case of the first embodiment. Therefore, despite the fact that the sub-word line is surrounded by polycrystalline silicon wiring, approximately the same signal propagation speed as the metal wiring word line can be achieved.

Alternatively, in the case of this embodiment, it is possible to realize a memory in which the signal propagation speed of the word line does not become slow even in a MISRAM in which the word line is particularly long. Regarding the layout pitch of the word lines, since polycrystalline silicon wiring is used for the sub-word lines, the smallest pitch in the conventional example can be achieved, resulting in a MISRAM capable of high-speed operation despite the small cell size.

As described above, regarding the semiconductor memory device of the present invention, the main word line 1
In this book, we have described an example of a configuration in which the main word line and the sub-word line are connected via MIS transistors at two and three locations of the word line, respectively, when there are two sub-word lines. However, the present invention is not limited to this configuration, and may include a configuration in which one main word line has three or more sub-word lines, or a main word line and a sub-word line are each connected to M I at four or more locations on the word line. Also, in this embodiment, the MIS transistor that connects the main word line and the sub-word line has been described using an N-channel MIS transistor. It can be a P-channel or any other MIS) transistor. Furthermore, the wiring materials for the main word line and sub-word line are not limited to metal wiring for the main word line and polycrystalline silicon wiring for the sub-word line, and the present invention applies to any combination of wiring materials. Needless to say, it can be applied.

(Effects of the Invention) As described above, according to the present invention, it is possible to achieve both a reduction in the layout pitch of word lines and a reduction in signal propagation time, which have been difficult in the past, and a large-capacity semiconductor integrated memory. This is effective for large capacity and high speed.

[Brief explanation of the drawing]

1 and 2 are MISRAM circuit diagrams showing the first and second embodiments of the present invention, respectively, and FIG. 3 is a conventional MISRAM circuit diagram.
1 is a circuit diagram for explaining an SRAM; FIG. In the symbols in the figure, Xl, Xl+ represent the X decoder output,
RA is the word line activation signal, 1 is the memory cell, 2 is the sense amplifier, Woi is the main word line, Wl, Wi+
t is the sub word line, Bi, Bi is the digit line, Xo
, Xo indicate sub-word line selection signals, respectively. Agent Patent Attorney Shinsuke Honsho λ Engineering η Day 7

Claims (1)

[Claims] Memory cells arranged in a matrix, a plurality of sub-word lines connecting the switch gates of the memory cells in the column direction, and a main word line arranged parallel to the sub-word lines for each of the plurality of sub-word lines. , comprising at least a plurality of digit line pairs connecting digit terminals of memory cells in the row direction, and a plurality of sense amplifiers respectively connected to the plurality of digit line pairs, and the main word line connects the corresponding plurality of main word lines at a plurality of locations. What is claimed is: 1. A semiconductor memory device, wherein the semiconductor memory device is connected to each of the sub word lines of the sub-word lines via MIS transistors.