JPS6311706B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microcomputer whose number of input/output ports (I/O ports) can be easily expanded and used.

In a 1-chip microcomputer (hereinafter referred to as 1-chip microcomputer), at least a CPU,
Contains instruction ROM, data RAM, and I/O ports. It also combines the instructions of one chip microcontroller
There is an evaluator chip that includes all functional elements except ROM and has an external instruction ROM, but here we will refer to it as a 1-chip microcontroller.

In general, even a single-chip microcontroller with the same structure has ROM.
There are several types available depending on the amount of memory, RAM capacity, and number of I/O ports. In this case, the number of I/O ports is usually fixed depending on the product type. This poses no practical inconvenience when selecting a product type depending on the application and using it as a dedicated microcomputer. However, when it is desired to use the same product for multiple purposes, especially for increasing the level of use, it would be convenient if the number of I/O ports could be increased or decreased.

For example, in the first example, a level 1 product has 3I/
Suppose that there is an application in which an O port is used, a level 2 product uses 5 I/O ports, and a level 3 product uses 12 I/O ports. If all ROM contents are the same, select a type that can be used for all levels 1 to 3. In this case, however, when used for level 1 and level 2, there are surplus I/O ports. Therefore, a type of 1-chip microcomputer (master side) that is compatible with the minimum system equivalent to level 1 is selected. And level 2,
The above problem can be solved by providing an I/O expansion chip (slave side) for level 3 applications and expanding and increasing only the I/O ports.

As a second example, in the case of a chip for evaluation, since the instruction ROM must be externally attached, the number of program counter output terminals and instruction code input terminals is increased compared to a chip with a built-in instruction ROM. For this reason, if the number of I/O ports increases, the number of pins on the package becomes insufficient, so the chip may be divided into two parts. In addition, if the number of units produced is small, an evaluation chip and an external ROM may be used to incorporate the device into the device. At this time, I/O ports may be incorporated and implemented for variation of a product that requires only a small number of I/O ports. Therefore, I installed a few I/O ports, a CPU section, and a single RAM chip for the evasion (master side).
The remaining I/O ports are stored in an I/O expansion chip (hereinafter referred to as slave side). Above are two examples of I/O from one chip microcontroller.
The advantages of dividing a part of the port were described.

However, when it is divided into two chips, signals are required to interconnect each chip.
It is also necessary to add a control signal terminal for the I/O expansion chip to the one-chip microcomputer side (hereinafter referred to as the master side) that includes the ROM, RAM, CPU section, and part of the I/O port. However, when used only on the master side, the control signal terminals of the I/O expansion chip are not used, so the number of unnecessary terminals increases.

The present invention eliminates the above-mentioned drawbacks of the conventional technology and uses I/O ports to input and output control signals for the I/O expansion chip, thereby reducing unnecessary ports as much as possible when only the master chip is used. The purpose is to

Another object of the present invention is to simplify I/O implementation of a support tool during expansion or when developing a series of microcomputers.

A detailed explanation will be given below based on one embodiment of the present invention.

FIG. 1 is a block diagram when a 1-chip microcomputer is used solely on the master side. In the figure, power supply, clock, interrupt, shift buffer,
The explanation of the timer and reset portion is well known and is not directly related to the present invention, so the explanation will be omitted.

The expansion switching terminal 2 of the 1-chip microcomputer 1 on the master side is left open. This terminal 2 is pulled up to the power supply level by a pull-up resistor in the chip and kept at a HIGH level.

Dedicated input/output ports 3 to 5 are ports for inputting and outputting I/O port signals. The composite input/output port 6 inputs/outputs either an input/output data port signal or a timing signal. The composite input/output port 7 inputs/outputs either an input/output port signal or a data signal. The composite input/output port 8 inputs/outputs either an input/output port signal or a control signal.

When the expansion switching terminal 2 is at HIGH level, it is switched to input and output port signals.

FIG. 2 is a block diagram when an I/O expansion chip (hereinafter referred to as slave side) 18 is added to the master side 1 of a one-chip microcomputer. At this time, the expansion switching terminal 2 of the microcomputer 1 on the master side is
Set to LOW level. Dedicated input/output port 3~
5 inputs and outputs I/O port signals.

Composite input/output ports 6 to 8 have expansion switching terminal 2.
Since it is at LOW level, it inputs and outputs extended control signals consisting of timing signals, data buses, and control signals.

At this time, the I/O ports 6 to 8 of the microcomputer 1 on the master side have no input/output ports because they input and output extended control signals, so the I/O ports 18 on the slave side
It is input and output from I/O ports 9, 10, and 11 of. Further, the expanded I/O ports 12 to 17 are also newly input/output from the slave side 18.

Next, the internal structure and operation of the chip will be described based on the block diagrams of FIGS. 3 and 4. First, in FIG. 3, we will discuss the case where a 1-chip microcomputer is used only on the master side. First, the expansion switching terminal 2 is pulled up and becomes HIGH level. Multiplexers 23 to 25 that operate as switching circuits at this time
is selected to input/output the I/O port signal side.

When an output command is executed, data on the data bus 30 is latched into the I/O registers 20-22.
The latch outputs of I/O registers 20-22 are output to composite input/output ports 6-8 via multiplexers 23-25.

When an input command is executed, the data of composite input/output ports 6 to 8 is transferred to multiplexers 23 to 2 as switching circuits.
5 to the data bus 30.

In this way, composite input/output ports 6 to 8 have I/O ports.
O port signals are input and output.

Next, a case will be described in which the master side shown in FIG. 3 and the slave side shown in FIG. 4 are connected to expand and use the I/O ports. First, set expansion switching terminal 2 to LOW level. At this time, multiplexers 20 to 22 operating as switching circuits select the timing signal side, the data bus signal side, and the control signal side, respectively.

Therefore, extended control signals consisting of timing signals, data bus signals for inputting and outputting to the I/O ports, and control signals are inputted and outputted from the composite input/output ports 6 to 8. In addition, the master side and slave side are mutually combined and combined input/output ports 6-6a, 7
-7a and 8-8a are connected. In the I/O control circuit 43, the control signal input from the composite input/output port 8a is combined with the timing signal input from the combined input/output port 6a.
AND gated. A gated control signal is output to the I/O control signal line 54 at the timing required for each input/output command. When an output command is executed, the data sent from the combined input/output port 7a to the data bus is transferred to the registers 44 to 5.
2 and the corresponding ports 9-17
Output to.

When an input command is executed, data is input from ports 9 to 17, output to the data bus 53, and sent to the master side from the combined input/output port 7a.

Next, FIGS. 5 and 6 show concrete circuits of FIGS. 3 and 4. 201-2 in Figure 5
12 is a D flip-flop, 215 is an output command signal line, 216 is an expansion switching signal line, 217 is an input command signal line, 218 is an output command signal line, 219 is a data bus and input/output switching signal line, and 220 is an input command signal line. , 221 is an output command signal line, 222 is an input command signal line, 224-255, 293-30
4 is a transistor, 256 to 279 are output driver transistors, 280 to 291 are input/output terminals, 292 is an OR gate, and 306 is a switching circuit.

In FIG. 6, 401 to 412 are connection terminals with the master side, 413 is a port address decoder, 414 is a port address latch D flip-flop, 415 is an I/O control encoder decoder, and 418 to 422 are I/Os on the slave side. O port terminals, 423-427 are AND gates, 428-432 are I/O port D flip-flops, 433-437 are pull-up transistors, 438-442 are I/O driver transistors, 443-452 are transfer gates.
The transistor 453 is a port address signal line.

Next, the operation will be explained. First, the case where it is used only on the master side will be described based on FIGS. 5A to 5C.

When the expansion switching terminal 2 is opened, the expansion switching signal line 216 becomes HIGH level.
Transistors 224 to 224 forming the switching circuit 306
235 is turned off, transistors 293-3
04 is in the ON state. As a result, the switching circuit 306 in FIG. flip-flop 205, 206, 20
7,208 output to transistors 265, 26
7, 269, 271, and in FIG. When an output command is executed, the data to be output to the input/output terminal is placed on the data bus 30, and a trigger pulse is sent to one of the output command signal lines 215, 218, and 221, which are independent for each port address, and corresponds to the output address. is output. When outputting to the input/output terminals 280, 281, 282, 283, the output latch flip-flops 201, 202, 203, 204 operate in synchronization with the trigger pulse from the output command signal line 215, and the output command is sent to the corresponding port. Retain data until executed. In this way, when an output command is executed, the data bus 30 is latched to the output latch flip-flops 201 to 212, and the transistor 25 is latched.
The output drivers 6 to 279 are driven to output to input/output terminals 280 to 291. When executing an input command, the output driver enhancement transistors 257, 259, 261, 263, 265,
267, 269, 271, 273, 275, 27
7,279 is turned off. Then, terminal 280
~291 are output driver pull-up depletion transistors 256, 258, 260,
262, 264, 266, 268, 270, 27
2, 274, 276, and 278 with appropriate impedance and are pulled up to the power supply VDD.

When an input command is executed, a pulse is output to one of the input command signal lines 217, 220, and 222, which are independent for each port address, and corresponds to the input address. Input/output terminals 280, 281, 282, 28
When reading data from 3, input command signal line 2
17 pulses cause transistors 236, 23
7, 238, 239 become conductive, and terminal 28
The levels 0 to 283 are transmitted to the data bus 30. The data thus input to the input/output terminals 280 to 291 is input to the data bus 30.

Next, the case of expanding connection on the slave side will be described based on FIGS. 5A to 5C and FIGS. 6A and 6B.

First, the part shown in Figure 5 on the master side will be described. When the extension switching terminal 2 is set to LOW level, the extension switching signal line 216 becomes LOW level, so the switching circuit 306
Transistors 224 to 235 constituting the circuit are turned on, and transistors 293 to 304 are turned off.

In FIG. 5A, the switching circuit 306 receives the switching signal.
Since it is LOW level, transistors 293 and 29
4,295,296 are turned OFF and transistors 224, 225, 226, 227 are turned ON, thereby timing signals T1, T2, T3,
T4 is transistor 257, 259, 261, 2
63 gates.

Transistors 256, 258, 260, 262
has the same function as a pull-up resistor, and the transistors 257, 259, 261, 26
3 operates as an inverter, and the timing signal T
The inverted signals of 1, T2, T3, and T4 are connected to terminals 280,
281, 282, and 283.

Similarly, in the switching circuit 306 in FIG.
1 is turned on.

First, while the command to output data from the master side is being executed, the switching signal 219 is at LOW level, so the transistors 252, 253, 254, and 255 are turned off.
OFF, transistors 248, 249, 25
0 and 251 are turned on, data bus signals B1, B2, B4, and B8 are transferred to transistor 2.
It is applied to the gates of 65, 267, 269, and 271. Transistor 264, 266, 268, 2
70 functions equivalent to a pull-up resistor, and transistors 265, 267, 269, 2
71 operates as an inverter, and the inverted signals of the data bus signals B1, B2, B4, and B8 are sent to the terminal 28.
4,285,286,287.

Next, while executing the command to input data to the master side, the switching signal 219 is at HIGH level, so the transistors 248, 249, 250, and 251 are activated.
turned off, transistors 252, 253, 2
54, 255 are turned on, the LOW level becomes the transistors 265, 267, 269, 2.
71 gate.

Transistors 264, 266, 268, 270
has the same function as a pull-up resistor, and the transistors 265, 267, 269, 27
1 is in the OFF state, so terminals 284, 285, 2
Pins 86 and 287 are pulled up with high resistance and set to an input-enabled state.

Therefore, since the switching signal 219 of the terminals 284, 285, 286, and 287 is at HIGH level, the transistors 240, 241, 242, and 243 are turned on.
data buses B1, B2, B
4, transmitted to B8.

Similarly, in the switching circuit 306 in FIG.
5 is turned ON, the control signal C
1, C2, C4, C8 are transistors 273, 2
It is applied to the gates of 75, 277, and 279.

Transistors 272, 274, 276, 278
has the same function as a pull-up resistor, and the transistors 273, 275, 277, 27
9 operates as an inverter and receives timing signal C
The inverted signals of 1, C2, C4, and C8 are connected to terminals 288,
289, 290, and 291.

Therefore, the timing signals T1 to T4 on the timing signal line 31 and the data B1 to T4 on the data bus 30
B8 and the control signals C1 to C8 of the control signal line 32 are input/output drivers 256 to 279.
is driven and output to input/output terminals 280-291.

The connection between the master side and the slave side is through the input/output terminals 280 to 291 and the connection terminal 401 between the master side and the master side.
~412.

Next, the operation of the slave side shown in FIG. 6 will be described. Connection terminals with master side 409-412, 401-4
The control signal input from 04 and the timing signals T1 to T4 are converted into control signals by the I/O control decoder/encoder 415.
RD1, WT1, RD2, and WT2 are created.

The input/output command execution port address is the connection terminal 40
When the timing signal is input to the data bus 53
The address is latched into the port address latch 414 from then on. This latch output is the port address decoder 4.
13 and outputs the port address to the port address signal line 453. The address decoded by the port address decoder 413 is at least an I/O address that the master side can no longer use to connect the master side and slave side.
Contains the port address. Due to this,
To enable restoration of an I/O port lost by a master side due to expansion. Therefore, the program when used alone on the master side can be used as is for expansion, and it is possible to simplify the I/O implementation of the support tool when developing a series of microcomputers.

That is, the port address signal 453 is a signal obtained by decoding each port address in units of 4 bits, and is output from the port address decoder 413. Its output signal lines consist of 16 lines. In other words, the port address signal line 453
The port address signal corresponding to port address 0 is set to 453-0, the port address signal corresponding to port address 1 is set to 453-1, and the port address signal corresponding to port address 15 is set to 453-15 in the same manner. Of these, port address signal 453-9 is sent to gates 423 and 42.
4,425,426 and transistors 448,4
49, 450, and 451 gates.

Terminals 401, 402, 403, and 404 are each applied with four-phase clock pulses that do not overlap. These pulses have the same repetition period as the instruction execution machine cycle and are completely synchronized with the instruction execution cycle.

When executing an output command, first specify the port address for output, and then specify the output data. The port address is specified when the timing signal is applied to the terminal 401, and the output data is specified when the data bus signal is sent to the terminals 405 and 40 when the timing signal is applied to the terminal 404.
6,407,408.

Also, the fact that the output command is being executed is indicated by the terminal 40.
I/O via 9,410,411,412
By outputting to the control decoder encoder 415, a write command to each port is transmitted to the slave side.

To explain the operation of port addressing in more detail, when a timing signal is applied to terminal 401, data on data bus 53 is latched into port address latch 414. At this time, the output port address is encoded and placed on the data bus, and the port address latch 414
By inputting the output of 1 to the port address decoder 413, the decoder output signal 413-9 corresponding to the specified output port address becomes HIGH.
become the level. In this state, the gates 423, 424, 425, 426, 427 shown in FIG.
One of the AND conditions is satisfied, the program waits for a trigger pulse for writing, and this state is maintained for one machine cycle.

Next, the port output data designation operation will be explained in detail. A control signal is placed on the terminals 409, 410, 411, and 412 within the same machine cycle as the address specification, and a write command to the port is sent to the I/O control decoder encoder 415.
deciphered by.

As a result, the output command is decoded on the upper half decoding plane of the I/O control decoder encoder 415 in FIG. When the timing signal of the terminal 404 is applied, the decode output becomes active and the encode output WT1 signal becomes HIGH level.

At this time, terminals 405, 406, 407, 408
The output data is input to the data bus 53 via the WT1 signal and the decoder output 413-
Since both 9 signals are at HIGH level, the gate 423,,
424, 425, and 426 are opened, and output data is taken into output port latches 428, 429, 430, and 431.

Furthermore, the output port latch output drives transistors 438, 439, 440, and 441 and is output to terminals 418, 419, 420, and 421.

Similarly, when you execute an input command, first the terminal 40
During the period when the timing signal is applied to 1, the signal encoding the port address is sent to data bus 5.
3, and the port address latch 41
At the same time, only one output of the port address decoder 413 is set to HIGH level.

Next, during the period when the timing signal is applied to the terminal 403, a control signal encoded with a code instructing port input is sent to the terminals 409 to 411.
The RD1 signal output from the I/O control decoder/encoder 415 is set to HIGH level.

As a result, transistors 443, 444, 44
5,446 turns on, terminals 418, 419, 42
Port input data on ports 0 and 421 are input to data bus 416 via transistors 443, 444, 445, and 446.

I/O from data bus 53 when executing an output command
Data to be output to port D flip-flops 428-432 is latched. This latch output drives the output drivers 433 to 442 and outputs them to slave side I/O port terminals 418 to 421, 422, . . . .

When an input command is executed, data is input from the slave-side I/O port terminals 418 to 421, 422, .

In the above embodiment, the I/O port terminals are also used to input and output control signals for the I/O expansion chip. For this purpose, a switching circuit for selectively switching input/output of the I/O port signal and the expansion control signal,
An expansion switching terminal is provided on the master side. That is, by increasing the number of expansion switching terminals by one pin, the number of I/O ports can be further increased.

Furthermore, when the I/O port is not expanded, the expansion control signal terminal does not have to be left unused as a dedicated terminal on the master side, and the terminal can be used efficiently.

As is clear from the above embodiments, according to the present invention, when a minimum system is configured to be used only on the master side, the number of expansion control signal input/output terminals can be reduced. Further, even when I/O is expanded, if the slave side is prepared as a general-purpose chip, I/O expansion can be performed for all master side chips.

Furthermore, the program when used alone on the master side can be used as is for expansion, and it is possible to simplify I/O implementation of support tools when developing a series of microcomputers.

[Brief explanation of the drawing]

1 and 2 are block diagrams of a microcomputer according to an embodiment of the present invention, FIGS. 3 and 4 are diagrams showing detailed configurations of main parts, respectively, and FIG.
Figures I to C and Figures 6A and 6B are wiring diagrams showing more detailed configurations of essential parts. 1...Master side, 18...Slave side, 3~
5, 9-17...Input/output port, 6-8...Combined input/output port, 6a-8a...Combined input/output port, 23-25...Multiplexer, 2...Extension switching terminal, 306...Switching circuit , 453...Port address decoder.

Claims (1)

[Claims] 1. A dedicated input/output port that inputs and outputs input/output port signals, a first composite input/output port that inputs and outputs either the input/output port signal or the timing signal, or either the input/output port signal or the data signal. a second composite input/output port that inputs and outputs the signal;
a third composite input/output port that inputs and outputs either an input/output port signal or a control signal;
A switching circuit for selectively inputting and outputting either the input/output port signal or the timing signal, data signal, or control signal to the first, second, and third composite input/output ports, and this switching circuit. a master side having an expansion switching terminal for controlling circuit selection;
first, second, and third combined input/output ports coupled to the second and third combined input/output ports, a timing signal input from the first combined input/output port, and the second combined input/output port; by an expanded input/output port address signal including input/output port addresses respectively assigned to the first, second, and third composite input/output ports on the master side included in the data signal input from the port. an address decoder that decodes an input/output port address and sets the input/output port to an active level; a timing signal input from the first composite input/output port; and a control signal input from the third composite input/output port; an input/output control decoder/encoder that generates a write/read control signal; and a first one on the master side that operates when the address decoder outputs an active level.
It consists of a slave side with expanded input/output ports including three input/output ports in place of the second and third composite input/output ports, and can be used alone on the master side or by connecting the master side and slave side. A microcomputer that is characterized by the following: