JPS6312844U - - Google Patents

Info

Publication number
JPS6312844U
JPS6312844U JP1986106421U JP10642186U JPS6312844U JP S6312844 U JPS6312844 U JP S6312844U JP 1986106421 U JP1986106421 U JP 1986106421U JP 10642186 U JP10642186 U JP 10642186U JP S6312844 U JPS6312844 U JP S6312844U
Authority
JP
Japan
Prior art keywords
resin
sealed
semiconductor chip
lead frame
fixing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986106421U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986106421U priority Critical patent/JPS6312844U/ja
Publication of JPS6312844U publication Critical patent/JPS6312844U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/381—Auxiliary members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図はそれぞれ本考案の樹脂封
止半導体集積回路の断面図、第3図は従来の樹脂
封止半導体集積回路の断面図である。 1……銅板、2……半導体チツプ、3……アイ
ランド部、4……リードフレーム、5……ペース
ト、6……ハンダ、7……ボンデイングワイヤ、
8……樹脂。
1 and 2 are sectional views of a resin-sealed semiconductor integrated circuit according to the present invention, and FIG. 3 is a sectional view of a conventional resin-sealed semiconductor integrated circuit. DESCRIPTION OF SYMBOLS 1...Copper plate, 2...Semiconductor chip, 3...Island part, 4...Lead frame, 5...Paste, 6...Solder, 7...Bonding wire,
8...Resin.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 樹脂封止される半導体チツプと半導体チツプを
固定するリードフレームとの間に金属板を設けた
ことを特徴とする樹脂封止半導体装置。
A resin-sealed semiconductor device characterized in that a metal plate is provided between a semiconductor chip to be resin-sealed and a lead frame for fixing the semiconductor chip.
JP1986106421U 1986-07-11 1986-07-11 Pending JPS6312844U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986106421U JPS6312844U (en) 1986-07-11 1986-07-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986106421U JPS6312844U (en) 1986-07-11 1986-07-11

Publications (1)

Publication Number Publication Date
JPS6312844U true JPS6312844U (en) 1988-01-27

Family

ID=30981763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986106421U Pending JPS6312844U (en) 1986-07-11 1986-07-11

Country Status (1)

Country Link
JP (1) JPS6312844U (en)

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