JPS6313214B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program memory for a one-chip microprocessor, and more particularly to a word organization method for the program memory.

A one-chip microprocessor is a circuit element that integrates an arithmetic processing section such as a CPU with arithmetic processing functions (logic, arithmetic, etc.) and a program memory (generally masked ROM) in which the program is written on the same device. be. In such a microprocessor, the instruction code is usually created to match the bit length that can be processed in parallel by the arithmetic processing section, or has a bit length that is an integral multiple of that length. For example, on an integrated circuit with an 8-bit arithmetic function, there are 8
A bit parallel read ROM is provided as a program memory. The reasons for this are: (1) Data is often stored as immediate data in a program, and for this purpose it is convenient to store one word as a bit length or an integer multiple thereof. As is known, immediate data here refers to data 10 in an operation such as adding 10 to the data at address i in RAM, and this data 10 has already been determined at the time the program is created. Ori,
Of course, the data at address i above is variable, but data 10
is fixed and can be said to be a program itself in the form of data. (2) This one-chip microcontroller is often made compatible with so-called general-purpose microprocessors (having an external program memory), and for this purpose, the length of one word should be 8-bit data length or an integral multiple thereof. It's convenient. However, if the one-word length of the program memory, that is, the parallel read bit length, is adjusted to (an integral multiple of) the data length as described above, when handling immediate data, it is necessary to use two or more of the operation code and the immediate data (immediate If the data is n words, along with the operation (n+
1) an area (more than a word) is occupied in program memory.

Generally, as is known in program evaluations such as Gibson Mix, the rate of handling immediate data is quite high at 20-30%, especially when it is often applied to control systems such as one-chip microprocessors. There is a strong tendency to do so.

If the operation code is 8 bits, there are 256 types of instructions, but in a one-chip microcontroller there are 256 types of instructions.
Seed commands are often not necessary. Furthermore, the memory capacity of a one-chip microprocessor is limited to about 2K/byte, and generally a small capacity memory of about 1Kbyte is often used, so it is preferable that the program memory is used effectively.

The present invention attempts to deal with this problem by focusing on the fact that immediate value data is frequently used, and by treating this data differently, it aims to improve the efficiency of program memory use. The present invention provides a microprocessor in which at least an arithmetic processing unit and a program memory are formed on one chip, in which the length of one word of the program memory is equal to the bit length that can be processed in parallel by the arithmetic processing unit or a bit length that is an integral multiple thereof. plus a decimal additional bit, and at least the operation code or operation prefix of an instruction that operates on immediate value data has a shorter bit length than the operation code or operation prefix of other instructions. The other operation code, operation prefix, and immediate value data are stored in an area other than the additional bit, and the arithmetic processing unit stores the additional bit in the predetermined operation. If the additional bits indicate a predetermined operation prefix, perform the operation on the immediate data stored in the remaining bits of the word; The present invention is characterized in that immediate data manipulation commands configured together with operation codes are executed, which will be described in detail below with reference to the illustrated embodiments.

FIG. 1 is an explanatory diagram of a program memory showing an embodiment of the present invention. Reference numeral 10 denotes a storage area for operation codes and immediate value data, which consists of W words. The program memory of a conventional one-chip microcomputer consists of this storage area 10, and an operation code is written using one word of the memory area, and immediate data is written with an operation code such as "Load the next data to the accumulator" and its associated data. One word of data was used for each word, so a total of two words were written (or more if the number of words of the immediate data was large). Reference numeral 20 denotes an area for storing an additional bit added according to the present invention, 1 bit in this example. According to the present invention, this additional bit is added to constitute a 1-word storage area 30 of the program memory. The entire memory has a storage area for W words, and the bit configuration of the storage area 10 is adjusted to match the parallel processing capacity of an arithmetic processing unit (not shown).For example, if the arithmetic processing capacity is 8 bits, the storage area 10 can be configured as Since it is assumed to be an integer multiple of that value (in the following, it is assumed to be 8 bits to simplify the explanation), the conventional program memory is 8W bits, but in this example, the storage area 20 adds 1 bit, so
1 word storage area 30 is 9 bits, total
It becomes 9W bit. In addition to various operation codes 12, immediate value data 14 are written in the storage area 10, and "0" is written to the additional bit of the word in which the operation code is written, and "0" is written to the additional bit of the word in which the immediate value data is written. writes “1”.
Here, “0” means normal (same as before),
"1" means that the subsequent bit is immediate value data, which means that it is loaded into the accumulator. In this way, there is no need to write the operation code for the immediate data into the storage area of the storage area 10 at the address before the data, making it possible to save memory cells. Write "0" to the storage area 20 corresponding to the storage area 10 where the operation code 12 is written (this is the same as writing nothing), and write "0" to the storage area 20 corresponding to the storage area 10 where the operation code 12 is written. If it is, write the instruction bits and immediate value data to the storage area 10 using two or more words as in the past, write "0" to the additional bits of those words, and write "0" to the additional bits of those words. ``Then, the system is configured so that the storage area 10 is used in the same way as before, so there is no restriction on the type of operation code, and this can be expanded to allow all storage areas 20 to be used without any restrictions. If it is not written to, it can be used like a conventional program memory, thus making it compatible with general-purpose processors. however,
Since the storage area 20 in words that are normally used becomes wasted bits, the merits and demerits of adding additional bits are evaluated in relation to the frequency of appearance of immediate value data in the program.

That is, in a conventional 8-bit program memory, if there are L words of an immediate load instruction, the present invention saves 8×L=8L bits of program memory for this instruction, while the additional bits reduce the program memory capacity. If the capacity of the program memory is W words, the increase will be W bits, and therefore, if 8L>W, that is, L/W>1/8, the program memory capacity will be saved. This L/W is the appearance frequency of immediate value data in the program, and if this is 1/8 = 12.5% or more (as mentioned above, this is 30 to 40%, and if a one-chip microcontroller is used as the controller) (It is expected that the reduction rate will be as high as 50%) The method of the present invention has advantages over the conventional method.

It should be noted that what is judged by the additional bits does not necessarily have to be an instruction (sampling the presence or absence of an interrupt after execution), and an immediate operation instruction may be formed together with the next operation code as a prefix. Which of these should be selected depends on the register structure architecture of each microprocessor, and it is best to select the format that provides the largest number of L's. Also, the instructions (prefixes) using additional bits are not necessarily limited to those that load immediate value data, but as long as they operate on immediate value data, they may be stores of immediate values, multiplication of immediate values, etc. Also, the additional bit does not have to be 1 bit. do not have.

FIG. 2 shows another embodiment of the present invention in which the additional bits are 2 bits, and the storage area 20 has "00", "01",
It can have four storage states: "10" and "11". Of these, if "00" corresponds to "0" in the previous example, and "01" corresponds to "1" in the previous example, "10" is "ANDed with the contents of the accumulator and the immediate value data 16, and loaded into the accumulator again." In addition, "11" can be used as a set command to ``OR the contents of the accumulator and the immediate value data 18 and load it into the accumulator again.'' The maximum number of additional bits is determined by the above relationship of L/W>1/8, and is approximately 3 bits.

As described above, according to the present invention, it is expected that the small capacity program memory of a one-chip microprocessor can be used efficiently, and the present invention has the advantage of being compatible with general-purpose processors.

[Brief explanation of the drawing]

1 and 2 are explanatory diagrams of program memories showing different embodiments of the present invention. In the figure, 10 is an operation code and immediate value data storage area of the program memory, 20 is an additional bit storage area, and 30 is a storage area for one word.

Claims (1)

[Claims] 1. In a microprocessor in which at least an arithmetic processing section and a program memory are formed on one chip, one word length of the program memory is set to a bit length that can be processed in parallel by the arithmetic processing section or a bit length that is an integer multiple thereof. At least the operation code or operation prefix of an instruction that operates on immediate data has a shorter bit length than the operation code or operation prefix of other instructions. The operation code, operation prefix, and immediate value data are stored in the additional bit, and the other operation code, operation prefix, and immediate value data are stored in an area other than the additional bit, and the arithmetic processing unit stores the additional bit as a predetermined operation code. performs the operation on the immediate data stored in the remaining bits of the word if the additional bit indicates a predetermined operation prefix; A microprocessor characterized by executing instructions for manipulating immediate data configured together with code.