JPS63132995U - - Google Patents
Info
- Publication number
- JPS63132995U JPS63132995U JP1987025398U JP2539887U JPS63132995U JP S63132995 U JPS63132995 U JP S63132995U JP 1987025398 U JP1987025398 U JP 1987025398U JP 2539887 U JP2539887 U JP 2539887U JP S63132995 U JPS63132995 U JP S63132995U
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- emitting elements
- display device
- signal
- generation unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
第１図は本考案に係る表示器の１実施例を示す
側面図、第２図は表示器の各発光素子を点灯する
回路の構成例を示す図、第３図は点灯回路に供給
する信号の例を示すタイムチヤート、第４図は信
号発生ユニツトの構成例を示す図、第５図は電源
回路の構成例を示す図である。
１……キヤラクタ表示パネル、２……半透明パ
ネル、３……取り付け部、４……基板、５……発
光素子、６……配線面、７……信号発生ユニツト
。
Fig. 1 is a side view showing one embodiment of the display according to the present invention, Fig. 2 is a diagram showing an example of the configuration of a circuit for lighting each light emitting element of the display, and Fig. 3 is a signal supplied to the lighting circuit. FIG. 4 is a diagram showing an example of the configuration of the signal generating unit, and FIG. 5 is a diagram showing an example of the configuration of the power supply circuit. DESCRIPTION OF SYMBOLS 1...Character display panel, 2...Semi-transparent panel, 3...Mounting section, 4...Substrate, 5...Light emitting element, 6...Wiring surface, 7...Signal generation unit.
Claims (1)
基板、凹凸面を有し発光素子の取り付け面を覆う
ように配置される半透明パネル、発光素子を駆動
する複数の駆動信号を発生し該駆動信号をクロツ
クの計数により所定の順序でハイレベルからロー
レベルに切り換える信号発生ユニツトを備え、発
生素子を複数のグループに分割し該グループ毎に
信号発生ユニツトの各駆動信号により駆動して点
滅させることを特徴とする表示器。 (2) 複数の発光素子は、基板上に特定のキヤラ
クタに従つて配列されたことを特徴とする実用新
案登録請求の範囲第１項記載の表示器。 (3) 発光素子は、発光ダイオードであることを
特徴とする実用新案登録請求の範囲第１項記載の
表示器。 (4) 半透明パネルは、凹凸面を発光素子側に備
えた半透明パネルと特定のキヤラクタの透明部を
有するパネルとの組み合わせからなることを特徴
とする実用新案登録請求の範囲第１項記載の表示
器。 (5) 信号発生ユニツトは、クロツク発信器とリ
ングカウンタとバイナリカウンタと論理ゲート群
を備え、リングカウンタによりクロツクをカウン
トしてそのカウント出力により複数の信号出力を
順次ハイレベルからローレベルに切り換え、バイ
ナリカウンタによりリングカウンタの特定の出力
をカウントしてそのカウント出力により複数の信
号出力を同時にハイレベルに保持するように構成
したことを特徴とする実用新案登録請求の範囲第
１項記載の表示器。[Claims for Utility Model Registration] (1) A plurality of light emitting elements, a substrate on which the light emitting elements are attached, a translucent panel having an uneven surface and arranged to cover the mounting surface of the light emitting elements, and a plurality of light emitting elements for driving the light emitting elements. The device is equipped with a signal generation unit that generates a drive signal and switches the drive signal from a high level to a low level in a predetermined order by counting the clock, and divides the generation elements into a plurality of groups and performs each drive of the signal generation unit for each group. A display device that is driven by a signal and blinks. (2) The display device according to claim 1, wherein the plurality of light emitting elements are arranged on a substrate according to a specific character. (3) The display device according to claim 1, wherein the light emitting element is a light emitting diode. (4) Utility model registration claim 1, characterized in that the translucent panel is composed of a combination of a translucent panel with an uneven surface on the light emitting element side and a panel with a transparent portion of a specific character. indicator. (5) The signal generation unit includes a clock oscillator, a ring counter, a binary counter, and a group of logic gates, the ring counter counts the clock, and the count output sequentially switches multiple signal outputs from high level to low level. A display device according to claim 1, characterized in that the display device is configured to count a specific output of a ring counter using a binary counter and simultaneously maintain a plurality of signal outputs at a high level based on the count output. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987025398U JPS63132995U (en) | 1987-02-23 | 1987-02-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987025398U JPS63132995U (en) | 1987-02-23 | 1987-02-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63132995U true JPS63132995U (en) | 1988-08-31 |
Family
ID=30825516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987025398U Pending JPS63132995U (en) | 1987-02-23 | 1987-02-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63132995U (en) |
-
1987
- 1987-02-23 JP JP1987025398U patent/JPS63132995U/ja active Pending
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