JPS63140486A - Semiconductor device - Google Patents

Abstract

PURPOSE:To freely control a discharge current and to turn into a low transient current independent of production variance by forming a current mirror circuit with a pulse input voltage and making a current outputted from the mirror circuit constant. CONSTITUTION:The current mirror circuit is controlled by a kind of inverter consisting of transistors Q1 and Q2. When the transistors Q2 and Q1 are turned on and off, respectively, the current mirror circuit is formed between a transistor Q3, a constant current source i/n and an output drive transistor QD. On the contrary, when the transistors Q2 and Q1 are turned off and on, respectively, the transistor QD is turned off. Where a current source in the mirror circuit, the gate width of a MOST and the gate width of the transistor QD are i/n, w/n and W, respectively, the on current of the transistor QD turns out to be a constant current (i). Even if the (w), the gate length or the threshold voltage of the transistor varies due to the variance of a producing process, the drive current of the transistor QD becomes constant with the constant i/n given.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a circuit suitable for suppressing transient current or amplitude of pulse voltage.

[Conventional technology]

Conventionally, when charging and discharging a large load capacity at high speed, it was considered that the transient current would be excessive.8For example, in dynamic random access memory (hereinafter referred to as DRAM) using dynamic memory cells, , an excessive transient current occurs when charging and discharging a large number of data lines at once.
A voltage limiter circuit system as shown in Figure 1 has been proposed.

[Problem that the invention seeks to solve]

As a result, charging was left unchecked, with only a low current achieved by effectively lowering the power supply voltage.

Furthermore, the charging transient current, which changes in response to fluctuations in the transistor's load driving ability due to variations in the gate length or threshold voltage of MOS transistors due to manufacturing variations, is not actively controlled, so there is a limit to lowering the current. was there.

An object of the present invention is to provide a semiconductor device that charges and discharges a load capacitor at a predetermined arbitrary constant current and achieves low transient current independent of manufacturing variations. Another object of the present invention is to provide a semiconductor device with low transient current and low power consumption by combining the present invention with a voltage limiter circuit system.

[Measures to solve problems]

The above object is achieved by using a current mirror circuit controlled by input pulses as a load driving circuit, and driving the load with a constant current corresponding to a predetermined constant current source within the current mirror circuit. .

[Effect]

Current mirror circuits are less susceptible to variations in process conditions and can therefore reduce transient currents.

Further, by using a voltage limiter, the voltage can be kept low and constant, and power consumption can be suppressed.

〔Example〕

Hereinafter, one embodiment of the circuit of the present invention will be explained with reference to FIG. 1, and its operation timing will be explained with reference to FIG. 2.

In DRAM, one of the data pair lines is connected to a memory cell (
There is an example of a memory cell consisting of one MO8T and one capacitor).
Charging is done with the well-known sense amplifier formed by sT. In this case, the latest megabit DRAM
In this case, it is necessary to simultaneously charge 1024 pairs of data lines at high speed.

Since the total capacitance of these data lines reaches 500 to 1000 pF, overcurrent becomes a problem. This charging is PMOS
This is performed by a drive circuit DRV connected to the common line cQ of the flip-flop, which is also a sense amplifier formed by T.

This embodiment is characterized in that this drive circuit is composed of a current mirror circuit and a comparator. The mirror circuit to Karen 1 is controlled by a type of inverter consisting of transistors Q□ and Q2. When Q2 is on and Q is off, a current mirror circuit is formed between Q3, the constant current source (i/n) and the output drive transistor Qo, and when Q2 is off and Ql is on.

QD is turned off. The current source in the mirror circuit is i/n, M
If the gate width of O8T is w/n and the gate width of Qo is W, then the on-current of Qo is a constant power supply i. Even if W or the gate length or the threshold voltage of the transistor changes due to variations in the manufacturing process, if i/n is kept constant, the QD driving constant current will be constant. Here the constant current source is i/n.

The reason why it is set as w/n is to reduce the consumption 'editorial' and the occupied area, and the larger n is, the better.

The comparator is connected to a predetermined internal power supply VCL (for example, 4
V) and output voltage V. This is a comparison. VCL
> At Vo, the output of the comparator becomes a high voltage, and vice versa.

When L<vo, the voltage is low. Note that voL may be generated within the chip from Vcc (externally applied power supply voltage).

The operation will be explained based on the above preparation.

In a normal DRAM, the data pair lines are set to approximately half the value of vcL during the precharge period, which is a so-called half precharge method. Therefore, during the precharge period, the common drive line CΩ or all the data pair lines are , / 2
is precharged. In this state, when a pulse is applied to the selected word line, a minute differential read signal appears on each data pair line. This situation is shown in Figure 2 as D O+D. Shown symmetrically and representatively. after that,
In the sense amplifier formed by nMOST and pMOST, the low voltage side is discharged to 0■, and the high voltage side is charged to vcL. Discharge occurs through the common drive line cQ' of each nMO3T
This is done by applying low voltage pulses to the Here, only an example in which charging is performed by a pulse applied to the common drive line cQ of PMOST will be described below. cQ is driven by applying an input pulse φ. When the input pulse φ turns on (high voltage is input), the control circuit AND
The output voltage of becomes a high voltage, and the gate voltage of the QD is V.

is the output voltage vS of the constant current source, and Qo drives the load with a constant current i. As a result, the voltage of the load V o l:!
V c t, rises at a constant rate from /2, but
When vcL is exceeded, the comparator is activated and the output of the control circuit AND becomes a low voltage, Ql is turned on, Q2 is turned off, QD is turned off, and vo is clamped almost to vcL.

This causes one data line of each data pair to be at V. L/
2 to almost vcL.

The above embodiment is an example of constant current generation using a comparator in combination with a voltage limiter. However, even when a voltage limiter is not used (when there is no output loop of the comparator), the mirror circuit can be controlled by the input pulse φ, so that a constant current is possible.

Further, as the constant current source, a circuit using a well-known bipolar transistor or the like is suitable. Also, the faster the response time of the comparator is than the response time of the output vo, the more V. is V.

LC: Since it can be made as close as possible, the comparator can be configured with a bipolar transistor suitable for high speed in some cases.

Further, the concept of the present invention can also be applied to the common drive of the sense amplifier configured with nMOsT and the drive of W c Q'. This allows the charging waveform and discharging waveform to be controlled arbitrarily. For example, if both waveforms are made completely complementary, the data line can be connected to another conductor (Si substrate).

Noise coupled to the word line, etc.) can also be completely canceled out.

Memories with wide operating margins can also be designed.

Moreover, the present invention is not limited to application to DRAM data line charging circuits, where transient currents are particularly problematic.

If applied to the data output section of all memories with a multi-bit configuration (a configuration in which multiple data outputs are output from one chip) or the address output section of a microcomputer, etc., it is effective as a countermeasure against transient currents.

〔Effect of the invention〕

By controlling the current mirror circuit as described above, it is possible to arbitrarily control the discharge current, which was left unchecked in the past, so transient currents can be suppressed, noise within the LSI chip is reduced, and chip design becomes easier. Also, for the user, the noise from the chip mounted on the card is reduced, making it easier to design the card. In addition, since a constant voltage pulse can be obtained at a low voltage, the power consumption of the chip can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram in which the present invention is implemented in a DRAM chip, and FIG. 2 is a diagram showing the operation timing of the present invention. DRV: Constant current, constant voltage drive circuit V , , , : Comparison voltage

Claims (1)

[Scope of Claims] 1. A semiconductor device characterized in that a current mirror circuit is formed by a pulse input voltage, and the output current of the mirror circuit is a constant current. 2. The output voltage of the current mirror circuit is compared with a predetermined comparison voltage by a comparator, and the mirror circuit is controlled with the output voltage of the comparator according to the comparison result. The semiconductor device according to item 1.