JPS63142929A - Stuff synchronization control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] In the stuff synchronous multiplex converter, a clock from a standby oscillator is used when the input signal is disconnected, and this oscillation frequency is made sufficiently lower than the frequency of the input signal of the lower order group. This makes it possible to reduce the cost of this oscillator and downsize the accompanying circuit.

[Industrial application field]

The present invention provides a stuff synchronous multiplex converter that inserts an extra pulse (hereinafter referred to as a stuff pulse) into a plesiochronous signal to match the frequencies between the signals and perform time division multiplexing. This invention relates to a synchronous control method.

Plesiochronous refers to the relationship between two digital signals when their bit rates are nominally the same (eg, 2048 Kbits/sec). The actual bit transmission rate can then differ from the nominal value within a predetermined tolerance range (for example 5.times.10).

In a digital communication system that has a hierarchical structure in transmission frequencies, when a low-order group input signal is disconnected, an AIS (Alarm I
ndication Signal) signal,
This prevents alarms from occurring in subsequent devices.

That is, a standby oscillator is provided, and when the input signal is disconnected,
The clock transfer circuit is switched to the standby oscillator to generate the clock, and stuff pulses are inserted into the necessary parts of the read clock generated by the high-order group frequency oscillator and transferred.

It is desirable that the standby oscillator used at this time be inexpensive and that the accompanying circuitry be small.

[Conventional technology]

FIG. 4 is a block diagram showing the circuit configuration of a device using the conventional stuff synchronization control method.

In FIG. 4, a clock of a digital input signal (the frequency corresponding to its transmission speed is set to 7) is regenerated by a receiving circuit 10, and the signal data is transmitted directly or the clock is transmitted through a clock switching circuit 50'. The data is written to the storage device 20.

On the other hand, a high-order group frequency oscillator (its frequency is f4)
A read clock generated by the read clock generation circuit 70 based on the output 906 and divided into one channel is read out by the storage device 20 via the inhibit circuit 60. At this time, the read clock is input signal speed (f)
) is set slightly higher than the storage device 20.
The input signal is synchronized with the read clock and multiplexed from the storage device 20 by comparing the phase information of the write clock and the read clock in the stuff determination circuit 40' and inserting a stuff pulse into the read clock if necessary. The data is transferred to a department (not shown).

Now, when the input signal is cut off, the write clock of the storage device 20 disappears and phase information cannot be obtained, so it becomes impossible to insert an appropriate stuff pulse, and it becomes impossible to transmit an appropriate lock signal to the subsequent device.

For this reason, a standby clock is created in the device from the standby oscillator 81 with the oscillation frequency fl, and when the input signal is cut off, the clock switching circuit 50' is switched to the standby oscillator 81 side by the input cutoff signal output from the input cutoff detection circuit 30. Switch to

In this way, by controlling the standby clock to be used as the write clock for the storage device 20, stuff pulses are inserted in the same way as when there is a human input signal.

[Problem that the invention seeks to solve]

However, in a device using the stuff synchronous control method described above, an oscillator with the same frequency as the low-order group input signal,
A clock switching circuit that operates at that speed is required, and in a high-order group stuff synchronous multiplex converter in which the frequency of the low-order group input signal is high, the cost will be high and the circuit scale will increase.

[Means for solving problems]

The above problem is solved as shown in FIG. 1, when a clock obtained from a digital input signal is applied to the storage device 2o, and the output of the read clock generator 9o which outputs a read clock with a predetermined repetition frequency is used for the above readout. Inhibitor circuit 60 inserting stuff pulse into clock
In addition to the storage device 2 through the input signal, there is also a staff that compares the phases of the clock obtained from the input signal and the read clock to determine when to insert the read clock henostuff pulse, and outputs a signal for controlling the inhibit circuit 60. In the stuff synchronous multiplex converter having the determination circuit 40, when the human input signal is disconnected, the switching circuit 50 is switched by the output of the input disconnection detection circuit 30 that detects the disconnection of the input signal, and the frequency equal to the insertion period of the stuff pulse is changed. In addition to the inhibit circuit 60, the output of the rising edge detection circuit 85 that detects the rising edge of the output signal of the oscillator 80 that outputs the clock is sent via the switching circuit 50 to control the insertion of a stuff pulse into the read clock. This problem is solved by the staff synchronization control method of the present invention.

[Effect]

An oscillator 80 is provided that outputs a signal with a frequency equal to the insertion period of the stuff pulse.
Since a stuff pulse is inserted into the read clock based on the rising edge detection signal of the output signal, there is no need to provide a spare oscillator with the same frequency as the input signal.

〔Example〕

FIG. 2 is a block diagram showing the circuit configuration of a device using the stuff synchronization control method according to the embodiment of the present invention.

The same reference numerals refer to the same objects throughout the design.

In Fig. 2, when the input signal is disconnected, the input disconnection detection circuit 3
The clock switching circuit 50'f is switched to the standby oscillator 82 side by the input disconnection signal of the 0 output.

As mentioned above, the oscillation frequency of the standby oscillator 82 can be made sufficiently lower than the frequency of the input signal, and the rise detection circuit 85 and the clock switching circuit 50 are used to trigger this output at a point corresponding to this frequency.
' to the inhibit circuit 60.

On the other hand, the output of the high-order group frequency oscillator 90' is read out and applied to the inhibit circuit 60 via the clock generation circuit 70, and a stuff pulse is generated at the point where insertion is required by the signal from the standby oscillator 82 mentioned above via the rise detection circuit 85. Insert it.

This output is then transferred to the multiplexer via the storage device 20.

Now, let the transmission rate of the high-order group be f<, that of the input signal of the low-order group be f, and the number of bits in one multiplexed frame is N.
, when the number of information bits per channel in the low-order group is X, the rate at which the read clock is inhibited (stuffing rate) ρ is as shown in Figure 3: ρ = stuffing frequency / (frame frequency) = (Frame frequency xX-fl)/(f4/N) =X-Nx (f7/f length) (2).

Since the stuff pulse can only be inserted once per frame, the frequency finh at which the readout chromic is inhibited is: )−fl ■.

The oscillation frequency of the standby oscillator 82 is as follows in (2) above, for example, if ρ = 0.1, fl = 100 Mbit/s, and N = 1500, then finh = P x (f, (/N) = 0.I X100 M (bits/second) /150
0 = IM (bits/second) x 150, and the conventional standby frequency f, is fl
= 32 Mbit/s, then 1/480 of r7
0, that is, approximately 6 kHz, which is a fairly low frequency.

As mentioned above, the clock generated by the standby oscillator 82 with a frequency sufficiently lower than the frequency of the input signal is added to the inhibit circuit 60 via the rise detection circuit 85 and the clock switching circuit 5 key, and the high-order group frequency oscillator 90 is manually operated. A stuff pulse is inserted into the clock at a predetermined period by the rising edge detection circuit 85 mentioned above, and the output thereof is added to the storage device 20.

In this way, the oscillation frequency of the standby oscillator 82 can be made sufficiently lower than the frequency of the input signal of the low-order group, and the clock switching circuit 50' can also be made small and designed for low frequencies.

〔Effect of the invention〕

According to the present invention, the standby frequency can be set to a frequency sufficiently lower than the frequency of the lower order group of the human input signal,
It is possible to reduce the cost of the oscillator and downsize the accompanying circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram of the principle of the present invention. FIG. 2 is a block diagram of a circuit configuration of a device using the stuffing synchronization control method according to an embodiment of the present invention. FIG. 3 is a diagram illustrating calculation of an example of a stuffing rate formula. , FIG. 4 is a block diagram showing the circuit configuration of a device using a conventional stuff synchronization control method. In the figure, 10 is a receiving circuit, 20 is a storage device, 30 is an input disconnection detection circuit, 40, 40' is a stuff judgment circuit, 50 is a switching circuit, 50' is a clock switching circuit, 60 is an inhibit circuit, and 70 is a read clock generation circuit. 80 is an oscillator, 81 and 82 are standby oscillators, 85 is a rising edge detection circuit, 90 is a read clock generator, 90' is a high-order group frequency oscillator, 100 is an input terminal, and 110 is an output terminal. The present invention f) Principle diagram: 1 time;

Claims (1)

[Claims] A clock obtained from a digital input signal is applied to the storage device (20), and the read clock is stuffed with the output of a read clock generator (90) that outputs a read clock with a predetermined repetition frequency. Inhibit circuit that inserts pulses (
60) in addition to the storage device (20), the inhibit circuit compares the phase of the clock obtained from the input signal and the read clock to determine when to insert a stuff pulse to the read clock; (60)
In a stuff synchronous multiplex converter having a stuff judgment circuit (40) that outputs a signal to control the switching circuit, when the input signal is cut off, the switching circuit is activated by the output of the input cutoff detection circuit (30) that detects the cutoff of the input signal. (50) to output the output of the rising edge detection circuit (85) which detects the rising edge of the output signal of the oscillator (80) which outputs a clock with a frequency equal to the insertion period of the stuff pulse. , inhibit circuit (6
0), a stuffing synchronization control method characterized in that, in addition to the above, insertion of a stuffing pulse into the read clock is controlled.