JPS63149498U - - Google Patents

Info

Publication number
JPS63149498U
JPS63149498U JP4226387U JP4226387U JPS63149498U JP S63149498 U JPS63149498 U JP S63149498U JP 4226387 U JP4226387 U JP 4226387U JP 4226387 U JP4226387 U JP 4226387U JP S63149498 U JPS63149498 U JP S63149498U
Authority
JP
Japan
Prior art keywords
resistor
inverting amplifier
inverting
control signal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4226387U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4226387U priority Critical patent/JPS63149498U/ja
Publication of JPS63149498U publication Critical patent/JPS63149498U/ja
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、この考案のサンプル・ホールド回路
の一実施例を示す回路図、第2図は、第1図に示
した反転増幅器の開ループゲイン特性を示す図、
第3図は、この考案のサンプル・ホールド回路の
他の実施例を示す回路図、第4図は、従来のサン
プル・ホールド回路の一例を示す回路図である。 11,21…サンプル・ホールド回路、2…反
転増幅器、3…サンプリングスイツチ、R…入
力抵抗、R…帰還抵抗、R,R…抵抗、C
…ホールドコンデンサ。
FIG. 1 is a circuit diagram showing an embodiment of the sample-and-hold circuit of this invention, and FIG. 2 is a diagram showing the open-loop gain characteristics of the inverting amplifier shown in FIG.
FIG. 3 is a circuit diagram showing another embodiment of the sample and hold circuit of this invention, and FIG. 4 is a circuit diagram showing an example of a conventional sample and hold circuit. 11, 21...Sample and hold circuit, 2...Inverting amplifier, 3...Sampling switch, R1...Input resistance, R2 ...Feedback resistance, R3 , R4 ...Resistance, C
...Hold capacitor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力抵抗と帰還抵抗の抵抗比に応じた利得をも
つ反転増幅器と、この反転増幅器の反転入力端子
と出力端子の間に設けたホールドコンデンサと、
前記反転増幅器の反転入力端子と前記入力抵抗の
間に設けられ、外部から供給される開閉制御信号
により開閉するサンプリングスイツチと、このサ
ンプリングスイツチと前記反転入力端子の間に設
けられ、サンプリングスイツチを突き抜けて入来
する開閉制御信号を抑制する抵抗からなるサンプ
ル・ホールド回路。
An inverting amplifier having a gain according to the resistance ratio of an input resistance and a feedback resistor, a hold capacitor provided between an inverting input terminal and an output terminal of this inverting amplifier,
a sampling switch provided between the inverting input terminal of the inverting amplifier and the input resistor and opened and closed by an open/close control signal supplied from the outside; A sample-and-hold circuit consisting of a resistor that suppresses the incoming opening/closing control signal.
JP4226387U 1987-03-23 1987-03-23 Pending JPS63149498U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4226387U JPS63149498U (en) 1987-03-23 1987-03-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4226387U JPS63149498U (en) 1987-03-23 1987-03-23

Publications (1)

Publication Number Publication Date
JPS63149498U true JPS63149498U (en) 1988-10-03

Family

ID=30858011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4226387U Pending JPS63149498U (en) 1987-03-23 1987-03-23

Country Status (1)

Country Link
JP (1) JPS63149498U (en)

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