JPS63149623U - - Google Patents

Info

Publication number
JPS63149623U
JPS63149623U JP4155987U JP4155987U JPS63149623U JP S63149623 U JPS63149623 U JP S63149623U JP 4155987 U JP4155987 U JP 4155987U JP 4155987 U JP4155987 U JP 4155987U JP S63149623 U JPS63149623 U JP S63149623U
Authority
JP
Japan
Prior art keywords
signal
circuit
amplifying
amplifying means
attenuates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4155987U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4155987U priority Critical patent/JPS63149623U/ja
Publication of JPS63149623U publication Critical patent/JPS63149623U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路図、第2
図は本考案の他の実施例を示す回路図、第3図は
TONE回路の一実施例を示す回路図、第4図は
減衰回路の一実施例を示す回路図、第5図は従来
の構成による減衰動作を示すグラフ図、第6図は
本考案の構成による減衰動作を示すグラフ図であ
る。 1:信号入力端子、2:前置増幅回路、3:T
ONE回路、4:主増幅回路、5:スピーカ、6
:整流回路、7:時定数回路、8:スイツチング
トランジスタ、9:減衰回路、10:切換回路。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
3 is a circuit diagram showing an embodiment of the TONE circuit, FIG. 4 is a circuit diagram showing an embodiment of the attenuation circuit, and FIG. 5 is a circuit diagram showing an embodiment of the TONE circuit. FIG. 6 is a graph showing the damping operation according to the structure of the present invention. 1: Signal input terminal, 2: Preamplifier circuit, 3: T
ONE circuit, 4: Main amplifier circuit, 5: Speaker, 6
: rectifier circuit, 7: time constant circuit, 8: switching transistor, 9: attenuation circuit, 10: switching circuit.

Claims (1)

【実用新案登録請求の範囲】 入力信号を増幅する増幅手段と、 該増幅手段の出力信号が所定レベル以上になる
と作動して該増幅手段の信号を周波数に応じた割
合で減衰する減衰手段とを有することを特徴とす
る信号レベル制御装置。
[Claims for Utility Model Registration] Amplifying means for amplifying an input signal; and attenuating means that operates when the output signal of the amplifying means exceeds a predetermined level and attenuates the signal of the amplifying means at a rate corresponding to the frequency. A signal level control device comprising:
JP4155987U 1987-03-20 1987-03-20 Pending JPS63149623U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4155987U JPS63149623U (en) 1987-03-20 1987-03-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4155987U JPS63149623U (en) 1987-03-20 1987-03-20

Publications (1)

Publication Number Publication Date
JPS63149623U true JPS63149623U (en) 1988-10-03

Family

ID=30856672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4155987U Pending JPS63149623U (en) 1987-03-20 1987-03-20

Country Status (1)

Country Link
JP (1) JPS63149623U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007027821A (en) * 2005-07-12 2007-02-01 Alpine Electronics Inc Audio apparatus

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50104847A (en) * 1974-01-19 1975-08-19

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50104847A (en) * 1974-01-19 1975-08-19

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007027821A (en) * 2005-07-12 2007-02-01 Alpine Electronics Inc Audio apparatus

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