JPS63149642U - - Google Patents
Info
- Publication number
- JPS63149642U JPS63149642U JP4283487U JP4283487U JPS63149642U JP S63149642 U JPS63149642 U JP S63149642U JP 4283487 U JP4283487 U JP 4283487U JP 4283487 U JP4283487 U JP 4283487U JP S63149642 U JPS63149642 U JP S63149642U
- Authority
- JP
- Japan
- Prior art keywords
- discharge
- input signal
- discharge time
- voltage
- constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 1
- 230000003247 decreasing effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は、本考案の一実施例を示す構成ブロツ
ク図、第２図は、第１図の装置の動作を説明する
波形図、第３図は、較正動作を説明する波形図で
ある。第４図は、従来公知のマルチスロープ型Ａ
ＤＣの構成ブロツク図、第５図は、コンデンサＣ
に蓄えられた電圧Ｖａの波形図である。
Ｒ１，ＳＷ１……入力信号部、Ｉ１，Ｉ２……
定電流回路、Ｕ９……クロツク、Ｕ７，Ｕ８……
カウンタ、Ｖｒｅｆ……リフアレンス電圧部、Ｖ
ｔｈ１，Ｖｔｈ２……較正電圧発生部、ＭＰＵ…
…補正演算部。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram explaining the operation of the apparatus shown in FIG. 1, and FIG. 3 is a waveform diagram explaining the calibration operation. Figure 4 shows a conventionally known multi-slope type A.
The DC configuration block diagram, Figure 5, shows the capacitor C.
FIG. 2 is a waveform diagram of voltage Va stored in FIG. R1, SW1...Input signal section, I1, I2...
Constant current circuit, U9...Clock, U7, U8...
Counter, Vref...reference voltage section, V
th1, Vth2...Calibration voltage generation section, MPU...
...Correction calculation section.
Claims (1)
のしきい値まで放電して第１の放電時間Ｔ１を測
定する第１の定放電回路、 当該第１の定放電電流で所定のしきい値Ｖｔｈ
まで低下した積分信号を、前記第１の定放電電流
よりも所定の比α−１で小さくした第２の放電電
流で零まで放電して第２の放電時間Ｔ２を測定す
る第２の定放電回路、 この第１及び第２の放電時間から前記入力信号
の電圧を定める演算部、 とを備えたアナログ・デイジタル変換装置におい
て、 入力信号として基準電圧を供給するリフアレン
ス電圧部、 前記しきい値として第１のしきい値電圧Ｖｔｈ
１とこれよりも小さな第２のしきい値電圧Ｖｔｈ
２を発生する較正電圧発生回路と、 この較正電圧発生回路で供給した第１のしきい
値電圧に対応する第１の放電時間Ｔ１１と第２の
放電時間Ｔ２１と、第２のしきい値電圧に対応す
る第１の放電時間Ｔ１２と第２の放電時間Ｔ２２
とを求め、前記所定の比を次のしきで補正する補
正演算部、 を具備することを特徴とするアナログ・デイジタ
ル変換装置。 記 α＝（Ｔ２１−Ｔ２２）／（Ｔ１２−Ｔ１１）[Claims for Utility Model Registration] An input signal section that integrates an input signal over a predetermined time period, and discharges this integrated signal to a predetermined threshold value with a first constant discharge current to measure the first discharge time T1. a first constant discharge circuit that has a predetermined threshold value Vth at the first constant discharge current;
A second constant discharge, in which the integrated signal that has decreased to zero is discharged to zero with a second discharge current that is smaller than the first constant discharge current by a predetermined ratio α −1 , and a second discharge time T2 is measured. An analog-to-digital converter comprising: a circuit; a calculation unit that determines the voltage of the input signal from the first and second discharge times; a reference voltage unit that supplies a reference voltage as the input signal; First threshold voltage Vth
1 and a second threshold voltage Vth smaller than this
2; a first discharge time T11 and a second discharge time T21 corresponding to the first threshold voltage supplied by the calibration voltage generation circuit; and a second threshold voltage. The first discharge time T12 and the second discharge time T22 corresponding to
An analog-to-digital conversion device comprising: a correction calculation unit that calculates the predetermined ratio and corrects the predetermined ratio using the following threshold. Note α=(T21-T22)/(T12-T11)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4283487U JPS63149642U (en) | 1987-03-24 | 1987-03-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4283487U JPS63149642U (en) | 1987-03-24 | 1987-03-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63149642U true JPS63149642U (en) | 1988-10-03 |
Family
ID=30859129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4283487U Pending JPS63149642U (en) | 1987-03-24 | 1987-03-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63149642U (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5961313A (en) * | 1982-09-30 | 1984-04-07 | Ando Electric Co Ltd | Method for correcting output of ad converter |
| JPS6074820A (en) * | 1983-09-30 | 1985-04-27 | Toshiba Corp | Analog/digital converter |
| JPS60134628A (en) * | 1983-12-23 | 1985-07-17 | Toshiba Corp | A/d converter |
| JPS61163722A (en) * | 1985-01-12 | 1986-07-24 | Sony Corp | A/d converter |
| JPS61177025A (en) * | 1985-02-01 | 1986-08-08 | Hitachi Ltd | A/d conversion circuit |
-
1987
- 1987-03-24 JP JP4283487U patent/JPS63149642U/ja active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5961313A (en) * | 1982-09-30 | 1984-04-07 | Ando Electric Co Ltd | Method for correcting output of ad converter |
| JPS6074820A (en) * | 1983-09-30 | 1985-04-27 | Toshiba Corp | Analog/digital converter |
| JPS60134628A (en) * | 1983-12-23 | 1985-07-17 | Toshiba Corp | A/d converter |
| JPS61163722A (en) * | 1985-01-12 | 1986-07-24 | Sony Corp | A/d converter |
| JPS61177025A (en) * | 1985-02-01 | 1986-08-08 | Hitachi Ltd | A/d conversion circuit |
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