JPS63155773A - Monolithic microwave ic - Google Patents

Abstract

PURPOSE:To improve output and efficiency, by boring holes in a rear region of the active element as deeply as they advance to an etching stopper layer interposed between a semiconductor substrate and the active layer so that thermal resistance of the element part is decreased. CONSTITUTION:A GaAlAs layer 12, a high resistance GaAs layer 13, and a GaAs active layer 14 are serially on formed a substrate 11. Next, source electrodes 15, drain electrodes 16, gate electrodes 17, and strip rails 18 are formed. Next, the substrate 11 is thinned to be 200mum or so in thickness, and successively holes 20 are bored at positions corresponding to FET-formed regions as deeply as they advance to the first layered GaAlAs layer by etching the rear of the substrate. Since a ratio of an etching speed in the substrate 11 to that in the first layered GaAlAs layer 12 is 100:1, the etched holes 20 stop in the GaAlAs layer. Similarly, through holes 21 are formed, and a thick film conductor 22 is on the rear side of the substrate 11 by gold plating or the like so as to bury the holes 20 and the through holes 21.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to integrated circuits in the ultra-high frequency region, more specifically, monolithic microwave ICs (hereinafter abbreviated as MMIC) using active elements such as FETs. This invention relates to a structure suitable for increasing the frequency and output of an amplifier.

[Conventional technology]

Generally, MMIC amplifiers using GaAsFETe are fabricated using FETs on a semi-insulating GaAS substrate with a thickness of approximately 200 μm or more.
Many of them consist of a microwave circuit using a strip line and a microwave circuit.

Conventional GaAs MMIC amplifiers handle only 1 signal level.
The power was relatively small at 00 mW or less, and the heat sink of the FET did not pose any particular problem even in the above configuration.

However, in order to obtain an amplifier with higher frequency and higher output, it is necessary to reduce the thickness of the semi-insulating GaAS substrate as much as possible in order to reduce thermal resistance and source inductance. For example, an example of a 28 GHs, IW F'ET with a semi-insulating substrate thickness of 30 μm is published in the Journal of the Institute of Electronics and Communication Engineers '85/12 Vol. No. 12 No. 199
Reported on pages ~997.

However, when the substrate is made thinner, the conductor width of the stripline decreases and line loss increases. FIG. 2 shows the dependence of line loss on substrate thickness.

The line loss increases as the circuit scale increases, and significantly reduces the output and efficiency of the amplifier.

[Problem that the invention seeks to solve]

In the conventional technology mentioned above, the line loss of the strip line increases as the circuit scale increases, and the output of the amplifier increases.

There were drawbacks that significantly reduced efficiency. Furthermore, it has been difficult to thin the semi-insulating substrate with good reproducibility.

The purpose of the present invention is to reduce the thermal resistance and source inductance of the element without increasing circuit loss in an MMIC that includes elements with a relatively large amount of heat, such as high-output FETs, and to output power at ultra-high frequencies. The object of the present invention is to provide MMICe that has excellent efficiency and can be manufactured with good reproducibility.

[Failure to solve the problem]

The above purpose is to form a crystal growth layer (etching stopper layer) 2 having a high etching selectivity with respect to the semiconductor substrate 1 as a first layer on a semiconductor substrate 1, as shown in FIG. 1, and an active layer as a second layer or higher. Used for wafers with MMIC overall f: 10
It consists of a semi-insulating substrate with a thickness of 0 μm or more, and selectively etches only the semi-insulating substrate in the element part, which causes an increase in thermal resistance and source inductance, to form the first layer (etching stopper layer). Drill hole 4 until it reaches 20~3
Make it as thin as 0 μm. This can be achieved by reducing thermal resistance and source inductance without incurring circuit losses.

[Effect]

The first crystal growth layer 2 is a layer whose etching rate is extremely slow relative to the semiconductor substrate 1, and when the substrate 1 is partially etched to form the hole 4, the first layer 2 is etched in the depth direction. Since etching does not proceed to the crystal layer 3 having a second or higher active layer unless it is a single-layer etching stopper, the active layer element portion can be thinned with good reproducibility.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIG. 3, taking as an example an MMIC using p-high frequency and high power GaASFETe.

(1) On a semi-insulating GaAs substrate 11, a first layer is a GaAtAs layer 12 with a thickness of 1 μm, a second layer is a high resistance Q a A 8 layer 13 with a thickness of 20 μm, and a third layer is a GaAS active layer 14. The whole layer is epitaxially grown to a thickness of 0.3 μm. Si is used as a donor impurity in the active layer, and its carrier concentration is 3.times.10"cm.sup.-". The epitaxial growth of these layers involves monocular
A beam epitaxial growth method or a metal organic vapor phase growth method is used.

(2) Source electrode 15 at a desired position on the surface of active layer 14
, drain electrode 16. The gate electrode 17 and the strip line 18 are formed using a normal vapor deposition technique, lithography technique, or the like.

(3) The thickness of the semi-insulating substrate 11 is reduced to about 200 μm by polishing or etching. Next, a semi-insulating Q is placed at a position corresponding to the region where the FET is formed.
A hole 20 is opened from the back surface of the aAS substrate 11 by etching to a depth that reaches the first QaAtAs layer. A double-sided mask aligner is used for this alignment, and a resist pattern is formed so that holes can be formed in desired areas.

A parallel plate type dry etching device was used for etching, and a mixed gas of l(e and CCl2F2) was used as the etching gas. At this time, the semi-insulating substrate 11 and the first layer GaAA
The etching rate ratio with respect to the AS layer 12 is 100:1, and the etching hole 20 remains in the G a Atks layer and does not penetrate into the second high-resistance Q a Ass layer 3 .

(4) From the back surface of the semi-insulating substrate 11 at the position corresponding to the source electrode 15 (by the same method as above), through-hole 21
Drill a hole. Etching is performed on the first layer G a A in advance.
All of the tA s layer 12 and the second high resistance GaAs layer 1
3) 12i9Q4°H202: H
After performing wet etching with a 20 series etching solution, the third active layer 14 is etched through the third active layer 14 until it reaches the back surface of the source electrode 15 under the condition that a hole 20 is formed by a dry etching method.

(5) The thick film conductor 22' is coated on the back side of the semi-insulating substrate 11 with gold plating or the like so as to fill the hole 201 through hole 21.

According to the present invention, when an MMIC in the ultra-high frequency region includes an element with a relatively large amount of heat, such as a high-output FET, there is no increase in circuit loss.

The thermal resistance and source inductance of the element section can be reduced, making it possible to realize an MMIC with excellent output and efficiency.

In this example, a case was described in which a GaAS layer lamp was used as an active element, but HEMT (HighEle
ctron Mobility 'l'ransist
or) and HBT (Hetero Bipolar Tr)
It is clear that it is also useful when using ``Ansistor'' etc.

Furthermore, this example describes an example in which GaAtAs is grown directly on the substrate as the first layer, but the buffer layer 1G
aA! Needless to say, it may be formed in advance before growing the As layer.

〔Effect of the invention〕

As explained above, according to the present invention, M in the ultra-high frequency region
In MIC, are elements with relatively large heat generation such as high output FETs? When included, without increasing circuit loss,
MM that can reduce the thermal resistance of the element part and has excellent output and efficiency
IC can be realized with good reproducibility.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the crystal structure of the present invention, FIG. 2 is a graph showing the dependence of the transmission loss of a strip line on the thickness of a semi-insulating GaAs substrate, and FIG. 3 is a high-frequency
FIG. 1 is a cross-sectional view showing a method of manufacturing an MMIC including a high-output FE'l. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... First crystal growth layer, 3...
... second or higher crystal growth layer, 11... semi-insulating Ga
AS substrate, 12-GaAtAs layer, 13-...high resistance G
aAS layer, 14... active layer, 15... source electrode,
16...Drain electrode, 17...Gate electrode, 18
...Strip line, 4,20...hole, 21...
Through hole, 22...thick film conductor.

Claims (1)

[Claims] 1. In a microwave IC in which an active element and a microwave circuit are formed on the surface of a semiconductor, etching is applied to the back surface of the active element region to a depth that reaches the etching stopper layer interposed between the semiconductor substrate and the active layer. A monolithic microwave IC characterized by having holes.