JPS6315810B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital protection relay, and more particularly to a digital protection relay that protects a power system using digital information from the power system.

2. Description of the Related Art Conventionally, there is a voltage balance relay as a relay that operates when the difference in input information between two voltages is equal to or greater than a certain value. To digitally process this relay, a so-called area calculation method has been used until now.

The calculation configuration when this method is used is shown in FIG. That is, in block 10 the input v _a
In block 11, the output from block 10 is integrated by a constant number to calculate the effective value V _a of v _a . Similarly, for other inputs v′ _a , block 1
2 and 13, calculate the effective value _V'a of _v'a . This is a processing method called area type. Next, block 14 selects block 1 from the output of block 11.
Subtract the output of 3, block 15 and block 14
The absolute value of the output of block 16 is taken, and the predetermined setting value V ₀ is determined from the output of block 15 in block 16.
Subtract. Then, when the output of block 16 is above a certain value, the relay is activated.

However, if the above-mentioned area form is used in calculation processing, errors will occur in principle depending on the sampling frequency. The error in the case of the area type is determined by the ratio of the input to the information, and if the absolute value of this error is εv, then the maximum value of the error when the difference between the two inputs is taken is 2εv. As mentioned above, this type of relay inputs two voltages and compares the difference between them with a set value, and the set value must be large enough to correspond to the difference between the inputs.
The value is smaller than the input. If the ratio of the above error to the set value V ₀ is ε, then ε=2εv/V ₀ ×100(%) (1).

Now, input is 110V, sampling frequency is 600
Hz, the calculation error is ±1.7%, and εv
=1.9V. Therefore, if the setting value V ₀ is 20V, ε = 2 × 1.9 / 20 × 100 = 19 (%) ... (2), and the error with respect to the setting value is ±19%, which is not practical. .

The present invention has been made in view of the above, and an object of the present invention is to provide a digital protection relay that can significantly improve accuracy.

A feature of the present invention is to compare the difference between two pieces of input information from the power system sampled at a predetermined time with a set value, and calculate the effective values of the two pieces of input information as V _a and V′ a respectively, and the set value as V a and V′ _a respectively. When is V ₀ , (V ² _a −
V′ ² _a ) and V ₀ (V _a +V′ _a ) or |V ² _a −V′ ² _a | and V ₀
(V _a +V′ _a ).

The present invention will be explained in detail below with reference to the embodiments shown in FIGS. 2, 4 to 8, and FIG.

Although not shown, the digital protection relay according to the present invention inputs two pieces of voltage or current information sampled from the power system at regular time intervals, detects the difference between these two inputs, and detects the difference between the two inputs. It is configured to compare the set value and operate when the difference is greater than or equal to a predetermined value.

By the way, when detecting the difference between the above two inputs and comparing this with a set value, in order to improve the accuracy, it is necessary to devise an arithmetic processing method.

First, the basic idea of the present invention will be explained. The operating formula for a voltage balanced relay is expressed by the following equation, where the effective values of the two inputs are V _a and V′ _a and the set value is V ₀ .

|V _a |−|V′ _a |>V ₀ …(3) Multiplying both sides of equation (3) by (V _a +V′ _a ), |V ² _a −V′ ² _a |>V ₀ (V _a + V′ _a ) …(4). Therefore, in the present invention, we adopt a product method that does not cause any operational errors in the calculation of the left side of equation (4) and can relatively easily calculate V ² _a and V′ ² _a . , it is relatively easy to calculate the right-hand side
The operating limit was determined using the above-mentioned area type method that can determine V ₀ and V ₀ '. In the embodiment of the present invention, the instantaneous value of the voltage is sampled, and the effective value is calculated based on this value. There are two methods for calculating the effective value: the product method and the area method. will occur. On the other hand, the stacking method is
Although this method uses sampling data for calculations, basically no errors occur due to calculations. For details on the area type method and volume type method, please refer to Hitachi Hyoron.
It is described in the paper entitled "Digital Protective Relay Device" on pages 779 to 784 of Vol. 61 No. 11 (1979-11). When considering general A/D conversion, the sampling error is 12 bits, and can be thought of as 1 bit, which is an order of magnitude smaller than the error caused by the area type method (area type method). The error is approximately ±1.7% when sampling at approximately 12 times the input frequency).

In actual processing, V _a and V′ _a on the right side of equation (4) are replaced by V _a ,
It is determined from the instantaneous values v _{a and} v′ a of V′ _a using the area type method described above. Therefore, the calculated values of V _a and V′ _a include an error ε (%) depending on the sampling frequency.
Considering this, and assuming V _a > V′ _a , equation (4) becomes V ² _a −V′ ² _a = V ₀ (V _a +V′ _a ) (1+ε/100) …(5), which Solving, (V ₀ −V′ _a )(V _a +V′ _a ) =V ₀ (V _a +V′ _a )(1+ε/100) …(6), and from equation (6), V _a −V ′ _a /1+ε/100=V ₀ (7) is obtained, and it can be seen that the operational error is determined only by the error ε due to the area type method, regardless of the setting value V ₀ .

Next, the above specific processing will be explained. Second
The figure is a block diagram showing one embodiment of the above processing. In FIG. 2, 100 and 102 are square calculation units, 101 and 103 are integration units, 104 is a subtraction unit,
105 is an absolute value calculation section, 106 and 108 are absolute value calculation sections, 107 and 109 are integration sections, 110 is an addition section, 111 is a multiplication section, and 112 is a subtraction section. First, block 100 calculates the square of the input v _a , and block 101 integrates the output of block 100 by a certain number to obtain the square of the effective value V _a (product form method). on the other hand,
In block 102, the square of the input _v'a is determined, and in block 103, the output of block 102 is integrated by a constant number to obtain the square of the effective value _V'a . In block 104, the output of block 103 is subtracted from the output of block 101, and in block 105, the output of block 103 is subtracted from the output of block 101.
Obtain the absolute value of the output of 04. Also, block 10
Step 6 obtains the absolute value of input v _a , and block 107 integrates the output of block 106 by a fixed number to obtain the effective value V _a
(area type method). On the other hand, block 108 obtains the absolute value of input _v'a , and block 109 integrates the output of block 108 by a constant number to obtain effective value _V'a . Block 110 adds the output of block 109 to the output of block 107, and
At step 11, the output of block 110 is multiplied by the set value _V0 . Then, in block 112, block 1
Subtract the output of block 111 from the output of block 05,
When the result is positive, the relay body (not shown) is activated, and when it is negative, it is deactivated.

Next, the performance when the above processing method is adopted will be explained. Blocks 106 and 107 are conventional area-type processing, which, as described above, introduces errors. When formula (4) is changed into a formula that takes into account the error, it becomes the formula (5) mentioned above, and when finding the limit V′ _a when V _a and V ₀ are given, V′ _a = V _a − (1+ε/100)V ₀ ...(8), and by substituting V _a = 110V, V ₀ = 20V, and ε = 1.7%, V' _a = 110-(1+0.017) x 20 = 89.66 (V)... (9) becomes. The ratio to the set value at this time is found to be (110-89.66)/20=1.017, resulting in an error of 1.7%. FIG. 3 is a diagram showing errors for various setting values. Curve a is the relationship based on the conventional method in FIG. 1, and curve b is the relationship in the case in accordance with the present invention in FIG. 2. It can be seen that the accuracy is significantly improved.

FIG. 4 is an arithmetic processing block diagram showing another embodiment of the present invention, in which the same blocks as in FIG. 2 are designated by the same reference numerals. In FIG. 4, the order of the integrating sections 101, 103 and the subtracting section 104 in FIG. 2 is changed,
Further, the order of the integrating sections 107, 109 and the adding section 110 is changed, and even with this arrangement, the same effect as in FIG. 2 can be obtained.

FIG. 5 is an arithmetic processing block diagram showing still another embodiment of the present invention. In Figure 5, 200
201 is an addition section, 201 is a subtraction section, 202 and 207 are absolute value calculation sections, 203 and 206 are integration sections, 204,
205 is a multiplication section, and 208 is a subtraction section. Block 200 calculates the sum of the inputs v _a and v' _a (v _a + v' _a ),
Block 201 calculates the difference between the inputs v _a and v' _a (v _a - v' _a ), block 202 calculates the absolute value of the output of block 200, and block 203 calculates the absolute value of the output of block 200.
The output of block 203 is integrated by a constant number, and in block 204, the output of block 203 is multiplied by a set value _V0 . on the other hand,
Block 205 calculates the product of the output of block 200 and block 201, block 206 integrates the output of block 205 by a fixed number, and block 207 takes the absolute value of the output of block 206.
Then, in block 208, the output of block 204 is subtracted from the output of block 207, and as in the second case,
When the output of block 208 is positive, the relay body (not shown) is activated, and when it is negative, it is deactivated.
Even if this is done, the effect is the same as in the case of FIG.

The explanation so far has been based on equation (4), but equation (4) means that when V ² _a −V′ ² _a >0, V ² _a −V′ ² _a >V ₀ (V _a +V′ _a ) …(10) When V ² _a −V′ ² _a <0, the same result can be obtained as V ² _a −V′ ² _a <V ₀ (V _a +V′ ² _a ) …(11) The following characteristics are obtained. Figures 6 and 7 show calculation processing block diagrams corresponding to Figures 2, 4, and 5 when this concept is introduced, respectively.
It is shown in FIG.

In FIG. 6, a determining section 113 is provided after block 104 in FIG. 2, and determines whether the output of block 104 is positive or negative.
In step 2, the output of block 110 is subtracted from the output of block 104, and when it is negative, the output of block 110 is subtracted from the inverted sign of the output of block 104 in block 112a. In either case, if the final output is positive, The relay body is set to operate, and when the voltage is negative, the relay body is set to be inoperative.

In FIG. 7, a determining section 113 is provided after block 101 in FIG. 4, and determines whether the output of block 101 is positive or negative.
In step 2, the output of block 111 is subtracted from the output of block 101, and when it is negative, the output of block 111 is subtracted from the inverted sign of the output of block 101 in block 112a. In either case, if the final output is positive, The relay body is set to operate, and is set to be inoperative when it is negative.

In FIG. 8, a determination unit 209 determines whether the output of block 206 in FIG.
Subtract the output of 04, and if it is negative, block 208
In a, the output of block 206 is subtracted from the output of block 204 whose sign is inverted, and in either case, if the final output is positive, the relay body is activated, and if it is negative, it is inactivated.

In addition, in any case of FIGS. 6 to 8, the effect is the same as in the case of FIG. 2.

In addition, the explanation so far is for a voltage balanced relay, but it can also be applied to other protection relays that seek to obtain protective performance based on the difference between two input information, and the same effect can be obtained.

As explained above, according to the present invention, there is an effect that accuracy can be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional digital protection relay arithmetic processing device, FIG. 2 is a block diagram showing an embodiment of the digital protection relay arithmetic processing device of the present invention, and FIG. 3 is a block diagram of the arithmetic processing device of a conventional digital protection relay. Diagrams for explaining performance, FIGS. 4 to 8 are block diagrams corresponding to FIG. 2 showing other embodiments of the present invention. 100, 102...square calculation unit, 101, 10
3,107,109... Integral section, 104,112
... Subtraction section, 105, 106, 108 ... Absolute value calculation section, 110 ... Addition section, 111 ... Multiplication section,
113...determination section, 200...addition section, 201,
208... Subtraction section, 202, 207... Absolute value calculation section, 203, 206... Integration section, 204, 20
5... Multiplication section, 209... Judgment section.

Claims (1)

[Claims] 1. Digital voltage or current information from the power system sampled at predetermined time intervals is input, and when the difference between the two input information is greater than or equal to a set value, the system operates to control the power system. In a digital protection relay for protection, the difference between the two input information and the set value is compared as follows, when the effective values of the two input information are respectively V _a and V _a ', and the set value is V ₀ .
(V ² _a −V′ _a ² ) and V ₀ (V _a +V′ _a ) or |V ² _a −V′ _a ²
A digital protection relay characterized in that the relay is constructed by comparing | and V ₀ (V _a +V′ _a ). 2 The means for comparing the above (V ² _a −V′ _a ² ) and V ₀ (V _a +V′ _a ) is a first means for calculating the square of one input v _a , and the first means Integrate the output by a predetermined number to obtain V ² _a
a second means for determining the absolute value of v a; a third means for determining the absolute value of v _a ; and integrating the output of the third means for a predetermined number of times.
a fourth means for obtaining V _a ; a fifth means for obtaining the square of the other input v'_a; a sixth means for obtaining V' _a ² by integrating the output of the fifth means by a predetermined number; seventh means for calculating the absolute value of v′ _a ; eighth means for calculating V′ _a by integrating the output of the seventh means by a predetermined number; a ninth means for subtracting the output to obtain (V ² _a −V′ _a ² );
a tenth means for calculating the absolute value of the output of the means; an eleventh means for calculating (V _a +V′ _a ) by adding the output of the fourth means and the eighth output; Claim 1, comprising: a twelfth means for multiplying the output of the means by a set value V ₀ ; and a thirteenth means for subtracting the output of the twelfth means from the output of the tenth means. Digital protection relay. 3 The means for comparing the above (V ² _a −V′ _a ² ) and V ₀ (V _a +V′ _a ) is the first means for calculating the square of one input v _a , and the absolute value of the above v _a a third means for calculating the square of the other input v′ _a ; a seventh means for calculating the absolute value of said v′ _a ; and said fifth means from the output of said first means. a fourteenth means for subtracting the output of (V ² _a
-V′ _a ² ), a tenth means for determining the absolute value of the output force of the fifteenth means, and adding the output of the third means and the output of the seventh means. No.
16 means, 17th means for calculating (V _a +V′ _a ) by integrating the output of the 16th means by a predetermined number, and 12th means for multiplying the output of the 17th means by a set value V ₀ and a thirteenth means for subtracting the output of the twelfth means from the output of the tenth means. 4. The means for comparing |V ² _a −V′ _a ² | and V ₀ (V _a +V′ _a ) is an eighteenth means for adding one input v _a and the other input v′ _a ; 19th means for subtracting said v′ _a from said v _a ;
a 20th means for multiplying the output of the 19th means;
21st means for integrating the output of the means for a predetermined number of times;
22nd means for determining the absolute value of the output of the 21st means |V ² _a −V′ _a ² |; 23rd means for determining the absolute value of the output of the 18th means; 24th means for obtaining (V _a +V′ _a ) by integrating a predetermined number of times;
25th means for multiplying the output of the means by a set value V ₀ ; and 26th means for subtracting the output of the 25th means from the output of the 22nd means. Digital protection relay.