JPS6316700U - - Google Patents
Info
- Publication number
- JPS6316700U JPS6316700U JP11104486U JP11104486U JPS6316700U JP S6316700 U JPS6316700 U JP S6316700U JP 11104486 U JP11104486 U JP 11104486U JP 11104486 U JP11104486 U JP 11104486U JP S6316700 U JPS6316700 U JP S6316700U
- Authority
- JP
- Japan
- Prior art keywords
- generation circuit
- pulse
- signal
- circuit
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本案装置の構成を示すブロツク図、第
２図はその検査信号発生回路の動作説明のための
タイミングチヤート、第３図は本案装置のアドレ
スデコーダの構成を示すブロツク図、第４図はそ
の動作説明のための真理値表、第５図は本案装置
の他の実施例を示すブロツク図である。
１……検査信号発生回路、４……アドレスデコ
ーダ、５……メモリセルアレイ、８……パルス発
生回路、１１……フリツプフロツプ、１２……限
時回路、１３……２進カウンタ、１４，１５……
ＡＮＤゲート。
FIG. 1 is a block diagram showing the configuration of the device of the present invention, FIG. 2 is a timing chart for explaining the operation of the test signal generation circuit, FIG. 3 is a block diagram showing the configuration of the address decoder of the device of the present invention, and FIG. 4 is a truth table for explaining its operation, and FIG. 5 is a block diagram showing another embodiment of the present device. 1...Test signal generation circuit, 4...Address decoder, 5...Memory cell array, 8...Pulse generation circuit, 11...Flip-flop, 12...Time limit circuit, 13...Binary counter, 14, 15...
AND gate.
Claims (1)
メモリ装置において、 前記メモリを検査するための検査信号の発生回
路と、 前記アドレス発生回路の複数の組に分割された
アドレス出力の各組それぞれに備えられ、前記検
査信号が与えられた場合に、１アドレス入力に対
応してそれぞれ１アドレス出力を発生するアドレ
ス出力分割回路と、 を具備することを特徴とするメモリ装置。 ２ 前記検査信号発生回路は、 電源投入時にワンシヨツトパルスを発生するパ
ルス発生回路と、 該パルス発生回路から与えられるパルスにてセ
ツトされるフリツプフロツプと、 前記パルス発生回路からパルスが与えられるこ
とにより、所定時間に亙つて信号を出力する限時
回路と、 前記パルス発生回路から与えられるパルスにて
リセツトされて計数を開始し、その計数値が所定
値に達した場合に信号を出力するカウンタと、 前記限時回路の所定時間に亙る信号出力期間中
に前記カウンタが信号出力した場合に、前記フリ
ツプフロツプをリセツトする回路とを備え、 前記フリツプフロツプのリセツト状態の出力信
号を前記検査信号として前記アドレス発生回路に
与えるべくなしてある実用新案登録請求の範囲第
１項記載のメモリ装置。 ３ 前記カウンタの計数対象は、装置外部から与
えられるパルス信号である実用新案登録請求の範
囲第２項記載のメモリ装置。[Claims for Utility Model Registration] 1. A memory device comprising a memory and its address generation circuit, comprising: a test signal generation circuit for testing the memory; and an address output divided into a plurality of sets of the address generation circuit. an address output dividing circuit, which is provided for each set of and generates one address output in response to one address input when the test signal is applied. 2. The test signal generation circuit includes a pulse generation circuit that generates a one-shot pulse when the power is turned on, a flip-flop that is set by a pulse given from the pulse generation circuit, and a flip-flop that is set by a pulse given from the pulse generation circuit. a time limit circuit that outputs a signal for a predetermined period of time; a counter that is reset by a pulse given from the pulse generating circuit to start counting and outputs a signal when the counted value reaches a predetermined value; and a circuit that resets the flip-flop when the counter outputs a signal during a signal output period of a predetermined time period of the time limit circuit, and provides an output signal of the reset state of the flip-flop to the address generation circuit as the test signal. A memory device according to claim 1, which has been registered as a utility model. 3. The memory device according to claim 2, wherein the object counted by the counter is a pulse signal applied from outside the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11104486U JPS6316700U (en) | 1986-07-18 | 1986-07-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11104486U JPS6316700U (en) | 1986-07-18 | 1986-07-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6316700U true JPS6316700U (en) | 1988-02-03 |
Family
ID=30990604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11104486U Pending JPS6316700U (en) | 1986-07-18 | 1986-07-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6316700U (en) |
-
1986
- 1986-07-18 JP JP11104486U patent/JPS6316700U/ja active Pending
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