JPS63168533U - - Google Patents

Info

Publication number
JPS63168533U
JPS63168533U JP5987087U JP5987087U JPS63168533U JP S63168533 U JPS63168533 U JP S63168533U JP 5987087 U JP5987087 U JP 5987087U JP 5987087 U JP5987087 U JP 5987087U JP S63168533 U JPS63168533 U JP S63168533U
Authority
JP
Japan
Prior art keywords
light
light receiving
control circuit
data input
tablet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5987087U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5987087U priority Critical patent/JPS63168533U/ja
Publication of JPS63168533U publication Critical patent/JPS63168533U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図はこの考案に係るタブレツト
型データ入力装置の一実施例を示すもので、第1
図はそのシステム構成を示すブロツク図、第2図
は同実施例のタブレツト板及び制御装置の具体的
な構成を示すブロツク回路図である。 11…タブレツト板、12…制御装置、121
…発振器、122…水平カウンタ、123…mチ
ヤンネルマルチプレクサ、124…カウントレジ
スタ、125…垂直カウンタ、126…nチヤン
ネルデコーダ、127…CPU、128…フイー
ルドメモリ、13…モニタ用デイスプレイ、14
…入力ペン、Q11〜Qmn…フオトトランジス
タ、S1〜Sn…スイツチ回路。
1 and 2 show an embodiment of a tablet type data input device according to this invention.
The figure is a block diagram showing the system configuration, and FIG. 2 is a block circuit diagram showing the specific configuration of the tablet board and control device of the same embodiment. 11... Tablet board, 12... Control device, 121
...Oscillator, 122...Horizontal counter, 123...m channel multiplexer, 124...count register, 125...vertical counter, 126...n channel decoder, 127...CPU, 128...field memory, 13...monitor display, 14
...Input pen, Q11-Qmn...Phototransistor, S1-Sn...Switch circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の受光素子をマトリツクス状に配置してな
るタブレツト板と、前記複数の受光素子を走査し
て各受光素子の受光状態からデータ入力を検出す
る制御回路と、この制御回路の制御動作及びデー
タの入出力動作を実行する演算制御回路と、前記
タブレツト板の受光面上で少なくとも複数の受光
素子への投光を遮蔽する入力ペンとを具備するタ
ブレツト型データ入力装置。
A tablet board having a plurality of light receiving elements arranged in a matrix, a control circuit that scans the plurality of light receiving elements and detects data input from the light receiving state of each light receiving element, and a control operation of the control circuit and data input. A tablet-type data input device comprising an arithmetic control circuit that performs input/output operations, and an input pen that blocks light from being emitted to at least a plurality of light-receiving elements on the light-receiving surface of the tablet board.
JP5987087U 1987-04-22 1987-04-22 Pending JPS63168533U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5987087U JPS63168533U (en) 1987-04-22 1987-04-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5987087U JPS63168533U (en) 1987-04-22 1987-04-22

Publications (1)

Publication Number Publication Date
JPS63168533U true JPS63168533U (en) 1988-11-02

Family

ID=30891771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5987087U Pending JPS63168533U (en) 1987-04-22 1987-04-22

Country Status (1)

Country Link
JP (1) JPS63168533U (en)

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