JPS63172A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63172A
JPS63172A JP61143638A JP14363886A JPS63172A JP S63172 A JPS63172 A JP S63172A JP 61143638 A JP61143638 A JP 61143638A JP 14363886 A JP14363886 A JP 14363886A JP S63172 A JPS63172 A JP S63172A
Authority
JP
Japan
Prior art keywords
layer
doped
channel
dimensional electron
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61143638A
Other languages
Japanese (ja)
Inventor
Satoru Asai
了 浅井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61143638A priority Critical patent/JPS63172A/en
Publication of JPS63172A publication Critical patent/JPS63172A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60Impurity distributions or concentrations
    • H10D62/605Planar doped, e.g. atomic-plane doped or delta-doped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/40FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To increase the surface density of a two-dimensional electron gas by alternately laminating non-doped channel layers and electron supply layers, which are made thinner than the channel layers and to which an impurity is atomic-plane doped, and forming the integral two-dimensional electron gases among both hetero-junction interfaces of the channel layers. CONSTITUTION:Non-doped channel layers 3b consisting of sutstances such as GaAs and electron supply layers 3a, to which a donor impurity is atomic-plane doped and which is composed of substances such as AlGaAs, are laminated alternately onto a semi-insulating substrate 1, and two-dimensional electron gases shaped near upper and lower hetero-junction interfaces are unified. The electron supply layer 3a is made thinner than the channel layer 3b for the layer 3a, and a donor impurity is atomic-plane doped at the central position of the layer 3a in high surface concentration. Accordingly, two-dimensional electron gases shaped in each channel layer 3b (and the outside of the electron supply layer 3a on the outermost side) are brought extremely close, high electronic surface density is obtained, using the whole two-dimensional electron gases as one channel, and controllability by a gate is also improved.

Description

【発明の詳細な説明】 〔概要〕 この発明は、2次元電子ガスをチャネルとする半導体装
置にかかり、 ノンドープのチャネル層と、該チャネル層より薄くドナ
ー不純物をアトミックプレーンドーピングした電子供給
層とを交互に積層し、該チャネル層の両ヘテロ接合界面
間に一体化した2次元電子ガスを形成する構造により、 2次元電子ガスの面密度を増大し、該半導体装置の特性
を向上するものである。
[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor device using a two-dimensional electron gas as a channel, and includes a non-doped channel layer and an electron supply layer thinner than the channel layer and atomically plane-doped with donor impurities. A structure in which the two-dimensional electron gas is formed by alternately stacking layers to form an integrated two-dimensional electron gas between both heterojunction interfaces of the channel layer increases the areal density of the two-dimensional electron gas and improves the characteristics of the semiconductor device. .

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置、特に空間分離ドーピングと界面量
子化による高移動度のキャリアをチャネルとする例えば
高電子移動度電界効果トランジスタ(HEMT)等の半
導体装置の改善に関する。
The present invention relates to improvements in semiconductor devices, particularly in semiconductor devices such as high electron mobility field effect transistors (HEMTs) that use high mobility carriers as channels through spatial separation doping and interface quantization.

例えばHEMTは、2次元状態の電子が移動する領域と
不純物をドーピングする領域とを空間的に分離してキャ
リア移動度の増大を実現しており、高速デバイスとして
強い期待が寄せられているが、そのチャネル電流、伝達
コンダクタンスg、の増大などの特性向上が要望されて
いる。
For example, in HEMT, carrier mobility is increased by spatially separating the region where two-dimensional electrons move and the region where impurities are doped, and there are strong expectations as a high-speed device. There is a demand for improved characteristics such as an increase in channel current and transfer conductance g.

〔従来の技術〕[Conventional technology]

空間分離ドーピングとキャリアの界面量子化により高移
動度を実現している半導体装置の例として、HEMTの
一従来例の模式側断面図を第4図に示す。
FIG. 4 shows a schematic side sectional view of a conventional example of a HEMT as an example of a semiconductor device that achieves high mobility through spatial separation doping and interfacial quantization of carriers.

すなわちこの従来例では、半絶縁性砒化ガリ□ウム(G
aAs)基板11上に分子線エピタキシャル成長方法(
MB2法)などにより、ノンドープのi型GaAs層゛
12、これより電子親和力が小さく例えば濃度2×10
’″cta−”程度にドナー不純物がドープされたn型
砒化アルミニウムガリウム(AlxGal−XAs)層
13、これと同程度以上の不純物濃度のn型GaAs層
14を積層成長している。
That is, in this conventional example, semi-insulating gallium arsenide (G
aAs) On the substrate 11, a molecular beam epitaxial growth method (
MB2 method) etc., a non-doped i-type GaAs layer 12, which has a smaller electron affinity than this, for example at a concentration of 2×10
An n-type aluminum gallium arsenide (Al x Gal -

このn型AlGaAs電子供給層13からi形GaAs
層12へ遷移した電子によってヘテロ接合界面近傍に2
次元電子ガス12eが形成され、ゲート電極16による
ショットキ空乏層で2次元電子ガス12eの面密度Ns
を制御してトランジスタ動作が行われるが、2次元電子
ガス12eは不純物散乱による移動度低下が殆どなく、
格子散乱が減少する例えば77に程度以下の低温におい
て最も高い移動度が得られる。
From this n-type AlGaAs electron supply layer 13 to i-type GaAs
2 near the heterojunction interface due to the electrons transferred to layer 12.
A two-dimensional electron gas 12e is formed, and the two-dimensional electron gas 12e has an areal density Ns in a Schottky depletion layer formed by the gate electrode 16.
The transistor operation is performed by controlling the two-dimensional electron gas 12e, but there is almost no decrease in mobility due to impurity scattering,
The highest mobility is obtained at low temperatures, such as 77°C or lower, where lattice scattering is reduced.

この構造において、n型AlGaAs電子供給層13と
i形GaAsチャネル層12との伝導帯のエネルギー準
位差が少ない場合には2次元電子ガス12eの面密度N
sが小さくなる。従って伝導帯の準位差を0゜24eν
程度以上、即ちn型A1gGat−xAs電子供給層1
3のAI組成比Xを0.3程度以上とすることが望まし
いが、他方においてこの^1組成比Xが0.25程度よ
り大きいときには、ドープしたSi等のドナー準位が急
激に深くなってドーピング濃度n、を増加しても高いキ
ャリア濃度が得られず、加えて結晶性が劣化するために
、 ドーピング濃度nD=2X10’ ” am−”程
度が上限であり、このとき2次元電子ガス12eの面密
度Ns#9.0X10”am−”、電子移動度島−3X
10’C11”/V、!11程となっている。
In this structure, when the energy level difference in the conduction band between the n-type AlGaAs electron supply layer 13 and the i-type GaAs channel layer 12 is small, the areal density of the two-dimensional electron gas 12e is N
s becomes smaller. Therefore, the level difference in the conduction band is 0°24eν
above, that is, n-type A1gGat-xAs electron supply layer 1
It is desirable that the AI composition ratio X of 3 is about 0.3 or more, but on the other hand, when this^1 composition ratio X is larger than about 0.25, the donor level of doped Si etc. becomes deep rapidly. Even if the doping concentration n is increased, a high carrier concentration cannot be obtained, and in addition, the crystallinity deteriorates. areal density Ns#9.0X10"am-", electron mobility island-3X
10'C11"/V, about !11.

2次元電子ガスの面密度Nsをこの限界以上に増大する
目的の種々の構造改善が既に提供されている。その1例
として厚さLoam程度以下のi形GaAsチャネル層
の上下にn型AlGaAs電子供給層を設ける構造があ
るが、この構造では電子移動度μ7の低下が避けがたく
、電子面密度Nsの増加も多くない。
Various structural improvements have already been proposed aimed at increasing the areal density Ns of the two-dimensional electron gas beyond this limit. One example is a structure in which n-type AlGaAs electron supply layers are provided above and below an i-type GaAs channel layer with a thickness of about Loam or less, but in this structure, a decrease in electron mobility μ7 is unavoidable, and the electron surface density Ns is There is not much increase either.

また他の例としてi形GaAsチャネル層−n型AlG
aAs電子供給層を複数段同一方向に重ねる構造がある
が、この構造ではチャネル層間が電子供給層のために広
く隔てられてゲート電圧−ドレイン電流特性に非線型性
が現れる。
As another example, an i-type GaAs channel layer-n-type AlG
There is a structure in which a plurality of aAs electron supply layers are stacked in the same direction, but in this structure, the channel layers are widely separated by the electron supply layer, and nonlinearity appears in the gate voltage-drain current characteristic.

上述の各構造ではn型電子供給層の不純物を通常の一層
ドーピングとしているのに対し、アトミックスレーンド
ーピング法により電子面密度Nsを増加させる構造があ
る。すなわち例えば、ノンドープA1.、 、G6.、
 、As層のGaAsチャネル層とのへ、テロ接合界面
から4nmの位置に14面濃度N、、= 4 X10”
elm−”のSiアトミックプレーンドーピングを行っ
て、2次元電子ガスの面密度はNs;1.lX10”C
11−”程度が得られている。
In each of the above-mentioned structures, the n-type electron supply layer is doped with impurities in a normal manner, whereas there is a structure in which the electron surface density Ns is increased by an atomic lane doping method. That is, for example, non-doped A1. , ,G6. ,
, between the As layer and the GaAs channel layer, there is a 14-plane concentration N, 4 nm from the telojunction interface, = 4 X10''
elm-'' Si atomic plane doping, the areal density of the two-dimensional electron gas is Ns; 1.1X10''C
About 11-'' was obtained.

〔発明が解決しようとする問題、点〕[Problem or point that the invention attempts to solve]

上述の如〈従来のHEMTの2次元電子ガス面密度Ns
に制約があり、この制約を越える高面密度を得る努力が
重ねられているが、伝達コンダクタンスga、チャネル
電流等の特性を一層向上するために1濃密度Nsを更に
増大することが強く要望されている。
As mentioned above, the two-dimensional electron gas areal density Ns of conventional HEMT
Although efforts are being made to obtain a high areal density that exceeds this constraint, there is a strong desire to further increase the concentration Ns in order to further improve characteristics such as transfer conductance ga and channel current. ing.

〔問題点を解決するための手段〕[Means for solving problems]

前記問題点は、ノンドープの第1の半導体層と、該第1
の半導体層より薄くかつ電子親和力が小さく、ドナー不
純物をアトミックプレーンドーピングした第2の半導体
層とが交互に積層され、該第1の半導体層の両ヘテロ接
合界面間に一体化した2次元電子ガ不が形成される本発
明による半導体装置により解決される。
The problem is that the non-doped first semiconductor layer and the first
A second semiconductor layer, which is thinner and has a lower electron affinity than the first semiconductor layer and is doped with donor impurities in an atomic plane, is alternately laminated to form a two-dimensional electron layer integrated between both heterojunction interfaces of the first semiconductor layer. This problem is solved by a semiconductor device according to the present invention in which defects are formed.

〔作 用〕[For production]

本発明によれば第1図のエネルギー図に例示する如く、
ノンドープの例えばGaAsからなるチャネル層3bと
、ドナー不純物をアトミックプレーンドーピングした例
えばAlGaAsからなる電子供給N3aとを交互に積
層する。
According to the present invention, as illustrated in the energy diagram of FIG.
Channel layers 3b made of non-doped GaAs, for example, and electron supply layers N3a made of AlGaAs, for example, doped with donor impurities in an atomic plane are alternately stacked.

ただしチャネル層3bの厚さは例えば10nm程度以下
として、上下のヘテロ接合界面近傍に形成される2次元
電子ガスを一体化する。なお電子のサブバンドを過度に
離散させないために例えば5 nm程度以上とすること
が望ましい。
However, the thickness of the channel layer 3b is set to, for example, about 10 nm or less to integrate the two-dimensional electron gas formed near the upper and lower heterojunction interfaces. Note that in order to prevent electron subbands from being excessively dispersed, it is desirable to set the thickness to about 5 nm or more, for example.

また電子供給層3aはこのチャネル層3bより薄く例え
ば4am程度とし、通常その中心位置に、例えばSiな
どのドナー不純物を高い面濃度N、にアトミックプレー
ンドーピング(PD)する。
The electron supply layer 3a is thinner than the channel layer 3b, for example, by about 4 am, and is usually atomic plane doped (PD) with a donor impurity such as Si at a high surface concentration N at the center thereof.

この構成により、各チャネル1J3b (並びに最外側
の電子供給N3aの外側)に形成される2次元電子ガス
は極めて近接し、その全体を一つのチャネルとして高い
電子面密度N、が得られ、かつゲートによる制御性も良
好である。
With this configuration, the two-dimensional electron gas formed in each channel 1J3b (and outside the outermost electron supply N3a) is very close to each other, and a high electron surface density N can be obtained by using the entire channel as one channel. The controllability is also good.

〔実施例〕〔Example〕

以下本発明を実施例により具体的に説明する。 The present invention will be specifically explained below using examples.

第2図は本発明の実施例の模式側断面図、第3図はその
チャネル領域の模式図である。
FIG. 2 is a schematic side sectional view of an embodiment of the present invention, and FIG. 3 is a schematic diagram of its channel region.

本実施例の半導体基体は、半絶縁性GaAs基板1上に
下記の各半導体層を順次積層してエピタキシャル成長し
ている。先ず2は厚さが例えば0.5〜11rm程度の
ノンドープのGaAs層である。
The semiconductor substrate of this example is epitaxially grown by sequentially laminating the following semiconductor layers on a semi-insulating GaAs substrate 1. First, 2 is a non-doped GaAs layer having a thickness of, for example, about 0.5 to 11 rm.

3aは電子供給層で、厚さ例えば4am程度のA1.。3a is an electron supply layer, which is A1.3a having a thickness of, for example, about 4 am. .

3Gao、 、AsNの中央に面濃度Nus#4 XI
O”cm−”のSiアトミックプレーンドーピング(S
i−PD)を行っている。
3Gao, , surface concentration Nus#4 XI in the center of AsN
Si atomic plane doping (S
i-PD).

3bはチャネル層で厚さ例えば7am程度のノンドープ
のGaAs層であり、本実施例では3層の電子供給層3
aと2層のチャネル層3bとを交互に積層している。
Reference numeral 3b denotes a channel layer, which is a non-doped GaAs layer with a thickness of, for example, about 7 am.
A and two channel layers 3b are alternately stacked.

また4はノンドープのGaAs層で厚さ例えば nm程
度とし、5はn型GaAsキャップ層で、Siを濃度n
B = 2×lQI8cm−3程度に一様にドーピング
している。
Further, 4 is a non-doped GaAs layer with a thickness of, for example, about nm, and 5 is an n-type GaAs cap layer with Si at a concentration of n.
It is doped uniformly to about B=2×lQI8cm−3.

この半導体基体では2次元電子ガスが2層のGaAsチ
ャネル層3b、並びにGaAs層2.4それぞれの電子
供給層3aとのヘテロ接合界面近傍に生成され、全体の
面密度はNs#2.0X1012cm−2が得られてい
る。
In this semiconductor substrate, two-dimensional electron gas is generated near the heterojunction interface between the two GaAs channel layers 3b and the electron supply layer 3a of each of the GaAs layers 2.4, and the overall areal density is Ns#2.0×1012 cm− 2 is obtained.

この半導体基体のn型GaAsキャップ層5上にソース
・ドレイン電極5 、GaAs層4上にゲート電極7を
配設した本実施例について、例えば伝達コンダクタンス
g −目00m5/msが得られて、例えば第4図の従
来例の構造で、2次元電子ガスの面密度N5=9.0X
10”ロー2の半導体基体を用いゲート電極の構造、寸
法等が等しい比較試料では、伝達コンダクタンスがg 
va #235m5/mm程度であるのに比較して大幅
に向上している。
In this embodiment, in which a source/drain electrode 5 is disposed on the n-type GaAs cap layer 5 of this semiconductor substrate, and a gate electrode 7 is disposed on the GaAs layer 4, a transfer conductance g-th 00 m5/ms is obtained, for example. In the conventional structure shown in Fig. 4, areal density of two-dimensional electron gas N5 = 9.0X
In a comparison sample using a 10" row 2 semiconductor substrate and having the same gate electrode structure and dimensions, the transfer conductance was g
va #235m5/mm, which is a significant improvement.

以上の説明はGaAs / A lGaAs系HEMT
を対象としているが、本発明はこれに限られるものでは
なく半導体材料が異なり、或いは構造に差異がある半導
体装置についても、本発明により同様の効果を得ること
ができる。
The above explanation is based on GaAs/AlGaAs HEMT.
However, the present invention is not limited thereto, and similar effects can be obtained by the present invention even for semiconductor devices that are made of different semiconductor materials or have different structures.

〔発明の効果〕〔Effect of the invention〕

以上説明した如(本発明によれば、空間分離ドーピング
と界面量子化による高移動度のキャリアをチャネルとす
るHEMT等の半導体装置の2次元電子ガス面密度Ns
、伝達コンダクタンスg1の増大などの改善が達成され
、高速デバイスとして大きい期待が寄せられているこの
半導体装置の進歩に大きい効果が得られる。
As explained above (according to the present invention, the two-dimensional electron gas areal density Ns
, an increase in transfer conductance g1, and other improvements have been achieved, resulting in a significant effect on the advancement of this semiconductor device, which has great expectations as a high-speed device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による半導体装置の1例のエネルギー図
、 第2図は実施例の模式側断面図、 第3図は実施例のチャネル領域の模式図、第4図は従来
例の模式側断面図である。 図において、 1は半絶縁性GaAs基板、 2はノンドープのGaAs層、 3aはSiをアトミックプレーンドーピングしたAlG
aAs電子供給層、 3bはノンドープのGaAsチャネル層、4はノンドー
プのGaAs層、 5はn型GaAsキャップ層、 6はソース、ドレイン電極、 7はゲート電極を示す。 −!′Jのエネルヘ゛−口 早 j 図 実施列の糎へ刊゛1j闇屓幻 チ 2 口 亥〕七rJのチで享ル劇吋戊へ慢バ■口早 3 g (Lヲliブリの孝麺へ/1嬰jさ工丁雨)酉]午 4
 口
Fig. 1 is an energy diagram of an example of a semiconductor device according to the present invention, Fig. 2 is a schematic side sectional view of the embodiment, Fig. 3 is a schematic diagram of the channel region of the embodiment, and Fig. 4 is a schematic side view of the conventional example. FIG. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an undoped GaAs layer, and 3a is an AlG layer with atomic plane doping of Si.
3b is a non-doped GaAs channel layer; 4 is a non-doped GaAs layer; 5 is an n-type GaAs cap layer; 6 is a source and drain electrode; 7 is a gate electrode. -! 'J's energy - fast-talking j Published on the diagram implementation column's glue 1j Dark side phantom 2 Mouth pig] 7rJ's ji to play the play 劊 arrogant 3 g (Lwoli Buri no filial piety To the noodles / 1.
mouth

Claims (1)

【特許請求の範囲】 ノンドープの第1の半導体層と、 該第1の半導体層より薄くかつ電子親和力が小さく、ド
ナー不純物をアトミックプレーンドーピングした第2の
半導体層とが交互に積層され、該第1の半導体層の両ヘ
テロ接合界面間に一体化した2次元電子ガスが形成され
ることを特徴とする半導体装置。
[Claims] A non-doped first semiconductor layer and a second semiconductor layer which is thinner and has a lower electron affinity than the first semiconductor layer and which is atomically plane-doped with donor impurities are laminated alternately, A semiconductor device characterized in that an integrated two-dimensional electron gas is formed between both heterojunction interfaces of one semiconductor layer.
JP61143638A 1986-06-19 1986-06-19 Semiconductor device Pending JPS63172A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61143638A JPS63172A (en) 1986-06-19 1986-06-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61143638A JPS63172A (en) 1986-06-19 1986-06-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63172A true JPS63172A (en) 1988-01-05

Family

ID=15343422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61143638A Pending JPS63172A (en) 1986-06-19 1986-06-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63172A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05198600A (en) * 1991-08-21 1993-08-06 Hughes Aircraft Co Manufacture of inversion modulation-doped hetero-structure
JP2016512927A (en) * 2013-03-14 2016-05-09 ノースロップ グラマン システムズ コーポレイションNorthrop Grumman Systems Corporation Superlattice relief gate field effect transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05198600A (en) * 1991-08-21 1993-08-06 Hughes Aircraft Co Manufacture of inversion modulation-doped hetero-structure
JP2016512927A (en) * 2013-03-14 2016-05-09 ノースロップ グラマン システムズ コーポレイションNorthrop Grumman Systems Corporation Superlattice relief gate field effect transistor

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