JPS6319774B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a combustion control device equipped with a timer circuit that gives a pre-purge time, when a pseudo flame is detected within the pre-purge time, the operation of the timer circuit is stopped, and the pseudo flame is extinguished. This invention relates to a simulated flame check circuit that is applied to perform a check that prevents the operation of a timer circuit from restarting even in some cases.

If the flame detector detects a false flame during the pre-purge operation that takes place prior to ignition of the combustor, the main fuel supply system will operate due to the false flame signal after the pre-purge time is completed and a large amount of fuel will be generated. There is a risk that a serious malfunction may occur in which unignited fuel is released.

This invention provides a false flame check circuit that immediately stops the operation of a timer circuit for providing a pre-purge time and prevents the control sequence for ignition from proceeding if a false flame is detected within the pre-purge time. is intended to provide.

The operation of the digital combustion control device of the present invention will be explained below with reference to the drawings.

FIG. 1 shows a combustion integrated control device that performs basic control sequence operations that are commonly used in various combustion control devices. Note that, in addition to the safety switch section and load relay drive section, devices to be connected to this integrated control device, such as a flame detection circuit or a thermostat starting switch, are not shown in the figure. Further, various connections can be considered for the blower, valve, pump, igniter, etc. controlled by the load relay, and an example thereof is shown in FIG. 2, and its operation will be described later.

In the figure, reference numeral 10 denotes a state determination circuit, which detects an output signal from a thermostat or manual start switch (not shown), that is, a heat request signal 11, and an inverted flame signal 13, which is an inversion of the output signal from a flame detection circuit (not shown). , AND gate 14 described later
NAND with output 16 and three signals as input
A gate 15 is provided. Here, the heat request signal 11 outputs "1" when there is a heat request and "0" when there is no heat request, and on the other hand, the flame detection circuit outputs "1" when there is a flame and "0" when there is no heat request. ”, so the inverted flame signal 13 is “0” when there is flame.
When there is no , "1" is given to the input of NAND15. On the other hand, the output of the OR gate 18 which inputs the inverted flame signal 13 and the signal 20 indicating the pre-purge signal M3, and the output of the NAND gate 15 mentioned above are applied to another NAND gate 17, from which the state discrimination logic is applied. It outputs the output of the circuit. Reference numeral 28 denotes a clock generation circuit which generates two clock signals: a clock 1 pulse from a commercial AC power source 29, and a clock 2 pulse from the clock 2 through a frequency divider 27. The clock 2 synchronizes the timing at which the heat request signal from the start switch is supplied to the control device, so that the safety switch circuit 21 operates at regular timing.

The safety switch circuit 21 includes a transistor _Q1 ,
It consists of a safety switch load connected between its collector and the power supply. A safety switch load is a heat driven load of a timed interval shutoff switch, such as an instantaneous shutoff switch or a thermally responsive switch. On the other hand, in order to sense the switch state of the transistor 23, a NAND gate 27 is provided which receives both the collector 25 of the transistor 23 and a state sensing signal _C1 from a first timer circuit, which will be described later.
Its output is input to an SR flip-flop 31 which acts as a latch circuit. This latch circuit 31 is given the clock 1 signal synchronized with the above-mentioned power supply commercial frequency, and its output is sent via a NOT gate 32 to an AND gate 33, and then to an output IN.
2 to another latch circuit 17.
The output of the AND gate 27 is directly applied to the AND gate 33, and the output of the AND gate 33 is
latch or memory circuit M1. On the other hand, an AND gate 37 is provided which receives the output of the AND27, a memory output 34, and a memory output 39 of another memory circuit M3, which will be described later. The transistor 7 of the provided load relay drive circuit 70
1 and relay 75 are opened and closed. Furthermore, the output 34 of the memory circuit M1 and the output 3 of the memory circuit 56
Another AND gate 35 which receives the inverted output 3 of 9 is provided, and another latch circuit, that is, a memory circuit 36 is also provided on the output side of this AND gate 35, from which the combustion fan motor drive is output. and the transistor 7 of the load relay drive circuit 70
2 and relay 76 are energized.

On the other hand, the output IN2 of the NOT circuit 32 is applied to the latch circuit 17, and the output of the AND gate 18 whose inputs are the output of the latch circuit 17 and the clock 2 is applied to each S-R flip-flop of the first timer circuit 40. Given.

On the other hand, the first
The timer circuit 40 receives both the input of the memory output 2 indicating the fan motor drive state via the NOT gate 42 and the time setting terminal TP input. A "0" signal is supplied to a timer circuit in which 42 are connected in cascade, and a "0" shift register is configured by the clock 2 signal.
It is connected to the input of gate 14 to form a first timer circuit. Here, the NAND gate 41 outputs "0" in a pulsed manner only during the first shift operation of the flip-flop 42 at the first stage, and thereafter maintains the output state of "1".
On the other hand, an interstage gate circuit 43 composed of a NOT gate 44 and a NAND gate 45 is connected to the output of each stage of the flip-flop 42, and the NAND gate 45 of each interstage gate circuit 43 has an inverted flame signal is applied. Final stage flip
The output F ₁ n of the flop 42 is not only supplied to the AND gate 14 but also to the AND gate 2 described above.
The second timer circuit 5 can also be used as input C ₁ of 7, and further secures the next stage ignition trial timing.
It also serves as a 0 input signal. Further, the second timer circuit 50 performs almost the same timer operation as the first timer circuit 40, but the first stage flip-flop 51
A pseudo flame latch circuit 52 is provided only to the output of the circuit, and is not provided in the subsequent stages. The flip-flop circuit of the second timer circuit 50 is a conventional S-R flip-flop circuit.
A flip-flop may also be used, but since a fail-safe flip-flop circuit is used here, a flip-flop 51 to which clock 2 is applied via a NOT gate 53,
Flip added without going through NOT gate 53
Flops 51' are connected alternately, and the first
Similar to the timer circuit 40, the output of each stage is applied to the input of the AND gate 14.

On the other hand, the input signal of the final stage flip-flop 42 of the first timer circuit and the final stage flame latch circuit 45
An AND gate 55 is provided, which receives the output signal of the NOT gate 44 and the output signal of the first stage flip-flop 51 of the second timer circuit, respectively. I'm letting you do it. That is, in the AND gate 55, the output data F _1(o-1) of the flip-flop located one stage before the final stage,
The three logic value array patterns of the output data F _1o of the final stage flip-flop and the output data F ₂₁ of the flip-flop located one stage after the final stage are as follows:
(“1”, “0”, “1”), it is determined that the prepurge timer 40 has timed up. Therefore, as described later, when the pseudo flame signal becomes "0", the above-mentioned
The array pattern of F _1(o-1) , F _1o , F ₂₁ is always (“1”,
1, 1), the prepurge timer will no longer time up. This memory circuit 5
6, it is determined whether or not the pre-purge timing has ended.

Furthermore, each flip-flop output of the first and second timer circuits is connected to the input of the AND gate 14, and the output is added to the gate 16 only when these inputs are all "1".

The output of the AND gate 14 is the NAND
15, and is also connected to a third timer circuit 60 for providing pilot-only timing, ie, pilot stabilization time, at the next stage. That is, the flame signal 13' (not inverted) indicating that a flame has been established, and the AND gate output 1.
6 and a pre-purge end signal 39 as inputs, a plurality of cascade-connected S-R flip-flops 62 are driven by the clock 2, and a NOT gate 63 drives the second valve, etc. The output V2 is applied to energize the transistor 73 and relay 77 of the load relay drive circuit 70.

Reference numeral 80 is a recycle/non-recycle setting circuit, which is used to set "recycle/non-recycle" through the external set terminal 85 when it is desired to cause the control device to perform a recycle operation, that is, when it is desired to automatically perform the ignition sequence again even after the flame has been extinguished. When you want to perform non-recycle operation, give "0". In addition, the outputs M1 and M2 of the two memory circuits 34 and 36 are input to an OR gate 83, and the output thereof is read out to the S-R flip-flop 82 as an inverted flame signal 13, and the output of the flip-flop 82 and an external set signal 85 are read out. and the output 84 of the AND gate 81 which receives the pre-purge timing signal M3 as input,
When carrying out the recycling operation, each latch circuit, that is, the memory circuits M1, M2, M4 and M5 are reset, and the control device is returned to a restartable state.

Next, the operation of such a configuration will be explained together with the operation of the load drive circuit shown in FIG. 2 as an example.

Figure 2 shows the fan motor 2, pilot valve 3,
This is a load drive circuit for a gas burner in which an igniter 4 and a main valve 5 are shown with well-known connections. In addition, the first
Using the load relay drive circuit shown in the figure, various known load drive circuits for oil burners can also be controlled by this control device, but here, explanation will be given using the most common connection example for gas combustor. do.

First, assume that all gate circuits are powered and energized, that there is no flame in the burner, and that there is no heat demand on the start switch or thermostat. At this time, AND gate 1 is output from the first and second timer circuits 40 and 50.
Since a signal of "1" is applied to all input terminals of the AND gate 14, the output of the AND gate 14 is "1".

Therefore, the NAND gate 15 of the state discriminating circuit 10 is set to ="1" indicating that there is no flame.
and the output "1" of the AND gate 14 are applied. In this state, the output of the NAND 17 is "0", the transistor Q1 of the safety switch drive circuit 21 is not energized, and the first timer circuit 40 is also not energized, so the final stage F-F
A signal of C1="1" from 42 and a signal "1" indicating that the safety switch circuit 21 is not energized are output.
It is applied to the AND gate 27, its output "1" is given to the SR flip-flop 31, and the output of the NOT gate 32 is held at "0", and the operations of the first and second timer circuits are stopped. For this reason,
The outputs of latch circuits 34 and 36 are both "0".

When the thermostat outputs a heat request signal "1" in such a state, the NAND
A heat request signal “1” is applied to the gate 15. Then, the output of the NAND gate 15 changes from "1" to "0", the output of the NAND gate 17 changes from "0" to "1", and the output of the AND gate 27 becomes "0" at its input terminal 25. Therefore, set the output to “0”. Therefore, the flip-flop 31 reads this "0" and inverts the IN2 of the inverter 32.
The output is set to "1", but since "0" is given to the other inputs of the AND gate 33, there is no change after that AND gate 33. However, since the inverter output "1" is given to the latch circuit 17, the AND gate 1 applied together with the clock 2
8, the clock 2 is directly transmitted from the output to each flip-flop 42, 51 of the first and second timer circuits.
is applied to Therefore, upon application of the first clock 2, the first stage SR flip-flop 42 of the first timer circuit receives the "0" output from the NAND gate 41. Since the inverted flame signal "1" is applied to the interstage gate circuit 43, a "0" output is applied to the AND gate ₁₄ at the first stage F11 of the output terminal 46 thereof.

The above operations are performed simultaneously when the heat request signal 1 and the clock 2 operate the NAND gate 15 in synchronization. Clock 1 here is a pulse generated from an AC power source by a clock generator 28 with a frequency of approximately 100 Hz, which is twice the frequency of the AC power source, but clock 2 is generated by a clock generator 28.
This frequency is divided to generate a pulse of about 1 second. Therefore, the pulse of clock 1 causes instantaneous
The output 16 of the AND gate 14 is from “1” to “0”
This "0" signal means the start of the prepurge operation. This "0" signal is applied to the NAND gate 15, so the NAND gate 15
The output of the NAND gate 17 becomes "1", the output of the NAND gate 17 becomes "0", and the output of the AND gate 27 becomes "1" again. Therefore, two "1" signals enter the AND gate 33, so the memory circuit 34 is latched to "1" for the first time at this point, and the "1" signal is applied to the AND gate 35. The AND gate 35 also has an inverted output 3= of the memory circuit 56 indicating that the prepurge timing has not yet been completed.
Since "1" is added, the memory circuit 36 is also latched to "1". Therefore, the signal that drives the fan motor 2 (Fig. 2) from the integrated control device is
It is output from the M output terminal, drives the relay 1R, and starts the operation of the fan motor 2.

In this way, as soon as the heat request signal "1" is applied to the state determination circuit 10, the memory circuits M1 and M2
The safety switch drive circuit 21 is operated for an instantaneous time determined by the clock 1 without being driven, and the latch circuit 31 is further provided, and the first and second timer circuits 40 and 50 are operated starting with the next clock 1. , the safety switch drive circuit 21 inverts the output of the NAND gate 15 of the state determination circuit 10 again by looking at the operation of the AND gate 14.
That is, this is particularly for checking whether the transistor 23 is functioning normally. That is, the output of the AND gate 27 changes from “1” to “0” to
If the one-cycle operation of "1" is not performed, the pre-purge operation will not start and the fan motor 2 will not be driven, and especially in this embodiment, when the conduction failure of the externally connected transistor 23 occurs, the safety switch is shut off. . Furthermore, during this one-cycle operation,
Transistor 23 is activated for an instantaneous time determined by the pulse timing of clock 1, at which time a normal safety shut-off switch of any type would not be pulled in. Although this embodiment shows the operation check of only the safety switch circuit, it is also possible to check the operation of the load relay drive circuit.

Now, the output of the discrimination circuit 10 mentioned above is "1"
→ After the cycle operation of “0” → “1”, contact 1R1 of relay 1R in Fig. 2 is closed, so only the fan motor operates, and after that, the first and second
Timer circuits 40 and 50 operate sequentially. 1st
Approximately 1 for each flip-flop 42 of timer circuit 40
Since clock pulses 2 with an interval of seconds are given,
The "0" signal from the output F ₁₁ sends "0" to the next stage F ₁₂ , and is sequentially shifted to the next stage flip-flop with the next clock pulse 2. For this reason
Since a “0” signal is applied to one of all inputs of the AND gate 14, the output of the AND gate 14 is
This indicates that the flip-flop 42 or 51 of either the first or second timer 40 or 50 is in the timing operation. Prepurge period ends and output
When a "0" signal is shifted to F _1o 47, all three input signals of AND gate 55 become 1, so that memory circuit 56 is latched to "1". However, since the pulse of clock 2 is also constantly applied to flip-flop 51, the final output _F1o is subsequently supplied to the second timer circuit for ignition trial timing.
The outputs F ₂₁ , F ₂₂ , . . . F _2n of the flip-flop 51 are successively shifted to “0”.

On the other hand, at the same time that the memory circuit 56 is latched to "1", this output M3 (=1) is applied to the input of the AND gate 37. Since the other inputs 48 and 49 of the AND gate 37 are applied with a signal "1" indicating that the motor output is energized and that the safety switch is normal, the output of the AND gate 37 is is inverted to "1" and energizes transistor 71 and relay 2R.

As shown in FIG. 2, the pilot valve 3 is energized and the ignition device 4 is activated simultaneously via the flame detection circuit output relay contacts F, C, and 6 in advance outside the integrated control device.

Here, if a flame is established in the combustor, a flame detector (not shown) detects the flame, inverts the relay contact FC6, and sends a signal of inverted flame signal = 0 to the state determination circuit 10 to the NAND gate 15. Apply. However, at this point, the ignition trial time has not yet been completed, so relay 3R is not energized, and the output of AND gate 14 is
Since the "0" output indicating that the second timer circuit 50 is in operation is applied to the NAND gate 15, the output of the NAND gate 17 of the state determination circuit 10 remains "0" without any change. , main valve 4
is not energized.

However, when the second timer circuit 50 times up, the AND gate 14 loses the "0" input from the flip-flop, so all inputs become "1", and a "1" signal indicating that the time has expired is output from the AND gate 14. . When this trial timing ends, the output “1” is output,
In the state determination circuit 10, =0 indicating that a flame is established is added to the NAND 15, so
There is no change in its output.

On the other hand, at this point, the AND gate 14 is “1”.
Since the output, the “1” output of the memory circuit 56, and the flame signal F=1 are applied to the NAND gate 61,
The SR flip-flop 6 of the third timer circuit 60 whose “0” output ensures the pilot-only time
This "0" signal shifts together with the pulse of the clock 2, and after a predetermined time has elapsed, a "1" signal is applied to the V2 output terminal via the NOT gate 63, energizing the relay 3R. Therefore, in FIG. 2, the main valve 5 opens via the flame relay contact 6 and the relay contact 3R1, which have already been reversed due to the establishment of the flame, and the main fuel is ignited by the pilot flame, resulting in steady combustion. Move to. This normal combustion operation sequence is shown in Figure 3a. In addition, in Figure 1,
If the output of the AND gate 14 is not applied to the NAND gate 61 and the inputs of the NAND gate 61 are the two inputs of the memory output 39 and the flame output 13', the pilot You can secure your own time.

Next, the ignition failure behavior in the ignition trial will be described. Until the ignition trial timing,
Assuming it is normal as above, AND gate 3
7 is energized, but after the ignition trial timing has elapsed, the output of the AND gate 14 is inverted from "0" to "1", so all the inputs of the NAND gate 15 become "1", and the output of the NAND gate 17 becomes "1". It is reversed to “1” and the safety cutoff drive circuit 21 is activated.
The SSW shown in Figure 2 opens and all power is cut off when used in a non-recycling manner. In addition,
When used as a recycling operation, it is not necessary to provide the safety switch driving section 24, and the cycle discrimination circuit 80 can be operated to repeat the initial sequence again. Figure 3b shows the case where the safety switch is activated.

Next, we will discuss the case where there is a pseudo flame. =
0, so the thermostat output is “1”
Since the state determination logic circuit 10 and the load latch control circuit 30 do not operate in one cycle, the control sequence does not proceed. Furthermore, if a pseudo flame occurs during prepurge, the pseudo flame signal to the interstage gate circuit 43 provided between each stage of the first timer circuit 40 becomes 0, so that the shift operation continues between any stage. The interstage gate circuit 43 eliminates the "0" signal. Therefore, the output of the AND gate 14 is
A "1" signal indicating the stop of the timer operation is issued, which drives the safety switch cutoff circuit via the discrimination logic circuit 10 to stop the sequence operation. This situation can be seen in the third
Shown in Figure c.

Also, an important point related to the present invention is that due to the action of the interstage gate circuit 43, the outputs F _{1 (o-1)} , F _o ,
F ₂₁ will always be (“1”, “1”, “1”) from now on and is a time-up pattern (“1”, “0”, “1”)
does not occur. Therefore, the pseudo flame signal is = “1”
Even if it returns to , the prepurge will not end and the operation sequence will not proceed to the next step.

As described above, according to the present invention, when a pseudo flame signal occurs during prepurge in this type of combustion control device, the operation of the prepurge timer is immediately stopped, and the combustion operation is started with the flame detector malfunctioning. Danger can be prevented.

Furthermore, according to the present invention, one "0" data corresponding to the time measurement start data is sequentially shifted, and the fact that it has been shifted to the final stage is detected by two times.
Since the determination is made based on the arrangement pattern of the output data logical values in the flip-flop, the reliability of determining the pre-purge time elapsed is high. In addition, once the "0" data is erased by the interstage gate circuit, it is possible to prevent the prepurge timer from time-up in the future, and even if the pseudo flame signal disappears, the combustion operation can be started after that. can definitely be prohibited.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a circuit diagram of a load drive circuit for a gas combustor controlled by the output of the device, and FIGS. 3a to 3c are sequence diagrams showing the operation sequence of each part of the device. DESCRIPTION OF SYMBOLS 10... State determination logic circuit, 20... Safety switch drive circuit, 30... Load control latch circuit, 40... First timer circuit, 50... Second timer circuit, 60... Third timer circuit, 70... Load relay drive circuit, 80
...Recycle/non-recycle setting circuit.

Claims (1)

[Claims] 1. In a combustion control device equipped with a shift register type prepurge timer circuit, a predetermined logical value indicating the start of time measurement is applied to the first stage flip-flop of the timer circuit only during the first shift operation in response to the arrival of the heat request signal. A timing start data set circuit that provides data is inserted between each successive flip-flop of the timer circuit, and when a pseudo flame signal does not arrive, the output data of the front-stage flip-flop is passed through as input data to the rear-stage flip-flop. , and an interstage gate circuit that prevents the output data of the front stage flip-flop from passing through so that it does not become the input data of the rear stage flip-flop in a state where the pseudo flame signal has arrived;
A time-up determination circuit is provided to determine whether the time measurement start data has been shifted to the final stage flip-flop based on an array pattern of output data logic values in two or more successive flip-flops, and once the pseudo flame signal arrives, A pseudo flame check circuit characterized in that the time-up determination circuit is configured so that a predetermined arrangement pattern corresponding to a time-up does not occur.