JPS6319909A - Adaptive digital filter - Google Patents

Abstract

PURPOSE:To increase the converging speed of a variable coefficient of each variable coefficient multiplier by securing the inputs orthogonal to each other to be supplied those variable coefficient multipliers of an adaptive digital filter. CONSTITUTION:An adaptive digital filter ADF-1 receives input of a signal P1 (k) from an input terminal 10-1 at a time point (k) and sends a signal P2 (k) to an input terminal 10-2 of an ADF-2. At the same time, the ADF-1 delivers a signal y1 (k) to an output terminal 11-1. At an ADF-M of the final stage, a signal PM(k) received from a 2nd output terminal 10-M of an ADF-(M-1) is supplied from an input terminal 10-M at the time point (k) and a signal yM(k) is delivered to an output terminal 11-M. The outputs y1(k)-yM(k) obtained at output terminals 11-1-11-M are added together by an adder 8. The result of this addition is used as the output y(k) of an ADF9 at the time point (k). Then the output y(k) is subtracted from the output y'(k) of an unknown system 3 by an adder 7 and a signal e(k) is obtained.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to an adaptive digital filter that can generate an arbitrary transfer function, and particularly relates to an adaptive digital filter that has a fast convergence speed and is suitable for application to, for example, an echo canceller. It is something.

(Prior Art) Recently, with the rapid progress of digital signal processing technology, adaptive digital filters have been developed.
1 Filter+ (hereinafter referred to as ADF) is attracting attention because of its wide range of application. A typical application example of ADF is its application to system identification. System identification means estimating the characteristics of an unknown system based on input/output data of a system whose characteristics are unknown.

FIG. 2 is a schematic diagram illustrating identification of an unknown system using ADF. In the figure, 41 is a signal input terminal, 42 is an estimation error output terminal, 43 is an unknown system, and 44 is an ADF.
, 45 is an adder. Also, x(k) is the input to the unknown system 43 and ADF 44 at time k, y(k) is the output of the unknown system 43 at time k, 9(k) is the output of ADF 44 at time k, and e(k) is The estimation error at time k, H(z) is the transfer function of the unknown system 43, and H(z) is the transfer function of the ADF 44. Consider the evaluation function J=e(k)2 with the configuration shown in Fig. 2. Then, if J=O, the characteristics of the unknown system 43 are ADF 4
4 is considered to be a correct estimate.

An echo canceller is a specific example of using the ADF as described above. This echo canceller is applied, for example, to remote conference systems, for which needs have been increasing in recent years. FIG. 3 is a diagram schematically showing a configuration when an echo canceller is applied to a remote conference system. In the same figure, 51-1.

51-2 is a microphone, 52-1.52-2 is a speaker, 53-1.53-2 is an echo canceller, 54-1
゜54-2 is a transmission line, 55-1.55-2 is ADF',
56-1 and 56-2 are acoustic coupling paths. Generally, a remote conference system uses an audio terminal in which a speaker and a microphone are integrated, as shown in FIG.

Therefore, acoustic coupling occurs between the speaker and the microphone, and as a result, the signal output from the speaker goes around to the microphone, significantly degrading the quality of the call. In the example of FIG. 3, the speaker 52-1 and the microphone 51-1
An acoustic coupling path 56-1.56-2 is formed between the echo canceller 53-1.56-2 and the microphone 51-2 and the microphone 51-2.
By providing 2, it is possible to eliminate a wraparound signal from the speaker to the microphone.

As the ADF of the above-mentioned echo canceller, ADH' as shown in Fig. 4 was conventionally used (
For example, ``1985 IEICE Information and Systems Division National Conference 4.366, p2-107).

In FIG. 4, this ADF is composed of M basic sections (M is an integer of 1 or more). One basic interval is M
Except for the th basic interval, the second-order cyclic digital filter F1 (having delay elements 62-1 and 63-1 of one unit time), the second-order acyclic digital filter F2 and 1
It is configured to include a second-order acyclic digital filter F3. The second-order acyclic digital filter F2 has a zero point at a position that is a mirror image of the unit circle of the second-order cyclic digital filter. The M-th basic section includes a second-order cyclic digital filter and a first-order acyclic digital filter. The first output OUT 1 of each of the M basic intervals is connected to the adder 640 input;
The output of 4 becomes the output of the ADF.

The second output OUT 2 of each basic section from the first to the (M-1)th is connected to the input of the next stage.

Further, the input of the first basic section becomes the input of the ADF.

In the ADF configured in this way, each variable coefficient is Pt*Qt t p2*q2 + ""e PM
Variable coefficient multiplier 60-1.61-1 with e qM
．． 60-2.61-2. ..., each input signal φ1(k) to 60-M, 61-M.

φs (k-1) *φ2 (k) tφ2 (k-1
) t..., φM(k), and φM(k-1), the following relationship holds true.

φ1(k)φt(k) =φ1(k-1)φt(k)
=φ1(k)φt(k-1) where i=:l, 2.・
..., M; t=1,2. ..., M:i)t, □ indicates an averaging operation for time k.

That is, the inputs to the variable coefficient multipliers between ADF-i and ADF-2 are orthogonal to each other.

(Problems to be solved by the invention) However, in the conventional ADF as shown in FIG.
As shown in the following equation, φ, (k) φ1 (k-1) lol (where i=l, 2.
..., M) ... (2) Input signal φ1(k) of variable coefficient multiplier 60-i and input signal of variable coefficient multiplier 61-1 in each basic interval.

The average value of the product with φ1(k-1) is not O, and furthermore, it is not equal to the respective root mean square values of the input signals φ1(k)-φ2(kL..., φM(k)).

φ, (k) lol φt (k) (however, i lol t)...
・(3) Therefore, the variable coefficient Pt *q1 *Pz yQ2 t
...# pMp (There was a problem that the convergence speed of 1M was slow.

The present invention solves the problems of the conventional ADF described above,
It is an object of the present invention to provide an ADF in which variable coefficients of a variable coefficient multiplier converge quickly.

(Means for solving the problem) According to the present invention, M basic sections (M is an integer of 1 or more) are connected in cascade, and each basic section up to the (M-1)th cascade connected at the beginning is has an input terminal, a first output terminal, and a second output terminal, while the Mth elementary section has an input terminal and a first output terminal, and the input terminal of the first elementary section has an input terminal of the adaptive digital terminal. A signal input terminal of the filter is configured, and the input terminal of each basic interval from the second to the Mth is connected to the second output terminal of the immediately preceding basic interval, and the signal is obtained at the first output terminal of each basic interval. The target is an adaptive digital filter whose output is the sum of signals.

The present invention provides a first adaptive digital filter.
Then, the path from the input terminal of each of the M basic sections to the first output terminal is connected to a first multiplier, a second-order cyclic digital filter, and a zero-order acyclic input of the second-order cyclic digital filter. It is constructed by cascading a first-order acyclic digital filter connected to the circuit.

Second, the path from the input terminal to the second output terminal of each basic interval from the first to the (M −1)th
The multiplier, the second-order cyclic digital filter, and the second-order acyclic digital filter are connected in cascade.

Third, the first-order acyclic digital filter of each m-th (1≦m≦M) basic interval is multiplied by the coefficient Rm by the signal um(k) input thereto by a second multiplier. The first adder adds the signal and the signal um(k-1) from one unit time ago, the output is multiplied by the coefficient Srn in the third multiplier, and the output ■m(k) is added to the first adder. The signal dm (k )um (k
) and a signal em(k) m(k) obtained by multiplying the signal um(k) by a variable coefficient cm(k) in a second variable coefficient multiplier.
The configuration is such that a second adder adds these.

Fourth, the coefficient Qm of the first multiplier is expressed as the root mean square value of the signal at the cascade connection point of the second-order cyclic digital filter, the filter, and the second-order acyclic digital filter. is determined to be equal to the root mean square value of the signal of the cascade connection points.

Fifth, the coefficient Rm of the second multiplier is set to the signal um(
, k ) and m(k) are determined to be orthogonal.

Sixthly, the coefficient Sm of the third multiplier is calculated from the root mean square value of the signal m(k) and 2 of the signal um(k).
Determine so that the root mean values are equal.

(Operation) Input signal p+ supplied to the input terminal of the first basic section
(k) is output to the second output terminal through the first multiplier, the second-order cyclic digital filter, and the second-order acyclic digital filter. The signal p2(k) output from this second output terminal is supplied to the input terminal of the second basic section, and is output to the output terminal in the same manner as the first basic section. Thereafter, operations are performed in the same manner, and the signal PM(k) is output from the second output terminal of the (M-1)th basic section and input to the Mth basic section.

On the other hand, the input signal PI(k) supplied to the input terminal of the first basic section passes through the first multiplier, the second-order cyclic digital filter, and the first-order acyclic digital filter, and then is sent to the first output terminal. A signal y1(k) is output. Similarly 2
p2(k) supplied to the input terminal of the th basic interval is outputted to the first output terminal as a signal 72(k).

Similarly, y3(kL...-yM(k)) is obtained from the first output terminal of the basic sections up to the Mth. These signals yl(k) e yz(k) *...pyH( k
) are added and become the output of the digital filter.

Here, in the present invention, the first to third multipliers are provided as described above, and these coefficients Qm'Rm and Sm
is set as above, so firstly, the root mean square value of the signal at the cascade connection point of the 2nd order cyclic digital filter and the 2nd order acyclic digital filter is the same as that of the corresponding cascade connection point of the other basic sections. secondly, in each elementary interval the inputs to the first and second variable coefficient multipliers are orthogonal; and thirdly, the two of these inputs are
The root mean values will be equal.

Therefore, the above problem is solved.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIGS. 1(a) to 1(c) are diagrams showing the configuration of an embodiment of the present invention, FIGS. 1(a) to 1(c) are block diagrams showing the basic configuration of this embodiment, and FIG. ADF-m in (,) (m
'5M), and (C) of the same figure is a circuit diagram showing the configuration of the ADF-M in (a) of the same figure.

First, the basic configuration of this embodiment will be explained with reference to FIG. The ADF' according to this embodiment is indicated by a dashed block indicated by reference numeral 9. ADF
9 has a configuration in which ADH'-1, ADF-2°, . . . , ADF-(M-1), and ADF-M are connected in cascade. In ADF'-1, the signal pt(k) (=x(
k) : This x(k) is the input signal of the ADF 9 according to this embodiment supplied from the input terminal 1) is input, and at the same time, the input terminal 1O-2 of the ADF-2 (this is
From the perspective of ADF-1, this is an output terminal; hereinafter, this output terminal will be referred to as the second output terminal).At the same time, the signal P2(k) is sent to the first output terminal 11-1.
k).

In the ADF-2, the signal P2(k) is input from the input terminal 10-2 at a time, and at the same time, the signal p3(k) is sent to the input terminal 10-3 of the ADF-3. The signal yz(k) is output to the output terminal 11-2. From then on, similar processing is performed sequentially up to ADF-3, . . . , ADF'-M. Final stage ADF-M
Then, ADF-(M-1
) The signal p sent out from the second output terminal (10-M) of
M(k) is input, and at the same time the first output terminal 11-
Output signal y, (k) to M.

ADF-M does not have a second output terminal. ADF-
1eADF-2t..., ADF-(M-1),
Each first output terminal 11-1.11 of ADF-M
-2. ..., 11-(M-1), output at 11-M yt(k) t yz(k) t...t 7M-1
(k) t 3'M(k) are added by an adder 8, and the result becomes the output y(k) of the ADF' 9 at time.

The output y(k) of the ADF 9 thus formed is subtracted from the output y(k) of the unknown system 3 by the adder 7, and a signal e(k) is output to the output terminal 2.

Next, the configuration of ADF-m(m)M) will be explained with reference to FIG. 1(b). ADF-m(m)M) consists of a first multiplier 12-m, a second-order recursive digital filter, a second-order acyclic digital filter having a zero point at a mirror image position with respect to the unit circle of this filter, and a first-order acyclic digital filter. The tail is comprised of an acyclic digital filter. The second-order cyclic digital filter includes adders 13-m and 14-m,
Multipliers 15-m and 16-m and unit delay element 19
m-1 and 19m-2. The second-order acyclic digital filter has unit delay elements 19m-1 and 19m-2.
, multipliers 17-m and 18-m, and adder 20-m
and 21-m. The first-order acyclic digital filter includes a unit delay element 19m-1, adders 23-m and 2
7-m, second multiplier 22-m, third multiplier 24-m
, a first variable coefficient multiplier 26-m, and a second variable coefficient multiplier 25-m. As shown in the figure, the input of the first-order acyclic digital filter is connected to the zero-order acyclic circuit of the second-order acyclic digital filter.

Such components are combined as follows. First, the path from the input terminal 10-m to the first output terminal 11-m is determined by the first multiplication N 12-m as shown in the figure.
, a second-order recursive digital filter, and a first-order non-recursive digital filter connected in series. On the other hand, from the input terminal 10-m to the second output terminal IQ-(
As shown in the figure, the path to K (m+1) is constituted by a cascade connection of a first multiplier 12-m, a second-order cyclic digital filter, and a second-order acyclic digital filter.

Next, the configuration of the ADF-M will be explained with reference to FIG. 1(c). The ADF-M includes a first multiplier 12-M, a second-order cyclic digital filter, and a first-order acyclic digital filter. The second-order cyclic digital filters are adders 13-M and 14-M.

Multipliers 15-M and 16-M and unit delay element 19
It is equipped with M-1 and 19M-2. The first-order acyclic digital filter includes a unit delay element 19M-1 and an adder 23-
M and 27-M, second multiplier 22-M.

Third multiplier 24-M, first variable coefficient multiplier 26-M
, and a second variable coefficient multiplier 25-M. As shown in the figure, the input of the first-order acyclic digital filter is connected to the zero-order acyclic circuit of the second-order acyclic digital filter. Input terminal 10- of this ADF-M
As shown in the figure, the path from M to the first output terminal 11-M has a cascade configuration of a first multiplier 12-M, a second-order cyclic digital filter, and a first-order acyclic digital filter. has been done.

Next, the operation of this embodiment will be explained.

First, the operation of ADF-m (m'yM) shown in FIG. 1(b) will be described. At time k, the signal p(k) sent from ADF -(m-1) is inputted to input terminal 10-m (however, in ADF-1, the signal x(k) sent from input terminal 1 is k), that is, p (lc) is input terminal 1
(input from 0-1). At the same time k, the input signal p (k) is multiplied by a coefficient ~ in a multiplier 12-m to obtain a signal tm(k) (=Qmpm(k)). At the same time k, the multiplier 15-m converts the signal url(k-1) into a
The signal amum(k-1) multiplied by m and the signal bmum(k-1) obtained by multiplying the signal um(k-2) by bm by the multiplier 16-m
) and a signal -b u (k-1) whose phase is inverted, are added by an adder 14-m to obtain a signal m v (k). The signal vm(k) and the signal tm
(k) are added at the same time to form a signal um (k). This signal u (k) becomes an input to the unit delay element 19m-1.

Signal ■m inputted to unit delay element 19m-1 at time
(k) is a unit delay as time passes, element 19m-1=
19m-2 and then shifted to Jli order. Also,
Input um to unit delay element 19m-2 at the same time k
(k-1) and the unit delay element 19 in the multiplier 22-m.
Input to m-1■ Signal RTrl which is m(k) multiplied by 3m■
After adding m(k) with the adder 23-m, the multiplier 24-m
to obtain a signal m(k) multiplied by 8m, and further multiplied by a variable coefficient dm(k) in a variable coefficient multiplier 26-m, and the resulting signal and the signal um(k) are multiplied by a variable coefficient cm(k).
) is added by the adder 27-m, and the signal ym
(k) and sends it to the output terminal 11-m.

Further, at the same time k, the signal um(k-1) is multiplied by am by the multiplier 18-m, and the output amum(k
) and the signal u
m(k-2) is added by an adder 21-m, and the output thereof and the signal obtained by multiplying the signal m(k) by bm by a multiplier 17-m are added by an adder 20-m. Output pm+1(k)
is sent to the input terminal 10-(m+1) of ADF-(m+1).

Next, the operation of the ADF-M shown in FIG. 1(e) will be explained.

At time k, the signal PM(k) sent from ADF -(M-1) is input to input terminal 10-M. At the same time k, the multiplier 12
-M is multiplied by the coefficient QM to obtain the signal tM(k). At the same time k, the signal uM(k-1) is generated by the multiplier 15-M.
The signal auuM (k-1) multiplied by 8M and the multiplier 16-M
The signal bMuM(k-
The signal -bMuM(k-1) obtained by inverting the phase of 1) is added by an adder 14-M to obtain a signal vM(k). The signal VM(k) and the signal tM(k) are added at the same time to form a signal uM(k).

This signal uM(k) becomes an input to the unit delay element 19M-1. The signal uM(k) inputted to the unit delay element 19M-1 at time changes to the unit delay element 19M as time passes.
-1 and 19M-2. Also, the input u to the unit delay element 19M-2 at the same time k
M(k-1) and the unit delay element 1 in the multiplier 22-M
Signal RxuM obtained by multiplying the input uM(k) to 9M-1 by RM
(k) by the adder 23-M, and then multiplied by the multiplier 24-M to obtain the signal 6M(k). Further, this is multiplied by a variable coefficient dM(k) in a variable coefficient multiplier 26-M, and the resulting signal and the signal uM(k) are multiplied by a variable coefficient ax(k) in a variable coefficient multiplier 25-M. The adder 27-M adds the signal yx(k) to the signal yx(k). Then, this is sent to the output terminal 11-M.

In the embodiment described above, ADF −m (m = 1
e2p...

The convergence speed of the variable coefficients is increased by orthogonalizing the input signals to each of the variable coefficient multipliers 22-m and 24-m of M) and making the root mean square values of the input signals equal to each other. . This point will be explained in detail below.

As mentioned above, in conventional ADFs, ADF-i and ADF
The inputs to the variable coefficient multiplier between ADF'-1 (where i'Ft) are orthogonal to each other as shown in equation (1) above, but ADF'-1 (m=1 y 2 e..., M
) are not orthogonal, as shown in equation (2) above. Moreover, each ADF-i (i
=1*2s...,M) of the signal φ1(k)
The root mean square values of are not equal as shown in equation (3) above.

On the other hand, in this embodiment, the variable coefficient multiplier 12-rn
, 22-rr+ and 24-m coefficients Qm p Rm
The variable coefficient multiplier 22-
The input signals to m and 24-m are made orthogonal to each other, and the root mean square values of the input signals are made equal to each other.

[Determination of Qm]

(However, each coefficient ~ is set so that m=2, 3, . . . s M ). In this case, x2(k) =
ut2(k) = u22(k) =”'= uM'
(k) ”' It can be easily confirmed that (5) is satisfied.

[Determination of Rm and Sm]

Determine so that they are equal. Specifically, Rm is =0 Yoshi It is found as

Determine Sm so that Specifically, Sm Hayoshi, ・・・・・・(7) It is found as

By doing the above, the input to the variable coefficient multiplier of ADF-m is made orthogonal to the input to the variable coefficient multiplier of ADF-n (however, m to n), and the two variable coefficient multipliers in ADF-m are made orthogonal to each other. The inputs to the coefficient multipliers are also orthogonal to each other, and the root mean square values of the inputs to all variable coefficient multipliers are equal. In this way, the correlation matrix input to the variable coefficient multiplier of ADF 9 is diagonalized.

And since the diagonal elements are equal, there is no variation in the eigenvalues of this matrix. Therefore, even if a well-known and easy-to-implement gradient method (steepest descent method, learning identification method, etc.) is used as a variable coefficient adaptive control method, the convergence speed is fast.

〔Effect of the invention〕

As explained above, according to the present invention, the inputs to each variable coefficient multiplier of the ADF are mutually orthogonalized, and the inputs to each variable coefficient multiplier are
Since the mean values are equally calculated, the effect is that the convergence speed of the variable coefficients of each variable coefficient multiplier is high.

The present invention is suitable for application to echo cancellers and the like.

[Brief explanation of drawings]

FIG. 1(,) shows the basic configuration of an embodiment of the present invention.
y diagram, Figure 1(b) is the ADF-in in Figure 1(a)
(m4M), Figure 1(c) is a circuit diagram showing the configuration of ADF-M in Figure 1(,), and Figure 2 is ADF-M.
A block diagram for explaining the identification of an unknown system using DF', and Fig. 3 is for explaining a remote conference system using ADF as an echo canceller that cancels echoes caused by acoustic coupling between a speaker and a microphone. and FIG. 4 are circuit diagrams showing examples of the configuration of a conventional ADF. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Output i-child, 3... Unknown system, 7... Adder, 8... Adder, 9... Adaptive digital filter (ADF), 10- 1.10-
2. ...slo-M...input terminal, 11-1.11
-2. ..., 11-M... first output terminal, 12
-m, 12-M...first multiplier, 19m-1-19
m-2, 19M-1*19M-2=・Unit delay element, 2
2-m, 22-M... second multiplier, 24-m t
24-M...Third multiplier, 25-m, 2
5- M = second variable coefficient multiplier, 26- m v
26-M...first variable coefficient multiplier.

Claims (1)

[Claims] M basic sections (M is an integer of 1 or more) are connected in cascade, and each of the cascaded basic sections up to (M-1) has an input terminal, a first output terminal, and having a second output terminal;
On the other hand, the M-th basic section has an input terminal and a first output terminal, the input terminal of the first basic section constitutes the signal input terminal of the adaptive digital filter, and each basic section from the second to the M-th An adaptive digital filter in which the input terminal of a section is connected to the second output terminal of the basic section immediately before it, and the sum of the signals obtained at the first output terminal of each basic section is the output of the adaptive digital filter. In the filter, a path from the input terminal of each of the M basic sections to the first output terminal is formed by a first multiplier, a second-order cyclic digital filter, and a zero-order non-linear input of the second-order cyclic digital filter. A path from the input terminal of each basic section from the 1st to the (M-1)th to the 2nd output terminal is configured by cascade connection with a first-order acyclic digital filter connected to the circuit. The first multiplier, the second-order cyclic digital filter, and the second-order acyclic digital filter are connected in cascade, and the first-order acyclic digital filter of each m-th (1≦m≦M) basic interval The digital filter receives the signal u_m(
k) multiplied by the coefficient R_m in the second multiplier and the signal u_m(k-1) from one unit time ago are added in the first adder, and the output is added by the coefficient R_m in the third multiplier. The output ■_m(k) is multiplied by the variable coefficient d_m(k) in the first variable coefficient multiplier, and the signal d_m(k)■_m(k) is multiplied by the signal u_m(k). The signal c_m(k) u_m(k
) in a second adder, and the coefficient Q_m of the first multiplier is added to two of the signals at the cascade connection point of the second-order cyclic digital filter and the second-order acyclic digital filter. Determine the root mean value to be equal to the root mean square value of the signals of the corresponding cascade connection points of other basic sections, and set the coefficient R_m of the second multiplier to the signal u_m(k).
and ■_m(k) are determined to be orthogonal, and the coefficient S_m of the third multiplier is determined such that the root mean square value of the signal u_m(k) and the root mean square value of the signal ■_m(k) are An adaptive digital filter characterized in that the filters are determined to be equal to each other.